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Started by upstream project "gerrit-osmo-e1-hardware-build" build number 101 originally caused by: Started by upstream project "gerrit-osmo-e1-hardware" build number 92 originally caused by: Triggered by Gerrit: https://gerrit.osmocom.org/c/osmo-e1-hardware/+/36677 in silent mode. Running as SYSTEM Building remotely on host2-deb11build-ansible (ttcn3 obs osmocom-gerrit osmocom-master) in workspace /home/osmocom-build/jenkins/workspace/gerrit-osmo-e1-hardware-build/JOB_TYPE/gateware/a1/default/a3/default/a4/default/label/osmocom-gerrit The recommended git tool is: NONE using credential d5eda5e9-b59d-44ba-88d2-43473cb6e42d > git rev-parse --resolve-git-dir /home/osmocom-build/jenkins/workspace/gerrit-osmo-e1-hardware-build/JOB_TYPE/gateware/a1/default/a3/default/a4/default/label/osmocom-gerrit/.git # timeout=10 Fetching changes from the remote Git repository > git config remote.origin.url ssh://jenkins@gerrit.osmocom.org:29418/osmo-e1-hardware # timeout=10 Fetching upstream changes from ssh://jenkins@gerrit.osmocom.org:29418/osmo-e1-hardware > git --version # timeout=10 > git --version # 'git version 2.30.2' using GIT_SSH to set credentials gerrit.osmocom.org Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --tags --force --progress -- ssh://jenkins@gerrit.osmocom.org:29418/osmo-e1-hardware refs/changes/77/36677/3 # timeout=10 Checking out Revision b5a7e87e14ba838d0e56d6664ad21efca18a91b3 (master) > git config core.sparsecheckout # timeout=10 > git checkout -f b5a7e87e14ba838d0e56d6664ad21efca18a91b3 # timeout=10 Commit message: "gateware/cores: Update no2e1" > git rev-parse FETCH_HEAD^{commit} # timeout=10 > git rev-list --no-walk ded31a7a8642c906fdc4474ffeaff12448589674 # timeout=10 > git remote # timeout=10 > git submodule init # timeout=10 > git submodule sync # timeout=10 > git config --get remote.origin.url # timeout=10 > git submodule init # timeout=10 > git config -f .gitmodules --get-regexp ^submodule\.(.+)\.url # timeout=10 > git config --get submodule.gateware/build.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/build.path # timeout=10 > git config --get submodule.gateware/cores/no2e1.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/cores/no2e1.path # timeout=10 > git config --get submodule.gateware/cores/no2ice40.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/cores/no2ice40.path # timeout=10 > git config --get submodule.gateware/cores/no2misc.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/cores/no2misc.path # timeout=10 > git config --get submodule.gateware/cores/no2usb.url # timeout=10 > git config -f .gitmodules --get submodule.gateware/cores/no2usb.path # timeout=10 > git submodule update --init --recursive gateware/build # timeout=10 > git submodule update --init --recursive gateware/cores/no2e1 # timeout=10 > git submodule update --init --recursive gateware/cores/no2ice40 # timeout=10 > git submodule update --init --recursive gateware/cores/no2misc # timeout=10 > git submodule update --init --recursive gateware/cores/no2usb # timeout=10 [osmocom-gerrit] $ /bin/sh -xe /tmp/jenkins7399360545090212115.sh + DOCKER_IMG=osmocom-build/debian-bookworm-build + DOCKER_IMG=registry.osmocom.org/osmocom-build/fpga-build + docker pull registry.osmocom.org/osmocom-build/fpga-build Using default tag: latest latest: Pulling from osmocom-build/fpga-build Digest: sha256:a10bc7e396b0c1300182dc546f283ac50bffe26af36f6b5727b018314ffe6db2 Status: Image is up to date for registry.osmocom.org/osmocom-build/fpga-build:latest registry.osmocom.org/osmocom-build/fpga-build:latest + docker run --rm=true --cap-add SYS_PTRACE -e ASCIIDOC_WARNINGS_CHECK=1 -e HOME=/build -e JOB_NAME=gerrit-osmo-e1-hardware-build/JOB_TYPE=gateware,a1=default,a3=default,a4=default,label=osmocom-gerrit -e MAKE=make -e OSMOPY_DEBUG_TCP_SOCKETS=1 -e OSMO_GSM_MANUALS_DIR=/opt/osmo-gsm-manuals -e PARALLEL_MAKE=-j 4 -e WITH_MANUALS=1 -w /build -i -u build -v /home/osmocom-build/jenkins/workspace/gerrit-osmo-e1-hardware-build/JOB_TYPE/gateware/a1/default/a3/default/a4/default/label/osmocom-gerrit:/build -e JOB_TYPE=gateware registry.osmocom.org/osmocom-build/fpga-build /usr/bin/timeout 30m /build/contrib/jenkins.sh =============== gateware/e1-tracer GATEWARE ============== make: Entering directory '/build/gateware/e1-tracer' make: Leaving directory '/build/gateware/e1-tracer' make: Entering directory '/build/gateware/e1-tracer' /build/gateware/cores/no2usb//utils/microcode.py > /build/gateware/e1-tracer/build-tmp/usb_trans_mc.hex cp -a /build/gateware/cores/no2usb//data/usb_ep_status.hex /build/gateware/e1-tracer/build-tmp/usb_ep_status.hex cp ../common/fw/boot.hex /build/gateware/e1-tracer/build-tmp/boot.hex cd /build/gateware/e1-tracer/build-tmp && \ yosys -s /build/gateware/e1-tracer/build-tmp/e1-tracer.ys \ -l /build/gateware/e1-tracer/build-tmp/e1-tracer.synth.rpt /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os) -- Executing script file `/build/gateware/e1-tracer/build-tmp/e1-tracer.ys' -- 1. Executing Verilog-2005 frontend: /build/gateware/e1-tracer/rtl/top.v Parsing Verilog input from `/build/gateware/e1-tracer/rtl/top.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_crc4.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_crc4.v' to AST representation. Generating RTLIL representation for module `\e1_crc4'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v' to AST representation. Generating RTLIL representation for module `\e1_rx_clock_recovery'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v' to AST representation. Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:68) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:209) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:215) is not recognized unless read_verilog is called with -sv! Generating RTLIL representation for module `\e1_rx_deframer'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_filter.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_filter.v' to AST representation. Generating RTLIL representation for module `\e1_rx_filter'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_phy.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_phy.v' to AST representation. Generating RTLIL representation for module `\e1_rx_phy'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_liu.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_liu.v' to AST representation. Generating RTLIL representation for module `\e1_rx_liu'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx.v' to AST representation. Generating RTLIL representation for module `\e1_rx'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_framer.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_framer.v' to AST representation. Generating RTLIL representation for module `\e1_tx_framer'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_phy.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_phy.v' to AST representation. Generating RTLIL representation for module `\e1_tx_phy'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_liu.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_liu.v' to AST representation. Generating RTLIL representation for module `\e1_tx_liu'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx.v' to AST representation. Generating RTLIL representation for module `\e1_tx'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v' to AST representation. Generating RTLIL representation for module `\e1_buf_if_wb'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb_rx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb_rx.v' to AST representation. Generating RTLIL representation for module `\e1_wb_rx'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb_tx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb_tx.v' to AST representation. Generating RTLIL representation for module `\e1_wb_tx'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb.v' to AST representation. Generating RTLIL representation for module `\e1_wb'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/hdb3_dec.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/hdb3_dec.v' to AST representation. Generating RTLIL representation for module `\hdb3_dec'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/hdb3_enc.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/hdb3_enc.v' to AST representation. Generating RTLIL representation for module `\hdb3_enc'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_ebr.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_ebr.v' to AST representation. Generating RTLIL representation for module `\ice40_ebr'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_i2c_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_i2c_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_i2c_wb'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_rgb_wb'. Successfully finished Verilog frontend. 22. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_spi_wb'. Successfully finished Verilog frontend. 23. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v' to AST representation. Generating RTLIL representation for module `\ice40_spram_gen'. ice40_spram_gen: (32768x32) -> 2x2 array of SPRAM Successfully finished Verilog frontend. 24. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_spram_wb'. Successfully finished Verilog frontend. 25. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_iserdes.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_iserdes.v' to AST representation. Generating RTLIL representation for module `\ice40_iserdes'. Successfully finished Verilog frontend. 26. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_oserdes.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_oserdes.v' to AST representation. Generating RTLIL representation for module `\ice40_oserdes'. Successfully finished Verilog frontend. 27. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_crg.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_crg.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_crg'. Successfully finished Verilog frontend. 28. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_dff.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_dff.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_dff'. Successfully finished Verilog frontend. 29. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_sync.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_sync.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_sync'. Successfully finished Verilog frontend. 30. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/delay.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/delay.v' to AST representation. Generating RTLIL representation for module `\delay_bit'. Generating RTLIL representation for module `\delay_bus'. Warning: Replacing memory \dl with list of registers. See /build/gateware/cores/no2misc//rtl/delay.v:59 Generating RTLIL representation for module `\delay_toggle'. Successfully finished Verilog frontend. 31. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/fifo_sync_ram.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v' to AST representation. Generating RTLIL representation for module `\fifo_sync_ram'. Successfully finished Verilog frontend. 32. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/fifo_sync_shift.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v' to AST representation. Generating RTLIL representation for module `\fifo_sync_shift'. Successfully finished Verilog frontend. 33. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/glitch_filter.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/glitch_filter.v' to AST representation. Generating RTLIL representation for module `\glitch_filter'. Successfully finished Verilog frontend. 34. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/i2c_master.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/i2c_master.v' to AST representation. Generating RTLIL representation for module `\i2c_master'. Successfully finished Verilog frontend. 35. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/i2c_master_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/i2c_master_wb.v' to AST representation. Generating RTLIL representation for module `\i2c_master_wb'. Successfully finished Verilog frontend. 36. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/muacm2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/muacm2wb.v' to AST representation. Generating RTLIL representation for module `\muacm2wb'. Successfully finished Verilog frontend. 37. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/prims.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/prims.v' to AST representation. Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:31) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:75) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:117) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:150) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:186) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:237) is not recognized unless read_verilog is called with -sv! Generating RTLIL representation for module `\lut4_n'. Generating RTLIL representation for module `\lut4_carry_n'. Generating RTLIL representation for module `\dff_n'. Generating RTLIL representation for module `\dffe_n'. Generating RTLIL representation for module `\dffer_n'. Generating RTLIL representation for module `\dffesr_n'. Successfully finished Verilog frontend. 38. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/pdm.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/pdm.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/build/gateware/cores/no2misc//rtl/pdm.v:91) Generating RTLIL representation for module `\pdm'. Generating RTLIL representation for module `\pdm_lfsr'. Successfully finished Verilog frontend. 39. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/pwm.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/pwm.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/build/gateware/cores/no2misc//rtl/pwm.v:69) Generating RTLIL representation for module `\pwm'. Successfully finished Verilog frontend. 40. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/ram_sdp.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/ram_sdp.v' to AST representation. Generating RTLIL representation for module `\ram_sdp'. Successfully finished Verilog frontend. 41. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/stream2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/stream2wb.v' to AST representation. Generating RTLIL representation for module `\stream2wb'. Successfully finished Verilog frontend. 42. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart2wb.v' to AST representation. Generating RTLIL representation for module `\uart2wb'. Successfully finished Verilog frontend. 43. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_rx.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_rx'. Successfully finished Verilog frontend. 44. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_tx.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. 45. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_wb.v' to AST representation. Generating RTLIL representation for module `\uart_wb'. Successfully finished Verilog frontend. 46. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/xclk_strobe.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/xclk_strobe.v' to AST representation. Generating RTLIL representation for module `\xclk_strobe'. Successfully finished Verilog frontend. 47. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/xclk_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/xclk_wb.v' to AST representation. Generating RTLIL representation for module `\xclk_wb'. Successfully finished Verilog frontend. 48. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb.v' to AST representation. Generating RTLIL representation for module `\usb'. Successfully finished Verilog frontend. 49. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_crc.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_crc.v' to AST representation. Generating RTLIL representation for module `\usb_crc'. Successfully finished Verilog frontend. 50. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_ep_buf.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_ep_buf.v' to AST representation. Generating RTLIL representation for module `\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 3 Successfully finished Verilog frontend. 51. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_ep_status.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_ep_status.v' to AST representation. Generating RTLIL representation for module `\usb_ep_status'. Successfully finished Verilog frontend. 52. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_phy.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_phy.v' to AST representation. Generating RTLIL representation for module `\usb_phy'. Successfully finished Verilog frontend. 53. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_rx_ll.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_rx_ll.v' to AST representation. Generating RTLIL representation for module `\usb_rx_ll'. Successfully finished Verilog frontend. 54. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_rx_pkt.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v' to AST representation. Generating RTLIL representation for module `\usb_rx_pkt'. Successfully finished Verilog frontend. 55. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_trans.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_trans.v' to AST representation. Generating RTLIL representation for module `\usb_trans'. Successfully finished Verilog frontend. 56. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_tx_ll.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_tx_ll.v' to AST representation. Generating RTLIL representation for module `\usb_tx_ll'. Successfully finished Verilog frontend. 57. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v' to AST representation. Generating RTLIL representation for module `\usb_tx_pkt'. Successfully finished Verilog frontend. 58. Executing Verilog-2005 frontend: /build/gateware/e1-tracer/rtl/misc.v Parsing Verilog input from `/build/gateware/e1-tracer/rtl/misc.v' to AST representation. Generating RTLIL representation for module `\misc'. Successfully finished Verilog frontend. 59. Executing Verilog-2005 frontend: /build/gateware/e1-tracer/rtl/sysmgr.v Parsing Verilog input from `/build/gateware/e1-tracer/rtl/sysmgr.v' to AST representation. Generating RTLIL representation for module `\sysmgr'. Successfully finished Verilog frontend. 60. Executing Verilog-2005 frontend: /build/gateware/common/rtl/capcnt.v Parsing Verilog input from `/build/gateware/common/rtl/capcnt.v' to AST representation. Generating RTLIL representation for module `\capcnt'. Successfully finished Verilog frontend. 61. Executing Verilog-2005 frontend: /build/gateware/common/rtl/capcnt_sb_mac16.v Parsing Verilog input from `/build/gateware/common/rtl/capcnt_sb_mac16.v' to AST representation. Generating RTLIL representation for module `\capcnt16_sb_mac16'. Generating RTLIL representation for module `\capcnt32_sb_mac16'. Successfully finished Verilog frontend. 62. Executing Verilog-2005 frontend: /build/gateware/common/rtl/dfu_helper.v Parsing Verilog input from `/build/gateware/common/rtl/dfu_helper.v' to AST representation. Generating RTLIL representation for module `\dfu_helper'. Successfully finished Verilog frontend. 63. Executing Verilog-2005 frontend: /build/gateware/common/rtl/picorv32.v Parsing Verilog input from `/build/gateware/common/rtl/picorv32.v' to AST representation. Generating RTLIL representation for module `\picorv32'. Generating RTLIL representation for module `\picorv32_regs'. Generating RTLIL representation for module `\picorv32_pcpi_mul'. Generating RTLIL representation for module `\picorv32_pcpi_fast_mul'. Generating RTLIL representation for module `\picorv32_pcpi_div'. Generating RTLIL representation for module `\picorv32_axi'. Generating RTLIL representation for module `\picorv32_axi_adapter'. Generating RTLIL representation for module `\picorv32_wb'. Successfully finished Verilog frontend. 64. Executing Verilog-2005 frontend: /build/gateware/common/rtl/picorv32_ice40_regs.v Parsing Verilog input from `/build/gateware/common/rtl/picorv32_ice40_regs.v' to AST representation. Generating RTLIL representation for module `\picorv32_ice40_regs'. Successfully finished Verilog frontend. 65. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_base.v Parsing Verilog input from `/build/gateware/common/rtl/soc_base.v' to AST representation. Generating RTLIL representation for module `\soc_base'. Successfully finished Verilog frontend. 66. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_bram.v Parsing Verilog input from `/build/gateware/common/rtl/soc_bram.v' to AST representation. Generating RTLIL representation for module `\soc_bram'. Successfully finished Verilog frontend. 67. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_iobuf.v Parsing Verilog input from `/build/gateware/common/rtl/soc_iobuf.v' to AST representation. Generating RTLIL representation for module `\soc_iobuf'. Successfully finished Verilog frontend. 68. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_picorv32_bridge.v Parsing Verilog input from `/build/gateware/common/rtl/soc_picorv32_bridge.v' to AST representation. Generating RTLIL representation for module `\soc_picorv32_bridge'. Successfully finished Verilog frontend. 69. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_spram.v Parsing Verilog input from `/build/gateware/common/rtl/soc_spram.v' to AST representation. Generating RTLIL representation for module `\soc_spram'. Successfully finished Verilog frontend. 70. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_arbiter.v Parsing Verilog input from `/build/gateware/common/rtl/wb_arbiter.v' to AST representation. Generating RTLIL representation for module `\wb_arbiter'. Successfully finished Verilog frontend. 71. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_dma.v Parsing Verilog input from `/build/gateware/common/rtl/wb_dma.v' to AST representation. Generating RTLIL representation for module `\wb_dma'. Successfully finished Verilog frontend. 72. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_epbuf.v Parsing Verilog input from `/build/gateware/common/rtl/wb_epbuf.v' to AST representation. Generating RTLIL representation for module `\wb_epbuf'. Successfully finished Verilog frontend. 73. Executing SYNTH_ICE40 pass. 73.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_LED_DRV_CUR'. Generating RTLIL representation for module `\SB_RGB_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\ICESTORM_RAM'. Successfully finished Verilog frontend. 73.2. Executing HIERARCHY pass (managing design hierarchy). 73.2.1. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: \ice40_spi_wb Used module: \misc Used module: \capcnt Used module: \capcnt16_sb_mac16 Used module: \dfu_helper Used module: \glitch_filter Used module: \soc_base Used module: \e1_buf_if_wb Used module: \e1_wb Used module: \e1_wb_tx Used module: \e1_tx Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: \e1_wb_rx Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: \wb_dma Used module: \wb_arbiter Used module: \wb_epbuf Used module: \ice40_spram_wb Used module: \ice40_spram_gen Used module: \xclk_strobe Used module: \xclk_wb Used module: \usb Used module: \usb_ep_status Used module: \usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: \usb_crc Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: \usb_phy Used module: \ice40_rgb_wb Used module: \uart_wb Used module: \fifo_sync_ram Used module: \ram_sdp Used module: \uart_rx Used module: \uart_tx Used module: \soc_spram Used module: \soc_bram Used module: \soc_picorv32_bridge Used module: \picorv32 Used module: \picorv32_ice40_regs Used module: \ice40_ebr Parameter \N_CS = 2 Parameter \WITH_IOB = 1 Parameter \UNIT = 1 73.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spi_wb'. Parameter \N_CS = 2 Parameter \WITH_IOB = 1 Parameter \UNIT = 1 Generating RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1'. Parameter \WB_N = 2 Parameter \E1_N = 2 Parameter \E1_UNIT_HAS_RX = 2'11 Parameter \E1_UNIT_HAS_TX = 2'00 Parameter \E1_LIU = 1 73.2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_base'. Parameter \WB_N = 2 Parameter \E1_N = 2 Parameter \E1_UNIT_HAS_RX = 2'11 Parameter \E1_UNIT_HAS_TX = 2'00 Parameter \E1_LIU = 1 Generating RTLIL representation for module `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \MFW = 7 Parameter \DW = 32 73.2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_buf_if_wb'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \MFW = 7 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\e1_buf_if_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\MFW=7\DW=32'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \LIU = 0 Parameter \MFW = 7 73.2.5. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\LIU=0\MFW=7'. Parameter \DW = 16 Parameter \AW = 12 73.2.6. Executing AST frontend in derive mode using pre-parsed AST for module `\xclk_wb'. Parameter \DW = 16 Parameter \AW = 12 Generating RTLIL representation for module `$paramod\xclk_wb\DW=16\AW=12'. Parameter \EPDW = 32 73.2.7. Executing AST frontend in derive mode using pre-parsed AST for module `\usb'. Parameter \EPDW = 32 Generating RTLIL representation for module `$paramod\usb\EPDW=32'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 73.2.8. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_rgb_wb'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Generating RTLIL representation for module `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 73.2.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 73.2.10. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spi_wb'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 Generating RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0'. Parameter \AW = 14 73.2.11. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_spram'. Parameter \AW = 14 Generating RTLIL representation for module `$paramod\soc_spram\AW=14'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 73.2.12. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_bram'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 Generating RTLIL representation for module `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram'. Parameter \WB_N = 9 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 73.2.13. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_picorv32_bridge'. Parameter \WB_N = 9 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 Generating RTLIL representation for module `$paramod\soc_picorv32_bridge\WB_N=9\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 0 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 73.2.14. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 0 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 Generating RTLIL representation for module `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32'. Parameter \W = 16 73.2.15. Executing AST frontend in derive mode using pre-parsed AST for module `\capcnt'. Parameter \W = 16 Generating RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \W = 16 Found cached RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \TIMER_WIDTH = 26 Parameter \BTN_MODE = 3 Parameter \DFU_MODE = 0 73.2.16. Executing AST frontend in derive mode using pre-parsed AST for module `\dfu_helper'. Parameter \TIMER_WIDTH = 26 Parameter \BTN_MODE = 3 Parameter \DFU_MODE = 0 Generating RTLIL representation for module `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0'. Parameter \W = 32 73.2.17. Executing AST frontend in derive mode using pre-parsed AST for module `\capcnt'. Parameter \W = 32 Generating RTLIL representation for module `$paramod\capcnt\W=32'. Parameter \LIU = 0 Parameter \MFW = 7 73.2.18. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_rx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_rx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 73.2.19. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Generating RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 73.2.20. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Generating RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \LIU = 0 Parameter \MFW = 7 73.2.21. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_tx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_tx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \LIU = 0 Parameter \MFW = 7 73.2.22. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_tx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_tx\LIU=0\MFW=7'. Parameter \LIU = 0 Parameter \MFW = 7 73.2.23. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_rx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_rx\LIU=0\MFW=7'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 73.2.24. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spram_gen'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Generating RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. ice40_spram_gen: (16384x32) -> 1x2 array of SPRAM Parameter \AWIDTH = 8 Parameter \DWIDTH = 16 73.2.25. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'. Parameter \AWIDTH = 8 Parameter \DWIDTH = 16 Generating RTLIL representation for module `$paramod\ram_sdp\AWIDTH=8\DWIDTH=16'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 73.2.26. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Generating RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 73.2.27. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_ram'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 8 Parameter \GLITCH_FILTER = 2 73.2.28. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \DIV_WIDTH = 8 Parameter \GLITCH_FILTER = 2 Generating RTLIL representation for module `$paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 8 73.2.29. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \DIV_WIDTH = 8 Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=8'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 16 Parameter \WWIDTH = 8 73.2.30. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 16 Parameter \WWIDTH = 8 Generating RTLIL representation for module `$paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf'. READ_MODE : 2 WRITE_MODE : 3 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 16 73.2.31. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 16 Generating RTLIL representation for module `$paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 2 Parameter \TARGET = 40'0100100101000011010001010011010000110000 73.2.32. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_phy'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Generating RTLIL representation for module `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 73.2.33. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_crc'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 Generating RTLIL representation for module `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 Found cached RTLIL representation for module `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101'. Parameter \WIDTH = 5 Parameter \POLY = 5'00101 Parameter \MATCH = 5'01100 73.2.34. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_crc'. Parameter \WIDTH = 5 Parameter \POLY = 5'00101 Parameter \MATCH = 5'01100 Generating RTLIL representation for module `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100'. Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 73.2.35. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 Generating RTLIL representation for module `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 73.2.36. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Generating RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. Parameter \A0W = 14 Parameter \A1W = 9 Parameter \DW = 32 73.2.37. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_dma'. Parameter \A0W = 14 Parameter \A1W = 9 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\wb_dma\A0W=14\A1W=9\DW=32'. Parameter \N = 2 Parameter \DW = 32 Parameter \AW = 9 73.2.38. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_arbiter'. Parameter \N = 2 Parameter \DW = 32 Parameter \AW = 9 Generating RTLIL representation for module `$paramod\wb_arbiter\N=2\DW=32\AW=9'. Parameter \AW = 9 Parameter \DW = 32 73.2.39. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_epbuf'. Parameter \AW = 9 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\wb_epbuf\AW=9\DW=32'. Parameter \N = 3 Parameter \DW = 32 Parameter \AW = 14 73.2.40. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_arbiter'. Parameter \N = 3 Parameter \DW = 32 Parameter \AW = 14 Generating RTLIL representation for module `$paramod\wb_arbiter\N=3\DW=32\AW=14'. Parameter \AW = 14 Parameter \DW = 32 Parameter \ZERO_RDATA = 0 73.2.41. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spram_wb'. Parameter \AW = 14 Parameter \DW = 32 Parameter \ZERO_RDATA = 0 Generating RTLIL representation for module `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0'. 73.2.42. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: \glitch_filter Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: \e1_buf_if_wb Used module: \e1_wb Used module: $paramod\e1_wb_tx\LIU=0\MFW=7 Used module: \e1_tx Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: $paramod\e1_wb_rx\LIU=0\MFW=7 Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: \ice40_spram_gen Used module: \xclk_strobe Used module: \xclk_wb Used module: \usb Used module: \usb_ep_status Used module: $paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf Used module: $paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: \ice40_rgb_wb Used module: \uart_wb Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: \ram_sdp Used module: $paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2 Used module: $paramod\uart_tx\DIV_WIDTH=8 Used module: \ice40_spi_wb Used module: \soc_spram Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \soc_bram Used module: \soc_picorv32_bridge Used module: \picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 Found cached RTLIL representation for module `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'11 Parameter \UNIT_HAS_TX = 2'00 Parameter \MFW = 7 Parameter \DW = 32 73.2.43. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_buf_if_wb'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'11 Parameter \UNIT_HAS_TX = 2'00 Parameter \MFW = 7 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32'. Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:176 Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:175 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'11 Parameter \UNIT_HAS_TX = 2'00 Parameter \LIU = 1 Parameter \MFW = 7 73.2.44. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'11 Parameter \UNIT_HAS_TX = 2'00 Parameter \LIU = 1 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7'. Parameter \DW = 16 Parameter \AW = 12 Found cached RTLIL representation for module `$paramod\xclk_wb\DW=16\AW=12'. Parameter \EPDW = 32 Found cached RTLIL representation for module `$paramod\usb\EPDW=32'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Found cached RTLIL representation for module `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Found cached RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 Found cached RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0'. Parameter \AW = 14 Found cached RTLIL representation for module `$paramod\soc_spram\AW=14'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 Found cached RTLIL representation for module `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram'. Parameter \WB_N = 10 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 73.2.45. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_picorv32_bridge'. Parameter \WB_N = 10 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 Generating RTLIL representation for module `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 0 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 Found cached RTLIL representation for module `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_tx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_rx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \AWIDTH = 9 Parameter \DWIDTH = 8 73.2.46. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'. Parameter \AWIDTH = 9 Parameter \DWIDTH = 8 Generating RTLIL representation for module `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Found cached RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. 73.2.47. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7 Used module: \e1_wb_rx Used module: $paramod\e1_rx\LIU=0\MFW=7 Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: \usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: \usb_phy Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: \fifo_sync_ram Used module: $paramod\ram_sdp\AWIDTH=8\DWIDTH=16 Used module: \uart_rx Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: \uart_tx Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: \ice40_spram_gen Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 32 Parameter \WWIDTH = 8 73.2.48. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 32 Parameter \WWIDTH = 8 Generating RTLIL representation for module `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf'. READ_MODE : 1 WRITE_MODE : 3 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 32 73.2.49. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 32 Generating RTLIL representation for module `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 1 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Found cached RTLIL representation for module `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 12 Parameter \GLITCH_FILTER = 2 73.2.50. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \DIV_WIDTH = 12 Parameter \GLITCH_FILTER = 2 Generating RTLIL representation for module `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 12 73.2.51. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \DIV_WIDTH = 12 Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=12'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. Parameter \LIU = 1 Parameter \MFW = 7 73.2.52. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_rx'. Parameter \LIU = 1 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_rx\LIU=1\MFW=7'. Parameter \LIU = 1 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_wb_rx\LIU=1\MFW=7'. 73.2.53. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7 Used module: $paramod\e1_wb_rx\LIU=1\MFW=7 Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: \glitch_filter Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Found cached RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \LIU = 1 Parameter \MFW = 7 73.2.54. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_rx'. Parameter \LIU = 1 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_rx\LIU=1\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. 73.2.55. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7 Used module: $paramod\e1_wb_rx\LIU=1\MFW=7 Used module: $paramod\e1_rx\LIU=1\MFW=7 Used module: \e1_rx_liu Used module: \e1_rx_deframer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr 73.2.56. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1 Used module: \misc Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7 Used module: $paramod\e1_wb_rx\LIU=1\MFW=7 Used module: $paramod\e1_rx\LIU=1\MFW=7 Used module: \e1_rx_liu Used module: \e1_rx_deframer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Removing unused module `$paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf'. Removing unused module `$paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf'. Removing unused module `$paramod\uart_tx\DIV_WIDTH=8'. Removing unused module `$paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2'. Removing unused module `$paramod\ram_sdp\AWIDTH=8\DWIDTH=16'. Removing unused module `$paramod\e1_wb_rx\LIU=0\MFW=7'. Removing unused module `$paramod\e1_wb_tx\LIU=0\MFW=7'. Removing unused module `$paramod\e1_tx\LIU=0\MFW=7'. Removing unused module `$paramod\e1_rx\LIU=0\MFW=7'. Removing unused module `$paramod\soc_picorv32_bridge\WB_N=9\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Removing unused module `$paramod\e1_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\LIU=0\MFW=7'. Removing unused module `$paramod\e1_buf_if_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\MFW=7\DW=32'. Removing unused module `\wb_epbuf'. Removing unused module `\wb_dma'. Removing unused module `\wb_arbiter'. Removing unused module `\soc_spram'. Removing unused module `\soc_picorv32_bridge'. Removing unused module `\soc_bram'. Removing unused module `\soc_base'. Removing unused module `\picorv32_wb'. Removing unused module `\picorv32_axi_adapter'. Removing unused module `\picorv32_axi'. Removing unused module `\picorv32_pcpi_div'. Removing unused module `\picorv32_pcpi_fast_mul'. Removing unused module `\picorv32_pcpi_mul'. Removing unused module `\picorv32_regs'. Removing unused module `\picorv32'. Removing unused module `\dfu_helper'. Removing unused module `\capcnt'. Removing unused module `\usb_phy'. Removing unused module `\usb_ep_buf'. Removing unused module `\usb_crc'. Removing unused module `\usb'. Removing unused module `\xclk_wb'. Removing unused module `\uart_wb'. Removing unused module `\uart_tx'. Removing unused module `\uart_rx'. Removing unused module `\uart2wb'. Removing unused module `\stream2wb'. Removing unused module `\ram_sdp'. Removing unused module `\pwm'. Removing unused module `\pdm_lfsr'. Removing unused module `\pdm'. Removing unused module `\dffesr_n'. Removing unused module `\dffer_n'. Removing unused module `\dffe_n'. Removing unused module `\dff_n'. Removing unused module `\lut4_carry_n'. Removing unused module `\lut4_n'. Removing unused module `\muacm2wb'. Removing unused module `\i2c_master_wb'. Removing unused module `\i2c_master'. Removing unused module `\glitch_filter'. Removing unused module `\fifo_sync_shift'. Removing unused module `\fifo_sync_ram'. Removing unused module `\delay_bus'. Removing unused module `\delay_bit'. Removing unused module `\ice40_serdes_sync'. Removing unused module `\ice40_serdes_dff'. Removing unused module `\ice40_serdes_crg'. Removing unused module `\ice40_oserdes'. Removing unused module `\ice40_iserdes'. Removing unused module `\ice40_spram_wb'. Removing unused module `\ice40_spram_gen'. Removing unused module `\ice40_spi_wb'. Removing unused module `\ice40_rgb_wb'. Removing unused module `\ice40_i2c_wb'. Removing unused module `\ice40_ebr'. Removing unused module `\hdb3_enc'. Removing unused module `\hdb3_dec'. Removing unused module `\e1_wb'. Removing unused module `\e1_wb_tx'. Removing unused module `\e1_wb_rx'. Removing unused module `\e1_buf_if_wb'. Removing unused module `\e1_tx'. Removing unused module `\e1_tx_liu'. Removing unused module `\e1_tx_phy'. Removing unused module `\e1_tx_framer'. Removing unused module `\e1_rx'. Removing unused module `\e1_rx_phy'. Removing unused module `\e1_rx_filter'. Removing unused module `\e1_rx_clock_recovery'. Removed 82 unused modules. 73.3. Executing PROC pass (convert processes to netlists). 73.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5228'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4480'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5173'. Found and cleaned up 1 empty switch in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4095'. Found and cleaned up 15 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. Found and cleaned up 1 empty switch in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3897'. Found and cleaned up 6 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:530$3543'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:530$3543'. Found and cleaned up 1 empty switch in `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:0$3349'. Removing empty process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:0$3349'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:471$3218'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:471$3218'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$137'. Cleaned up 26 empty switches. 73.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2914 in module SB_DFFNSR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2906 in module SB_DFFES. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2899 in module SB_DFFESS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2895 in module SB_DFFER. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2888 in module SB_DFFESR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2885 in module SB_DFFS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2882 in module SB_DFFSS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2879 in module SB_DFFR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2876 in module SB_DFFSR. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_epbuf.v:51$4858 in module $paramod\wb_epbuf\AW=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:116$4847 in module $paramod\wb_arbiter\N=2\DW=32\AW=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:80$4837 in module $paramod\wb_arbiter\N=2\DW=32\AW=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:190$4805 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:98$4766 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:92$4765 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:86$4761 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4737 in module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4733 in module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4729 in module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4721 in module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Removed 2 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4682 in module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4682 in module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:203$5312 in module $paramod\e1_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:188$5302 in module $paramod\e1_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:247$5292 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:240$5290 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5272 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5271 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5263 in module $paramod\e1_wb_rx\LIU=1\MFW=7. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5261 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5258 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5254 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5250 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5240 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5236 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5232 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4533 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4527 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4525 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4516 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4510 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4504 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4500 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4496 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4488 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 16 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323 in module $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1595 in module sysmgr. Marked 1 switch rules as full_case in process $proc$/build/gateware/e1-tracer/rtl/misc.v:116$1593 in module misc. Marked 2 switch rules as full_case in process $proc$/build/gateware/e1-tracer/rtl/misc.v:73$1592 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/e1-tracer/rtl/misc.v:66$1588 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1547 in module usb_tx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1531 in module usb_tx_pkt. Marked 8 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1529 in module usb_tx_pkt. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1526 in module usb_tx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1526 in module usb_tx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1504 in module usb_tx_ll. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1498 in module usb_tx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1494 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1483 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1467 in module usb_trans. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1452 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1449 in module usb_trans. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1444 in module usb_trans. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1433 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1428 in module usb_trans. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1425 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1425 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1416 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1407 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1344 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1341 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1338 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1335 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1325 in module usb_rx_pkt. Marked 18 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1309 in module usb_rx_pkt. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1304 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1304 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1303 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1302 in module usb_rx_ll. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1286 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1286 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1276 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5107 in module $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4207 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4205 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4196 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4194 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4185 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4183 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4174 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4172 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4161 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4159 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4150 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4148 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4139 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4137 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4128 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4126 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5033 in module $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1104 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1103 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1101 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:149$4104 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:120$4095 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:109$4091 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:103$4089 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Marked 37 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1375$3911 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1288$3883 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1274$3878 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 8 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1165$3843 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 3 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:840$3583 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 3 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:791$3581 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:760$3577 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 47 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:684$3576 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 4 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:549$3552 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:414$3514 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Removed 2 dead cases from process $proc$/build/gateware/common/rtl/picorv32.v:385$3511 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:385$3511 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:374$3506 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:309$3432 in module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5008 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5002 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4991 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4953 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4951 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3311 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3301 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3284 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3279 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3272 in module $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3266 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3258 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3254 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3250 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3246 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3232 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3219 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3217 in module $paramod\usb\EPDW=32. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3213 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3195 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3191 in module $paramod\xclk_wb\DW=16\AW=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3184 in module $paramod\xclk_wb\DW=16\AW=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4922 in module $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:116$4901 in module $paramod\wb_arbiter\N=3\DW=32\AW=14. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:80$4889 in module $paramod\wb_arbiter\N=3\DW=32\AW=14. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/soc_base.v:185$3095 in module $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2944 in module SB_DFFNES. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2937 in module SB_DFFNESS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2933 in module SB_DFFNER. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2926 in module SB_DFFNESR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2923 in module SB_DFFNS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2920 in module SB_DFFNSS. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$143 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$137 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$111 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$91 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$69 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$57 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$53 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$49 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$39 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$35 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$31 in module e1_rx_deframer. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$23 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$21 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$16 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2917 in module SB_DFFNR. Removed a total of 8 dead cases. 73.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 121 redundant assignments. Promoted 277 assignments to connections. 73.3.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2916'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2913'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2911'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2909'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2905'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2898'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2894'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2887'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2884'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2881'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2878'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2875'. Set init value: \Q = 1'0 Found init rule in `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2873'. Set init value: \Q = 1'0 Found init rule in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1308'. Set init value: \dec_sym_1 = 2'00 Found init rule in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2947'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2943'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2936'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2932'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2925'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2922'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2919'. Set init value: \Q = 1'0 73.3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \S in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2906'. Found async reset \R in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2895'. Found async reset \S in `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2885'. Found async reset \R in `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2879'. Found async reset \rst in `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$4858'. Found async reset \rst in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4847'. Found async reset \rst in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4837'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4805'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$4765'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$4761'. Found async reset \rst in `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4682'. Found async reset \rst in `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:203$5312'. Found async reset \rst in `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:188$5302'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:247$5292'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:240$5290'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5271'. Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5261'. Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5250'. Found async reset \rst in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5232'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4533'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4527'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4525'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4516'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4510'. Found async reset \pll_lock in `\sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1595'. Found async reset \rst in `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:116$1593'. Found async reset \rst in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1531'. Found async reset \rst in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1526'. Found async reset \ll_start in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1504'. Found async reset \rst in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1498'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1467'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1449'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1444'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1433'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1428'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1416'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1407'. Found async reset \rst in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1325'. Found async reset \rst in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1276'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4207'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4205'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4196'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4194'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4185'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4183'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4174'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4172'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4161'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4159'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4150'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4148'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4139'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4137'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4128'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4126'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1104'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1103'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1101'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4104'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4095'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4091'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4089'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5008'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5002'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4953'. Found async reset \rst in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3279'. Found async reset \rst in `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3272'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3266'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3254'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3232'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3217'. Found async reset \rst in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3191'. Found async reset \rst in `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4922'. Found async reset \rst in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4901'. Found async reset \rst in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4889'. Found async reset \rst_sys in `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3095'. Found async reset \S in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2944'. Found async reset \R in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2933'. Found async reset \S in `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2923'. Found async reset \R in `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2917'. 73.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2916'. Creating decoders for process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2914'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2913'. Creating decoders for process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$2912'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2911'. Creating decoders for process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$2910'. Creating decoders for process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2909'. Creating decoders for process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2906'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2905'. Creating decoders for process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2899'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2898'. Creating decoders for process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2895'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2894'. Creating decoders for process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2888'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2887'. Creating decoders for process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2885'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2884'. Creating decoders for process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2882'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2881'. Creating decoders for process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2879'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2878'. Creating decoders for process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2876'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2875'. Creating decoders for process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2874'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2873'. Creating decoders for process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2872'. Creating decoders for process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$4858'. 1/1: $0\ack_i[0:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4847'. 1/2: $0\busy[0:0] 2/2: $0\sel[1:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4840'. 1/2: $0\sel_nxt[1:0] [1] 2/2: $0\sel_nxt[1:0] [0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4837'. 1/4: $0\m_wmsk[3:0] 2/4: $0\m_we[0:0] 3/4: $0\m_wdata[31:0] 4/4: $0\m_addr[8:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4824'. Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4805'. 1/3: $0\ctl_ack_i[0:0] 2/3: $0\ctl_do_read[0:0] 3/3: $0\ctl_do_write[0:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$4801'. 1/1: $0\dir[0:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$4798'. 1/1: $0\len[12:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$4788'. 1/1: $0\m1_addr_i[8:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$4784'. 1/1: $0\m0_addr_i[13:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$4782'. 1/1: $0\data_reg[31:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$4766'. 1/1: $0\state_nxt[1:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$4765'. 1/1: $0\state[1:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$4761'. 1/1: $0\go[0:0] Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4757'. Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4753'. Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4749'. Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4742'. Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4737'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4733'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4729'. 1/1: $0\cnt[3:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4721'. 1/2: $2\cnt_move[3:0] 2/2: $1\cnt_move[3:0] Creating decoders for process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4719'. 1/1: $0\state[4:0] Creating decoders for process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4706'. 1/1: $0\state[15:0] Creating decoders for process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4682'. 1/2: $0\dn_state[2:0] 2/2: $0\dp_state[2:0] Creating decoders for process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:203$5312'. 1/1: $0\bd_crc_e[1:0] Creating decoders for process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:196$5306'. Creating decoders for process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:188$5302'. 1/1: $0\mf_valid[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:254$5296'. Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:247$5292'. 1/1: $0\rx_overflow[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:240$5290'. 1/1: $0\rx_rst[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5272'. 1/2: $0\bro_rden[0:0] 2/2: $0\bri_wren[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5271'. 1/2: $0\rx_mode[1:0] 2/2: $0\rx_enabled[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5263'. 1/2: $0\crx_clear[0:0] 2/2: $0\crx_wren[0:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5262'. Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5261'. 1/1: $0\shift[9:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5258'. 1/1: $0\bit_cnt[4:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5254'. 1/1: $0\div_cnt[12:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5250'. 1/1: $0\active[0:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5244'. Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5243'. 1/1: $0\shift[8:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5240'. 1/1: $0\bit_cnt[4:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5236'. 1/1: $0\div_cnt[12:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5232'. 1/1: $0\active[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4533'. 1/1: $0\rd_valid[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4527'. 1/1: $0\ram_rd_addr[8:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4525'. 1/1: $0\ram_wr_addr[8:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4516'. 1/1: $0\full[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4510'. 1/1: $0\level[9:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4509'. Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4504'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4500'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4496'. 1/1: $0\cnt[1:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4488'. 1/2: $2\cnt_move[1:0] 2/2: $1\cnt_move[1:0] Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5224'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5220'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5216'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5212'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5208'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5204'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5200'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5196'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5192'. Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4479'. Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323'. 1/320: $8\mem_dm_w[7:0] [7] 2/320: $8\mem_dm_w[7:0] [4] 3/320: $8\mem_dm_w[7:0] [2] 4/320: $8\mem_dm_w[7:0] [0] 5/320: $8\mem_dm_w[7:0] [6] 6/320: $8\mem_dm_w[7:0] [1] 7/320: $8\mem_dm_w[7:0] [3] 8/320: $8\mem_dm_w[7:0] [5] 9/320: $8\mem_di_w[31:0] [31] 10/320: $8\mem_di_w[31:0] [24] 11/320: $8\mem_di_w[31:0] [22] 12/320: $8\mem_di_w[31:0] [20] 13/320: $8\mem_di_w[31:0] [18] 14/320: $8\mem_di_w[31:0] [16] 15/320: $8\mem_di_w[31:0] [14] 16/320: $8\mem_di_w[31:0] [12] 17/320: $8\mem_di_w[31:0] [10] 18/320: $8\mem_di_w[31:0] [8] 19/320: $8\mem_di_w[31:0] [6] 20/320: $8\mem_di_w[31:0] [4] 21/320: $8\mem_di_w[31:0] [2] 22/320: $8\mem_di_w[31:0] [0] 23/320: $8\mem_di_w[31:0] [30] 24/320: $8\mem_di_w[31:0] [27] 25/320: $8\mem_di_w[31:0] [23] 26/320: $8\mem_di_w[31:0] [21] 27/320: $8\mem_di_w[31:0] [17] 28/320: $8\mem_di_w[31:0] [13] 29/320: $8\mem_di_w[31:0] [9] 30/320: $8\mem_di_w[31:0] [5] 31/320: $8\mem_di_w[31:0] [1] 32/320: $8\mem_di_w[31:0] [28] 33/320: $8\mem_di_w[31:0] [26] 34/320: $8\mem_di_w[31:0] [15] 35/320: $8\mem_di_w[31:0] [3] 36/320: $8\mem_di_w[31:0] [7] 37/320: $8\mem_di_w[31:0] [25] 38/320: $8\mem_di_w[31:0] [19] 39/320: $8\mem_di_w[31:0] [29] 40/320: $8\mem_di_w[31:0] [11] 41/320: $7\mem_dm_w[7:0] [7] 42/320: $7\mem_dm_w[7:0] [4] 43/320: $7\mem_dm_w[7:0] [2] 44/320: $7\mem_dm_w[7:0] [0] 45/320: $7\mem_dm_w[7:0] [6] 46/320: $7\mem_dm_w[7:0] [1] 47/320: $7\mem_dm_w[7:0] [3] 48/320: $7\mem_dm_w[7:0] [5] 49/320: $7\mem_di_w[31:0] [31] 50/320: $7\mem_di_w[31:0] [24] 51/320: $7\mem_di_w[31:0] [22] 52/320: $7\mem_di_w[31:0] [20] 53/320: $7\mem_di_w[31:0] [18] 54/320: $7\mem_di_w[31:0] [16] 55/320: $7\mem_di_w[31:0] [14] 56/320: $7\mem_di_w[31:0] [12] 57/320: $7\mem_di_w[31:0] [10] 58/320: $7\mem_di_w[31:0] [8] 59/320: $7\mem_di_w[31:0] [6] 60/320: $7\mem_di_w[31:0] [4] 61/320: $7\mem_di_w[31:0] [2] 62/320: $7\mem_di_w[31:0] [0] 63/320: $7\mem_di_w[31:0] [30] 64/320: $7\mem_di_w[31:0] [27] 65/320: $7\mem_di_w[31:0] [23] 66/320: $7\mem_di_w[31:0] [21] 67/320: $7\mem_di_w[31:0] [17] 68/320: $7\mem_di_w[31:0] [13] 69/320: $7\mem_di_w[31:0] [9] 70/320: $7\mem_di_w[31:0] [5] 71/320: $7\mem_di_w[31:0] [1] 72/320: $7\mem_di_w[31:0] [28] 73/320: $7\mem_di_w[31:0] [26] 74/320: $7\mem_di_w[31:0] [15] 75/320: $7\mem_di_w[31:0] [3] 76/320: $7\mem_di_w[31:0] [7] 77/320: $7\mem_di_w[31:0] [25] 78/320: $7\mem_di_w[31:0] [19] 79/320: $7\mem_di_w[31:0] [29] 80/320: $7\mem_di_w[31:0] [11] 81/320: $6\mem_dm_w[7:0] [7] 82/320: $6\mem_dm_w[7:0] [4] 83/320: $6\mem_dm_w[7:0] [2] 84/320: $6\mem_dm_w[7:0] [0] 85/320: $6\mem_dm_w[7:0] [6] 86/320: $6\mem_dm_w[7:0] [1] 87/320: $6\mem_dm_w[7:0] [3] 88/320: $6\mem_dm_w[7:0] [5] 89/320: $6\mem_di_w[31:0] [31] 90/320: $6\mem_di_w[31:0] [24] 91/320: $6\mem_di_w[31:0] [22] 92/320: $6\mem_di_w[31:0] [20] 93/320: $6\mem_di_w[31:0] [18] 94/320: $6\mem_di_w[31:0] [16] 95/320: $6\mem_di_w[31:0] [14] 96/320: $6\mem_di_w[31:0] [12] 97/320: $6\mem_di_w[31:0] [10] 98/320: $6\mem_di_w[31:0] [8] 99/320: $6\mem_di_w[31:0] [6] 100/320: $6\mem_di_w[31:0] [4] 101/320: $6\mem_di_w[31:0] [2] 102/320: $6\mem_di_w[31:0] [0] 103/320: $6\mem_di_w[31:0] [30] 104/320: $6\mem_di_w[31:0] [27] 105/320: $6\mem_di_w[31:0] [23] 106/320: $6\mem_di_w[31:0] [21] 107/320: $6\mem_di_w[31:0] [17] 108/320: $6\mem_di_w[31:0] [13] 109/320: $6\mem_di_w[31:0] [9] 110/320: $6\mem_di_w[31:0] [5] 111/320: $6\mem_di_w[31:0] [1] 112/320: $6\mem_di_w[31:0] [28] 113/320: $6\mem_di_w[31:0] [26] 114/320: $6\mem_di_w[31:0] [15] 115/320: $6\mem_di_w[31:0] [3] 116/320: $6\mem_di_w[31:0] [7] 117/320: $6\mem_di_w[31:0] [25] 118/320: $6\mem_di_w[31:0] [19] 119/320: $6\mem_di_w[31:0] [29] 120/320: $6\mem_di_w[31:0] [11] 121/320: $5\mem_dm_w[7:0] [7] 122/320: $5\mem_dm_w[7:0] [4] 123/320: $5\mem_dm_w[7:0] [2] 124/320: $5\mem_dm_w[7:0] [0] 125/320: $5\mem_dm_w[7:0] [6] 126/320: $5\mem_dm_w[7:0] [1] 127/320: $5\mem_dm_w[7:0] [3] 128/320: $5\mem_dm_w[7:0] [5] 129/320: $5\mem_di_w[31:0] [31] 130/320: $5\mem_di_w[31:0] [24] 131/320: $5\mem_di_w[31:0] [22] 132/320: $5\mem_di_w[31:0] [20] 133/320: $5\mem_di_w[31:0] [18] 134/320: $5\mem_di_w[31:0] [16] 135/320: $5\mem_di_w[31:0] [14] 136/320: $5\mem_di_w[31:0] [12] 137/320: $5\mem_di_w[31:0] [10] 138/320: $5\mem_di_w[31:0] [8] 139/320: $5\mem_di_w[31:0] [6] 140/320: $5\mem_di_w[31:0] [4] 141/320: $5\mem_di_w[31:0] [2] 142/320: $5\mem_di_w[31:0] [0] 143/320: $5\mem_di_w[31:0] [30] 144/320: $5\mem_di_w[31:0] [27] 145/320: $5\mem_di_w[31:0] [23] 146/320: $5\mem_di_w[31:0] [21] 147/320: $5\mem_di_w[31:0] [17] 148/320: $5\mem_di_w[31:0] [13] 149/320: $5\mem_di_w[31:0] [9] 150/320: $5\mem_di_w[31:0] [5] 151/320: $5\mem_di_w[31:0] [1] 152/320: $5\mem_di_w[31:0] [28] 153/320: $5\mem_di_w[31:0] [26] 154/320: $5\mem_di_w[31:0] [15] 155/320: $5\mem_di_w[31:0] [3] 156/320: $5\mem_di_w[31:0] [7] 157/320: $5\mem_di_w[31:0] [25] 158/320: $5\mem_di_w[31:0] [19] 159/320: $5\mem_di_w[31:0] [29] 160/320: $5\mem_di_w[31:0] [11] 161/320: $4\mem_dm_w[7:0] [7] 162/320: $4\mem_dm_w[7:0] [4] 163/320: $4\mem_dm_w[7:0] [2] 164/320: $4\mem_dm_w[7:0] [0] 165/320: $4\mem_dm_w[7:0] [6] 166/320: $4\mem_dm_w[7:0] [1] 167/320: $4\mem_dm_w[7:0] [3] 168/320: $4\mem_dm_w[7:0] [5] 169/320: $4\mem_di_w[31:0] [31] 170/320: $4\mem_di_w[31:0] [24] 171/320: $4\mem_di_w[31:0] [22] 172/320: $4\mem_di_w[31:0] [20] 173/320: $4\mem_di_w[31:0] [18] 174/320: $4\mem_di_w[31:0] [16] 175/320: $4\mem_di_w[31:0] [14] 176/320: $4\mem_di_w[31:0] [12] 177/320: $4\mem_di_w[31:0] [10] 178/320: $4\mem_di_w[31:0] [8] 179/320: $4\mem_di_w[31:0] [6] 180/320: $4\mem_di_w[31:0] [4] 181/320: $4\mem_di_w[31:0] [2] 182/320: $4\mem_di_w[31:0] [0] 183/320: $4\mem_di_w[31:0] [30] 184/320: $4\mem_di_w[31:0] [27] 185/320: $4\mem_di_w[31:0] [23] 186/320: $4\mem_di_w[31:0] [21] 187/320: $4\mem_di_w[31:0] [17] 188/320: $4\mem_di_w[31:0] [13] 189/320: $4\mem_di_w[31:0] [9] 190/320: $4\mem_di_w[31:0] [5] 191/320: $4\mem_di_w[31:0] [1] 192/320: $4\mem_di_w[31:0] [28] 193/320: $4\mem_di_w[31:0] [26] 194/320: $4\mem_di_w[31:0] [15] 195/320: $4\mem_di_w[31:0] [3] 196/320: $4\mem_di_w[31:0] [7] 197/320: $4\mem_di_w[31:0] [25] 198/320: $4\mem_di_w[31:0] [19] 199/320: $4\mem_di_w[31:0] [29] 200/320: $4\mem_di_w[31:0] [11] 201/320: $3\mem_dm_w[7:0] [7] 202/320: $3\mem_dm_w[7:0] [4] 203/320: $3\mem_dm_w[7:0] [2] 204/320: $3\mem_dm_w[7:0] [0] 205/320: $3\mem_dm_w[7:0] [6] 206/320: $3\mem_dm_w[7:0] [1] 207/320: $3\mem_dm_w[7:0] [3] 208/320: $3\mem_dm_w[7:0] [5] 209/320: $3\mem_di_w[31:0] [31] 210/320: $3\mem_di_w[31:0] [24] 211/320: $3\mem_di_w[31:0] [22] 212/320: $3\mem_di_w[31:0] [20] 213/320: $3\mem_di_w[31:0] [18] 214/320: $3\mem_di_w[31:0] [16] 215/320: $3\mem_di_w[31:0] [14] 216/320: $3\mem_di_w[31:0] [12] 217/320: $3\mem_di_w[31:0] [10] 218/320: $3\mem_di_w[31:0] [8] 219/320: $3\mem_di_w[31:0] [6] 220/320: $3\mem_di_w[31:0] [4] 221/320: $3\mem_di_w[31:0] [2] 222/320: $3\mem_di_w[31:0] [0] 223/320: $3\mem_di_w[31:0] [30] 224/320: $3\mem_di_w[31:0] [27] 225/320: $3\mem_di_w[31:0] [23] 226/320: $3\mem_di_w[31:0] [21] 227/320: $3\mem_di_w[31:0] [17] 228/320: $3\mem_di_w[31:0] [13] 229/320: $3\mem_di_w[31:0] [9] 230/320: $3\mem_di_w[31:0] [5] 231/320: $3\mem_di_w[31:0] [1] 232/320: $3\mem_di_w[31:0] [28] 233/320: $3\mem_di_w[31:0] [26] 234/320: $3\mem_di_w[31:0] [15] 235/320: $3\mem_di_w[31:0] [3] 236/320: $3\mem_di_w[31:0] [7] 237/320: $3\mem_di_w[31:0] [25] 238/320: $3\mem_di_w[31:0] [19] 239/320: $3\mem_di_w[31:0] [29] 240/320: $3\mem_di_w[31:0] [11] 241/320: $2\mem_dm_w[7:0] [7] 242/320: $2\mem_dm_w[7:0] [4] 243/320: $2\mem_dm_w[7:0] [2] 244/320: $2\mem_dm_w[7:0] [0] 245/320: $2\mem_dm_w[7:0] [6] 246/320: $2\mem_dm_w[7:0] [1] 247/320: $2\mem_dm_w[7:0] [3] 248/320: $2\mem_dm_w[7:0] [5] 249/320: $2\mem_di_w[31:0] [31] 250/320: $2\mem_di_w[31:0] [24] 251/320: $2\mem_di_w[31:0] [22] 252/320: $2\mem_di_w[31:0] [20] 253/320: $2\mem_di_w[31:0] [18] 254/320: $2\mem_di_w[31:0] [16] 255/320: $2\mem_di_w[31:0] [14] 256/320: $2\mem_di_w[31:0] [12] 257/320: $2\mem_di_w[31:0] [10] 258/320: $2\mem_di_w[31:0] [8] 259/320: $2\mem_di_w[31:0] [6] 260/320: $2\mem_di_w[31:0] [4] 261/320: $2\mem_di_w[31:0] [2] 262/320: $2\mem_di_w[31:0] [0] 263/320: $2\mem_di_w[31:0] [30] 264/320: $2\mem_di_w[31:0] [27] 265/320: $2\mem_di_w[31:0] [23] 266/320: $2\mem_di_w[31:0] [21] 267/320: $2\mem_di_w[31:0] [17] 268/320: $2\mem_di_w[31:0] [13] 269/320: $2\mem_di_w[31:0] [9] 270/320: $2\mem_di_w[31:0] [5] 271/320: $2\mem_di_w[31:0] [1] 272/320: $2\mem_di_w[31:0] [28] 273/320: $2\mem_di_w[31:0] [26] 274/320: $2\mem_di_w[31:0] [15] 275/320: $2\mem_di_w[31:0] [3] 276/320: $2\mem_di_w[31:0] [7] 277/320: $2\mem_di_w[31:0] [25] 278/320: $2\mem_di_w[31:0] [19] 279/320: $2\mem_di_w[31:0] [29] 280/320: $2\mem_di_w[31:0] [11] 281/320: $1\mem_dm_w[7:0] [7] 282/320: $1\mem_dm_w[7:0] [4] 283/320: $1\mem_dm_w[7:0] [2] 284/320: $1\mem_dm_w[7:0] [0] 285/320: $1\mem_dm_w[7:0] [6] 286/320: $1\mem_dm_w[7:0] [1] 287/320: $1\mem_dm_w[7:0] [3] 288/320: $1\mem_dm_w[7:0] [5] 289/320: $1\mem_di_w[31:0] [31] 290/320: $1\mem_di_w[31:0] [24] 291/320: $1\mem_di_w[31:0] [22] 292/320: $1\mem_di_w[31:0] [20] 293/320: $1\mem_di_w[31:0] [18] 294/320: $1\mem_di_w[31:0] [16] 295/320: $1\mem_di_w[31:0] [14] 296/320: $1\mem_di_w[31:0] [12] 297/320: $1\mem_di_w[31:0] [10] 298/320: $1\mem_di_w[31:0] [8] 299/320: $1\mem_di_w[31:0] [6] 300/320: $1\mem_di_w[31:0] [4] 301/320: $1\mem_di_w[31:0] [2] 302/320: $1\mem_di_w[31:0] [0] 303/320: $1\mem_di_w[31:0] [30] 304/320: $1\mem_di_w[31:0] [27] 305/320: $1\mem_di_w[31:0] [23] 306/320: $1\mem_di_w[31:0] [21] 307/320: $1\mem_di_w[31:0] [17] 308/320: $1\mem_di_w[31:0] [13] 309/320: $1\mem_di_w[31:0] [9] 310/320: $1\mem_di_w[31:0] [5] 311/320: $1\mem_di_w[31:0] [1] 312/320: $1\mem_di_w[31:0] [28] 313/320: $1\mem_di_w[31:0] [26] 314/320: $1\mem_di_w[31:0] [15] 315/320: $1\mem_di_w[31:0] [3] 316/320: $1\mem_di_w[31:0] [7] 317/320: $1\mem_di_w[31:0] [25] 318/320: $1\mem_di_w[31:0] [19] 319/320: $1\mem_di_w[31:0] [29] 320/320: $1\mem_di_w[31:0] [11] Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4322'. 1/1: $0\addr_r[13:0] Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5169'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5165'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5161'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5157'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5153'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5149'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5145'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5141'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5137'. Creating decoders for process `\sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1595'. 1/1: $0\rst_cnt[3:0] Creating decoders for process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:116$1593'. 1/2: $0\boot_now[0:0] 2/2: $0\boot_sel[1:0] Creating decoders for process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:73$1592'. 1/1: $0\wb_rdata[31:0] Creating decoders for process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:66$1588'. 1/1: $0\bus_we_boot[0:0] Creating decoders for process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:60$1583'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1579'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1576'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1570'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1566'. 1/1: $0\len[10:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1560'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1553'. 1/2: $0\shift_last_byte[0:0] 2/2: $0\shift_data_crc[0:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1551'. 1/1: $0\shift_data[7:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1547'. 1/1: $0\shift_load[7:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1544'. 1/1: $0\shift_bit[3:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1532'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1531'. 1/1: $0\state[3:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1529'. 1/8: $8\state_nxt[3:0] 2/8: $7\state_nxt[3:0] 3/8: $6\state_nxt[3:0] 4/8: $5\state_nxt[3:0] 5/8: $4\state_nxt[3:0] 6/8: $3\state_nxt[3:0] 7/8: $2\state_nxt[3:0] 8/8: $1\state_nxt[3:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1528'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1526'. 1/1: $0\out_sym[1:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1519'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1514'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1504'. 1/2: $0\bs_now[0:0] 2/2: $0\bs_cnt[2:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1501'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1498'. 1/1: $0\state[2:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1494'. 1/1: $0\pkt_pid[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1486'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1483'. 1/1: $0\bd_length[10:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1477'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1476'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1473'. 1/1: $0\txpkt_pid[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1467'. 1/1: $0\cel_state_i[0:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1465'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1452'. 1/7: $0\bd_state[2:0] 2/7: $0\ep_data_toggle[0:0] 3/7: $0\ep_bd_idx_nxt[0:0] 4/7: $0\ep_bd_idx_cur[0:0] 5/7: $0\ep_bd_ctrl[0:0] 6/7: $0\ep_bd_dual[0:0] 7/7: $0\ep_type[2:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1449'. 1/1: $0\epfw_cap_dl[5:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1444'. 1/1: $0\epfw_state[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1440'. 1/4: $0\trans_cel[0:0] 2/4: $0\trans_dir[0:0] 3/4: $0\trans_endp[3:0] 4/4: $0\trans_is_setup[0:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1433'. 1/1: $0\rto_cnt[9:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1428'. 1/1: $0\evt[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1425'. 1/1: $0\mc_a_reg[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1416'. 1/1: $0\mc_pc_nxt[7:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1407'. 1/1: $0\mc_rst_n[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1404'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1395'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1393'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1390'. 1/1: $0\token_data[10:8] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1387'. 1/1: $0\token_data[7:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1370'. 1/5: $0\pid_is_handshake[0:0] 2/5: $0\pid_is_data[0:0] 3/5: $0\pid_is_token[0:0] 4/5: $0\pid_is_sof[0:0] 5/5: $0\pid[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1369'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1348'. 1/1: $0\pid_valid[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1344'. 1/2: $0\crc16_ok[0:0] 2/2: $0\crc5_ok[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1343'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1341'. 1/1: $0\crc_in_first[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1338'. 1/1: $0\bit_eop_ok[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1335'. 1/1: $0\bit_cnt[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1334'. 1/1: $0\data[7:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1326'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1325'. 1/1: $0\state[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1309'. 1/18: $18\state_nxt[3:0] 2/18: $17\state_nxt[3:0] 3/18: $16\state_nxt[3:0] 4/18: $15\state_nxt[3:0] 5/18: $14\state_nxt[3:0] 6/18: $13\state_nxt[3:0] 7/18: $12\state_nxt[3:0] 8/18: $11\state_nxt[3:0] 9/18: $10\state_nxt[3:0] 10/18: $9\state_nxt[3:0] 11/18: $8\state_nxt[3:0] 12/18: $7\state_nxt[3:0] 13/18: $6\state_nxt[3:0] 14/18: $5\state_nxt[3:0] 15/18: $4\state_nxt[3:0] 16/18: $3\state_nxt[3:0] 17/18: $2\state_nxt[3:0] 18/18: $1\state_nxt[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1308'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1306'. 1/1: $0\dec_bs_skip_1[0:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1304'. 1/1: $0\dec_rep_state_1[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1303'. 1/1: $0\dec_sync_state_1[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1302'. 1/1: $0\dec_eop_state_1[2:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1301'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1294'. 1/2: $0\dec_bit_1[0:0] 2/2: $0\dec_sym_1[1:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1287'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1286'. 1/1: $0\samp_cnt[2:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1276'. 1/1: $0\samp_active[0:0] Creating decoders for process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5113'. 1/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 2/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_DATA[7:0]$5115 3/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_ADDR[8:0]$5114 4/4: $0\rd_data[7:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1272'. 1/1: $0\s_dout_3[15:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1270'. 1/1: $0\p_dout_3[15:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1267'. Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1259'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5107'. 1/1: $0\wb_rdata_reg[31:0] Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5105'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5080'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5077'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4216'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4207'. 1/1: $0\stage[4].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4205'. 1/1: $0\stage[4].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4196'. 1/1: $0\stage[3].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4194'. 1/1: $0\stage[3].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4185'. 1/1: $0\stage[2].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4183'. 1/1: $0\stage[2].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4174'. 1/1: $0\stage[1].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4172'. 1/1: $0\stage[1].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4170'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4161'. 1/1: $0\stage[4].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4159'. 1/1: $0\stage[4].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4150'. 1/1: $0\stage[3].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4148'. 1/1: $0\stage[3].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4139'. 1/1: $0\stage[2].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4137'. 1/1: $0\stage[2].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4128'. 1/1: $0\stage[1].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4126'. 1/1: $0\stage[1].l_data[8:0] Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5038'. Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5033'. 1/1: $0\wb_rdata[15:0] Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5028'. Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:106$5023'. Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1104'. 1/1: $0\out_stb[0:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1103'. 1/1: $0\dst[1:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1101'. 1/1: $0\src[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4104'. 1/1: $0\wb_now[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4095'. 1/3: $0\wb_req[0:0] 2/3: $0\wb_sel[1:0] 3/3: $0\rst_req[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4091'. 1/1: $0\timer[25:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4089'. 1/1: $0\armed[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. 1/82: $0\reg_next_pc[31:0] [31:2] 2/82: $0\reg_next_pc[31:0] [1:0] 3/82: $0\reg_pc[31:0] [1:0] 4/82: $18\next_irq_pending[2:2] 5/82: $17\next_irq_pending[2:2] 6/82: $16\next_irq_pending[2:2] 7/82: $15\next_irq_pending[2:2] 8/82: $14\next_irq_pending[2:2] 9/82: $13\next_irq_pending[2:2] 10/82: $4\next_irq_pending[31:0] [31:2] 11/82: $3\set_mem_do_rdata[0:0] 12/82: $4\next_irq_pending[31:0] [1] 13/82: $3\set_mem_do_wdata[0:0] 14/82: $4\next_irq_pending[31:0] [0] 15/82: $4\set_mem_do_rinst[0:0] 16/82: $3\set_mem_do_rinst[0:0] 17/82: $4\set_mem_do_wdata[0:0] 18/82: $11\next_irq_pending[1:1] 19/82: $10\next_irq_pending[1:1] 20/82: $9\next_irq_pending[1:1] 21/82: $4\set_mem_do_rdata[0:0] 22/82: $7\next_irq_pending[1:1] 23/82: $6\next_irq_pending[1:1] 24/82: $12\next_irq_pending[1:1] 25/82: $5\set_mem_do_rinst[0:0] 26/82: $8\next_irq_pending[1:1] 27/82: $5\next_irq_pending[31:0] 28/82: $3\current_pc[31:0] 29/82: $2\current_pc[31:0] 30/82: $2\set_mem_do_wdata[0:0] 31/82: $2\set_mem_do_rdata[0:0] 32/82: $2\set_mem_do_rinst[0:0] 33/82: $3\next_irq_pending[31:0] 34/82: $1\current_pc[31:0] 35/82: $1\set_mem_do_wdata[0:0] 36/82: $1\set_mem_do_rdata[0:0] 37/82: $1\set_mem_do_rinst[0:0] 38/82: $0\trace_data[35:0] 39/82: $2\next_irq_pending[0:0] 40/82: $1\next_irq_pending[0:0] 41/82: $0\count_instr[63:0] 42/82: $0\count_cycle[63:0] 43/82: $0\trace_valid[0:0] 44/82: $0\do_waitirq[0:0] 45/82: $0\decoder_pseudo_trigger[0:0] 46/82: $0\decoder_trigger[0:0] 47/82: $0\alu_wait_2[0:0] 48/82: $0\alu_wait[0:0] 49/82: $0\reg_out[31:0] 50/82: $0\reg_sh[4:0] 51/82: $0\trap[0:0] 52/82: $0\pcpi_timeout[0:0] 53/82: $0\latched_rd[4:0] 54/82: $0\latched_is_lb[0:0] 55/82: $0\latched_is_lh[0:0] 56/82: $0\latched_is_lu[0:0] 57/82: $0\latched_trace[0:0] 58/82: $0\latched_compr[0:0] 59/82: $0\latched_branch[0:0] 60/82: $0\latched_stalu[0:0] 61/82: $0\latched_store[0:0] 62/82: $0\irq_state[1:0] 63/82: $0\cpu_state[7:0] 64/82: $0\dbg_rs2val_valid[0:0] 65/82: $0\dbg_rs1val_valid[0:0] 66/82: $0\dbg_rs2val[31:0] 67/82: $0\dbg_rs1val[31:0] 68/82: $0\mem_do_wdata[0:0] 69/82: $0\mem_do_rdata[0:0] 70/82: $0\mem_do_rinst[0:0] 71/82: $0\mem_do_prefetch[0:0] 72/82: $0\mem_wordsize[1:0] 73/82: $0\irq_mask[31:0] 74/82: $0\irq_active[0:0] 75/82: $0\irq_delay[0:0] 76/82: $0\reg_op2[31:0] 77/82: $0\reg_op1[31:0] 78/82: $0\reg_pc[31:0] [31:2] 79/82: $19\next_irq_pending[2:2] 80/82: $0\eoi[31:0] 81/82: $0\pcpi_valid[0:0] 82/82: $0\timer[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3897'. Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3883'. 1/4: $2\cpuregs_write[0:0] 2/4: $2\cpuregs_wrdata[31:0] 3/4: $1\cpuregs_wrdata[31:0] 4/4: $1\cpuregs_write[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$3878'. 1/2: $2\clear_prefetched_high_word[0:0] 2/2: $1\clear_prefetched_high_word[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$3877'. Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3855'. 1/2: $1\alu_out[31:0] 2/2: $1\alu_out_0[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$3843'. 1/8: $8\dbg_ascii_state[127:0] 2/8: $7\dbg_ascii_state[127:0] 3/8: $6\dbg_ascii_state[127:0] 4/8: $5\dbg_ascii_state[127:0] 5/8: $4\dbg_ascii_state[127:0] 6/8: $3\dbg_ascii_state[127:0] 7/8: $2\dbg_ascii_state[127:0] 8/8: $1\dbg_ascii_state[127:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. 1/76: $0\decoded_rs1[4:0] [4] 2/76: $0\decoded_imm_uj[31:0] [10] 3/76: $0\decoded_imm_uj[31:0] [7] 4/76: $0\decoded_imm_uj[31:0] [6] 5/76: $0\decoded_imm_uj[31:0] [3:1] 6/76: $0\decoded_imm_uj[31:0] [5] 7/76: $0\decoded_imm_uj[31:0] [9:8] 8/76: $0\decoded_imm_uj[31:0] [31:20] 9/76: $0\decoded_imm_uj[31:0] [4] 10/76: $0\decoded_imm_uj[31:0] [11] 11/76: $0\decoded_imm_uj[31:0] [0] 12/76: $0\decoded_rs1[4:0] [3:0] 13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0] 14/76: $0\is_alu_reg_reg[0:0] 15/76: $0\is_alu_reg_imm[0:0] 16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0] 17/76: $0\is_sll_srl_sra[0:0] 18/76: $0\is_sb_sh_sw[0:0] 19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0] 20/76: $0\is_slli_srli_srai[0:0] 21/76: $0\is_lb_lh_lw_lbu_lhu[0:0] 22/76: $0\compressed_instr[0:0] 23/76: $0\is_compare[0:0] 24/76: $0\decoded_imm[31:0] 25/76: $0\decoded_rs2[4:0] 26/76: $0\decoded_imm_uj[31:0] [19:12] 27/76: $0\decoded_rd[4:0] 28/76: $0\instr_timer[0:0] 29/76: $0\instr_waitirq[0:0] 30/76: $0\instr_maskirq[0:0] 31/76: $0\instr_retirq[0:0] 32/76: $0\instr_setq[0:0] 33/76: $0\instr_getq[0:0] 34/76: $0\instr_ecall_ebreak[0:0] 35/76: $0\instr_rdinstrh[0:0] 36/76: $0\instr_rdinstr[0:0] 37/76: $0\instr_rdcycleh[0:0] 38/76: $0\instr_rdcycle[0:0] 39/76: $0\instr_and[0:0] 40/76: $0\instr_or[0:0] 41/76: $0\instr_sra[0:0] 42/76: $0\instr_srl[0:0] 43/76: $0\instr_xor[0:0] 44/76: $0\instr_sltu[0:0] 45/76: $0\instr_slt[0:0] 46/76: $0\instr_sll[0:0] 47/76: $0\instr_sub[0:0] 48/76: $0\instr_add[0:0] 49/76: $0\instr_srai[0:0] 50/76: $0\instr_srli[0:0] 51/76: $0\instr_slli[0:0] 52/76: $0\instr_andi[0:0] 53/76: $0\instr_ori[0:0] 54/76: $0\instr_xori[0:0] 55/76: $0\instr_sltiu[0:0] 56/76: $0\instr_slti[0:0] 57/76: $0\instr_addi[0:0] 58/76: $0\instr_sw[0:0] 59/76: $0\instr_sh[0:0] 60/76: $0\instr_sb[0:0] 61/76: $0\instr_lhu[0:0] 62/76: $0\instr_lbu[0:0] 63/76: $0\instr_lw[0:0] 64/76: $0\instr_lh[0:0] 65/76: $0\instr_lb[0:0] 66/76: $0\instr_bgeu[0:0] 67/76: $0\instr_bltu[0:0] 68/76: $0\instr_bge[0:0] 69/76: $0\instr_blt[0:0] 70/76: $0\instr_bne[0:0] 71/76: $0\instr_beq[0:0] 72/76: $0\instr_jalr[0:0] 73/76: $0\instr_jal[0:0] 74/76: $0\instr_auipc[0:0] 75/76: $0\instr_lui[0:0] 76/76: $0\pcpi_insn[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3581'. 1/13: $3\dbg_insn_opcode[31:0] 2/13: $2\dbg_insn_rd[4:0] 3/13: $2\dbg_insn_rs2[4:0] 4/13: $2\dbg_insn_rs1[4:0] 5/13: $2\dbg_insn_opcode[31:0] 6/13: $2\dbg_insn_imm[31:0] 7/13: $2\dbg_ascii_instr[63:0] 8/13: $1\dbg_insn_rd[4:0] 9/13: $1\dbg_insn_rs2[4:0] 10/13: $1\dbg_insn_rs1[4:0] 11/13: $1\dbg_insn_imm[31:0] 12/13: $1\dbg_ascii_instr[63:0] 13/13: $1\dbg_insn_opcode[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. 1/8: $0\cached_insn_rd[4:0] 2/8: $0\cached_insn_rs2[4:0] 3/8: $0\cached_insn_rs1[4:0] 4/8: $0\cached_insn_opcode[31:0] 5/8: $0\cached_insn_imm[31:0] 6/8: $0\cached_ascii_instr[63:0] 7/8: $0\dbg_valid_insn[0:0] 8/8: $0\dbg_insn_addr[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3576'. 1/47: $47\new_ascii_instr[63:0] 2/47: $46\new_ascii_instr[63:0] 3/47: $45\new_ascii_instr[63:0] 4/47: $44\new_ascii_instr[63:0] 5/47: $43\new_ascii_instr[63:0] 6/47: $42\new_ascii_instr[63:0] 7/47: $41\new_ascii_instr[63:0] 8/47: $40\new_ascii_instr[63:0] 9/47: $39\new_ascii_instr[63:0] 10/47: $38\new_ascii_instr[63:0] 11/47: $37\new_ascii_instr[63:0] 12/47: $36\new_ascii_instr[63:0] 13/47: $35\new_ascii_instr[63:0] 14/47: $34\new_ascii_instr[63:0] 15/47: $33\new_ascii_instr[63:0] 16/47: $32\new_ascii_instr[63:0] 17/47: $31\new_ascii_instr[63:0] 18/47: $30\new_ascii_instr[63:0] 19/47: $29\new_ascii_instr[63:0] 20/47: $28\new_ascii_instr[63:0] 21/47: $27\new_ascii_instr[63:0] 22/47: $26\new_ascii_instr[63:0] 23/47: $25\new_ascii_instr[63:0] 24/47: $24\new_ascii_instr[63:0] 25/47: $23\new_ascii_instr[63:0] 26/47: $22\new_ascii_instr[63:0] 27/47: $21\new_ascii_instr[63:0] 28/47: $20\new_ascii_instr[63:0] 29/47: $19\new_ascii_instr[63:0] 30/47: $18\new_ascii_instr[63:0] 31/47: $17\new_ascii_instr[63:0] 32/47: $16\new_ascii_instr[63:0] 33/47: $15\new_ascii_instr[63:0] 34/47: $14\new_ascii_instr[63:0] 35/47: $13\new_ascii_instr[63:0] 36/47: $12\new_ascii_instr[63:0] 37/47: $11\new_ascii_instr[63:0] 38/47: $10\new_ascii_instr[63:0] 39/47: $9\new_ascii_instr[63:0] 40/47: $8\new_ascii_instr[63:0] 41/47: $7\new_ascii_instr[63:0] 42/47: $6\new_ascii_instr[63:0] 43/47: $5\new_ascii_instr[63:0] 44/47: $4\new_ascii_instr[63:0] 45/47: $3\new_ascii_instr[63:0] 46/47: $2\new_ascii_instr[63:0] 47/47: $1\new_ascii_instr[63:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3552'. 1/9: $0\mem_16bit_buffer[15:0] 2/9: $0\prefetched_high_word[0:0] 3/9: $0\mem_la_secondword[0:0] 4/9: $0\mem_state[1:0] 5/9: $0\mem_wstrb[3:0] 6/9: $0\mem_wdata[31:0] 7/9: $0\mem_instr[0:0] 8/9: $0\mem_valid[0:0] 9/9: $0\mem_addr[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4076'. Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3514'. 1/9: $0\mem_rdata_q[31:0] [31] 2/9: $0\mem_rdata_q[31:0] [7] 3/9: $0\mem_rdata_q[31:0] [24:20] 4/9: $0\mem_rdata_q[31:0] [19:15] 5/9: $0\mem_rdata_q[31:0] [6:0] 6/9: $0\mem_rdata_q[31:0] [14:12] 7/9: $0\mem_rdata_q[31:0] [11:8] 8/9: $0\mem_rdata_q[31:0] [30:25] 9/9: $0\next_insn_opcode[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3511'. 1/5: $3\mem_rdata_word[31:0] 2/5: $2\mem_rdata_word[31:0] 3/5: $1\mem_rdata_word[31:0] 4/5: $1\mem_la_wstrb[3:0] 5/5: $1\mem_la_wdata[31:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3506'. 1/2: $0\last_mem_valid[0:0] 2/2: $0\mem_la_firstword_reg[0:0] Creating decoders for process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3432'. 1/2: $1\pcpi_int_rd[31:0] 2/2: $1\pcpi_int_wr[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5014'. Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5013'. Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5008'. 1/1: $0\rx_pending[1:1] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5007'. 1/2: $0\rx_addr_reg[1][15:0] 2/2: $0\rx_data_reg[1][7:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5002'. 1/1: $0\rx_pending[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5001'. 1/2: $0\rx_addr_reg[0][15:0] 2/2: $0\rx_data_reg[0][7:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4991'. 1/3: $1\t_done[3:0] 2/3: $1$bitselwrite$data$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$4950[3:0]$4995 3/3: $1$bitselwrite$mask$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$4949[3:0]$4994 Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. 1/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4944[15:0]$4987 2/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4943[15:0]$4986 3/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4942[15:0]$4984 4/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4941[15:0]$4983 5/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4938[15:0]$4981 6/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4937[15:0]$4980 7/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4936[15:0]$4978 8/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4935[15:0]$4977 9/20: $1\mux.j[31:0] 10/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4944[15:0]$4975 11/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4943[15:0]$4974 12/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4942[15:0]$4973 13/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4941[15:0]$4972 14/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4938[15:0]$4971 15/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4937[15:0]$4970 16/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4936[15:0]$4969 17/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4935[15:0]$4968 18/20: $0\wb_wdata_byte[7:0] 19/20: $0\wb_addr_lsb[1:0] 20/20: $0\wb_addr[13:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$4955'. 1/1: $0\t_chan[1:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4953'. 1/1: $0\t_busy[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4951'. 1/4: $4\t_nxt_chan[1:0] 2/4: $3\t_nxt_chan[1:0] 3/4: $2\t_nxt_chan[1:0] 4/4: $1\t_nxt_chan[1:0] Creating decoders for process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. 1/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_EN[31:0]$3325 2/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_DATA[31:0]$3324 3/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_ADDR[7:0]$3323 4/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN[31:0]$3328 5/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_DATA[31:0]$3327 6/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_ADDR[7:0]$3326 7/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN[31:0]$3331 8/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_DATA[31:0]$3330 9/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_ADDR[7:0]$3329 10/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN[31:0]$3334 11/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_DATA[31:0]$3333 12/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_ADDR[7:0]$3332 Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3313'. 1/1: $0\uart_div[11:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3311'. 1/1: $0\ub_rdata[31:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3301'. 1/1: $0\ub_ack[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3284'. 1/4: $0\ub_wr_div[0:0] 2/4: $0\ub_wr_data[0:0] 3/4: $0\ub_rd_ctrl[0:0] 4/4: $0\ub_rd_data[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3279'. 1/1: $0\urf_overflow[0:0] Creating decoders for process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3272'. 1/1: $0\led_ctrl[4:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3266'. 1/1: $0\evt_cnt[3:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3261'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3259'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3258'. 1/1: $0\pad_pu[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3254'. 1/1: $0\rst_pending[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3250'. 1/1: $0\timeout_reset[19:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3246'. 1/1: $0\timeout_suspend[19:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3232'. 1/1: $0\eps_bus_ack_wait[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3229'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3219'. 1/3: $0\eps_bus_req[0:0] 2/3: $0\eps_bus_write[0:0] 3/3: $0\eps_bus_read[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3270'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3217'. 1/4: $0\cr_addr[6:0] 2/4: $0\cr_addr_chk[0:0] 3/4: $0\cr_cel_ena[0:0] 4/4: $0\cr_pu_ena[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3213'. 1/2: $2\csr_bus_dout[15:0] 2/2: $1\csr_bus_dout[15:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3195'. 1/7: $0\ir_bus_we[0:0] 2/7: $0\evt_rd_ack[0:0] 3/7: $0\sof_clear[0:0] 4/7: $0\rst_clear[0:0] 5/7: $0\cel_rel[0:0] 6/7: $0\cr_bus_we[0:0] 7/7: $0\csr_bus_req[0:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3191'. 1/1: $0\m_cyc_i[0:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3187'. Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3184'. 1/1: $0\s_rdata[15:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3183'. 1/1: $0\m_rdata_i[15:0] Creating decoders for process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4922'. 1/1: $0\ack_i[0:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4901'. 1/2: $0\busy[0:0] 2/2: $0\sel[2:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4892'. 1/3: $0\sel_nxt[2:0] [2] 2/3: $0\sel_nxt[2:0] [0] 3/3: $0\sel_nxt[2:0] [1] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4889'. 1/4: $0\m_wmsk[3:0] 2/4: $0\m_we[0:0] 3/4: $0\m_wdata[31:0] 4/4: $0\m_addr[13:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4870'. Creating decoders for process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3100'. Creating decoders for process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3098'. Creating decoders for process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3096'. Creating decoders for process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3095'. 1/1: $0\pb_rst_n[0:0] Creating decoders for process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2947'. Creating decoders for process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2944'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2943'. Creating decoders for process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2937'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2936'. Creating decoders for process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2933'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2932'. Creating decoders for process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2926'. 1/1: $0\Q[0:0] Creating decoders for process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:59$179'. Creating decoders for process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:52$178'. Creating decoders for process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2925'. Creating decoders for process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2923'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2922'. Creating decoders for process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2920'. 1/1: $0\Q[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$143'. 1/1: $0\aligned[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$137'. 1/7: $0\out_last[0:0] 2/7: $0\out_first[0:0] 3/7: $0\out_ts_is0[0:0] 4/7: $0\out_ts[4:0] 5/7: $0\out_frame[3:0] 6/7: $0\out_data[7:0] 7/7: $0\out_valid[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:357$129'. Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$111'. 1/4: $0\ec_mfa[1:0] 2/4: $0\ec_crc[1:0] 3/4: $0\ec_nfas[1:0] 4/4: $0\ec_fas[1:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$91'. 1/4: $0\ed_mfa[0:0] 2/4: $0\ep_mfa[0:0] 3/4: $0\ed_crc[0:0] 4/4: $0\ep_crc[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$69'. 1/4: $0\ed_nfas[0:0] 2/4: $0\ep_nfas[0:0] 3/4: $0\ed_fas[0:0] 4/4: $0\ep_fas[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$68'. 1/1: $0\crc_smf[3:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$57'. 1/3: $0\ts0_msbs_match_crc[0:0] 2/3: $0\ts0_msbs_match_mf[0:0] 3/3: $0\ts0_msbs[15:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$53'. 1/1: $0\mfa_timeout[6:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$49'. 1/1: $0\fas_pos[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$39'. 1/5: $0\frame_mf_last[0:0] 2/5: $0\frame_mf_first[0:0] 3/5: $0\frame_smf_last[0:0] 4/5: $0\frame_smf_first[0:0] 5/5: $0\frame[3:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$35'. 1/3: $0\ts_is_ts31[0:0] 2/3: $0\ts_is_ts0[0:0] 3/3: $0\ts[4:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$31'. 1/3: $0\bit_last[0:0] 2/3: $0\bit_first[0:0] 3/3: $0\bit[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$23'. 1/1: $0\fsm_state_nxt[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$21'. 1/1: $0\fsm_state[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$18'. 1/1: $0\data_match_fas[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$17'. 1/1: $0\data[7:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$16'. 1/1: $0\strobe[0:0] Creating decoders for process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2919'. Creating decoders for process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2917'. 1/1: $0\Q[0:0] Creating decoders for process `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$10'. 1/1: $0\state[3:0] 73.3.7. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\sel_nxt' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4840'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\prio.i' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4840'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_addr' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4824'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_wdata' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4824'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_wmsk' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4824'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux.i' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4824'. No latch inferred for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\state_nxt' from process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$4766'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4745$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4757'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4748$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4757'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4748$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4757'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4744$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4753'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4747$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4753'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4747$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4753'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4743$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4749'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4746$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4749'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4746$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4749'. No latch inferred for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\cnt_move' from process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4721'. No latch inferred for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\cnt_move' from process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4488'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5182$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5224'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5191$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5224'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5191$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5224'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5181$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5220'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5190$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5220'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5190$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5220'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5180$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5216'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5189$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5216'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5189$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5216'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5179$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5212'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5188$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5212'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5188$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5212'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5178$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5208'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5187$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5208'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5187$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5208'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5177$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5204'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5186$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5204'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5186$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5204'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5176$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5200'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5185$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5200'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5185$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5200'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5175$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5196'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5184$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5196'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5184$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5196'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5174$\ram_wr_shuffle_32' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5192'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5183$\ram_wr_shuffle_32' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5192'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5183$\src' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5192'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_do_m[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4479'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4479'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di[1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4479'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4479'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm[1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4479'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\rd_data' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.n' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.x' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.o' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323'. Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$15258 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$15373 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [2]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$15536 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [3]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$15747 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [4]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$15958 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [5]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$16169 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [6]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$16380 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [7]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$16591 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [8]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$16802 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [9]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$17013 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [10]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$17224 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [11]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$17435 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [12]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$17646 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [13]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$17857 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [14]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$18068 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [15]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$18279 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [16]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$18490 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [17]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$18701 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [18]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$18912 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [19]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$19123 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [20]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$19334 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [21]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$19545 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [22]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$19756 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [23]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$19967 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [24]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$20178 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [25]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$20389 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [26]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$20600 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [27]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$20811 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [28]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$21022 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [29]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$21233 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [30]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$21444 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [31]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$21655 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$21722 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$21789 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [2]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$21856 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [3]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$21923 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [4]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$21990 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [5]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$22057 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [6]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$22124 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [7]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323': $auto$proc_dlatch.cc:430:proc_dlatch$22191 No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5127$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5169'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5136$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5169'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5136$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5169'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5126$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5165'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5135$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5165'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5135$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5165'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5125$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5161'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5134$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5161'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5134$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5161'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5124$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5157'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5133$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5157'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5133$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5157'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5123$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5153'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5132$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5153'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5132$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5153'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5122$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5149'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5131$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5149'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5131$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5149'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5121$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5145'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5130$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5145'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5130$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5145'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5120$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5141'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5129$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5141'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5129$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5141'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5119$\ram_rd_shuffle_32' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5137'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5128$\ram_rd_shuffle_32' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5137'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5128$\src' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5137'. No latch inferred for signal `\usb_tx_pkt.\shift_load' from process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1547'. No latch inferred for signal `\usb_tx_pkt.\state_nxt' from process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1529'. No latch inferred for signal `\usb_rx_pkt.\state_nxt' from process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1309'. No latch inferred for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdata_or' from process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5080'. No latch inferred for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_or.i' from process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5080'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[0]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4216'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[1]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4216'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[2]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4216'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[3]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4216'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[4]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4216'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[5]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4216'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[0]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4170'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[1]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4170'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[2]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4170'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[3]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4170'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[4]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4170'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[5]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4170'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\bus_rdata_tx[0]' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5038'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\bus_rdata_tx[1]' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5038'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\bus_rdata' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5028'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\rdata_or.j' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5028'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpuregs_rs1' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3897'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpuregs_rs2' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3897'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_rs' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3897'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpuregs_write' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3883'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpuregs_wrdata' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3883'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\clear_prefetched_high_word' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$3878'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_out' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3855'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_out_0' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3855'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_ascii_state' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$3843'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_opcode' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3581'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_ascii_instr' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3581'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_imm' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3581'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_rs1' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3581'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_rs2' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3581'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_rd' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3581'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\new_ascii_instr' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3576'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_add_sub' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4076'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_shl' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4076'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_shr' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4076'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_eq' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4076'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_ltu' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4076'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_lts' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4076'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_la_wdata' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3511'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_la_wstrb' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3511'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_rdata_word' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3511'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_int_wr' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3432'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_int_rd' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3432'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_int_wait' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3432'. No latch inferred for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_int_ready' from process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3432'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_done' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4991'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$bitselwrite$mask$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$4949' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4991'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$bitselwrite$data$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$4950' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4991'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_nxt_busy' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4951'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_nxt_chan' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4951'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\next_sel.j' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4951'. No latch inferred for signal `$paramod\usb\EPDW=32.\irq' from process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3270'. No latch inferred for signal `$paramod\usb\EPDW=32.\csr_bus_dout' from process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3213'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\sel_nxt' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4892'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\prio.i' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4892'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_addr' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4870'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_wdata' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4870'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_wmsk' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4870'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux.i' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4870'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\wb_rdata[3] [31:16]' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3100'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\wb_rdata[5]' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3100'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\wb_rdata[6]' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3100'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\wb_rdata[7] [31:16]' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3100'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$mem2bits$\wb_rdata$/build/gateware/common/rtl/soc_base.v:499$3094' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3098'. No latch inferred for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$mem2bits$\wb_rdata$/build/gateware/common/rtl/soc_base.v:402$3093' from process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3096'. No latch inferred for signal `\e1_rx_deframer.\fsm_state_nxt' from process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$23'. 73.3.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2914'. created $dff cell `$procdff$22192' with negative edge clock. Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$2912'. created $dff cell `$procdff$22193' with negative edge clock. Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$2910'. created $dff cell `$procdff$22194' with negative edge clock. Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2906'. created $adff cell `$procdff$22195' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2899'. created $dff cell `$procdff$22196' with positive edge clock. Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2895'. created $adff cell `$procdff$22197' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2888'. created $dff cell `$procdff$22198' with positive edge clock. Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2885'. created $adff cell `$procdff$22199' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2882'. created $dff cell `$procdff$22200' with positive edge clock. Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2879'. created $adff cell `$procdff$22201' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2876'. created $dff cell `$procdff$22202' with positive edge clock. Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2874'. created $dff cell `$procdff$22203' with positive edge clock. Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2872'. created $dff cell `$procdff$22204' with positive edge clock. Creating register for signal `$paramod\wb_epbuf\AW=9\DW=32.\ack_i' using process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$4858'. created $adff cell `$procdff$22205' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\sel' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4847'. created $adff cell `$procdff$22206' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\busy' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4847'. created $adff cell `$procdff$22207' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_addr' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4837'. created $adff cell `$procdff$22208' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_wdata' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4837'. created $adff cell `$procdff$22209' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_we' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4837'. created $adff cell `$procdff$22210' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_wmsk' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4837'. created $adff cell `$procdff$22211' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_do_write' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4805'. created $adff cell `$procdff$22212' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_do_read' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4805'. created $adff cell `$procdff$22213' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_ack_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4805'. created $adff cell `$procdff$22214' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\dir' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$4801'. created $dff cell `$procdff$22215' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\len' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$4798'. created $dff cell `$procdff$22216' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\m1_addr_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$4788'. created $dff cell `$procdff$22217' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\m0_addr_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$4784'. created $dff cell `$procdff$22218' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\data_reg' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$4782'. created $dff cell `$procdff$22219' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\state' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$4765'. created $adff cell `$procdff$22220' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\go' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$4761'. created $adff cell `$procdff$22221' with positive edge clock and positive level reset. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\sync' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4742'. created $dff cell `$procdff$22222' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\rise' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4737'. created $dff cell `$procdff$22223' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\fall' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4737'. created $dff cell `$procdff$22224' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\state' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4733'. created $dff cell `$procdff$22225' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\cnt' using process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4729'. created $dff cell `$procdff$22226' with positive edge clock. Creating register for signal `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.\state' using process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4719'. created $dff cell `$procdff$22227' with positive edge clock. Creating register for signal `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.\state' using process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4706'. created $dff cell `$procdff$22228' with positive edge clock. Creating register for signal `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.\dp_state' using process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4682'. created $adff cell `$procdff$22229' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.\dn_state' using process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4682'. created $adff cell `$procdff$22230' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_rx\LIU=1\MFW=7.\bd_crc_e' using process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:203$5312'. created $adff cell `$procdff$22231' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_rx\LIU=1\MFW=7.\bd_done' using process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:196$5306'. created $dff cell `$procdff$22232' with positive edge clock. Creating register for signal `$paramod\e1_rx\LIU=1\MFW=7.\bd_miss' using process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:196$5306'. created $dff cell `$procdff$22233' with positive edge clock. Creating register for signal `$paramod\e1_rx\LIU=1\MFW=7.\mf_valid' using process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:188$5302'. created $adff cell `$procdff$22234' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\tx_crc_e_auto' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:254$5296'. created $dff cell `$procdff$22235' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\rx_overflow' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:247$5292'. created $adff cell `$procdff$22236' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\rx_rst' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:240$5290'. created $adff cell `$procdff$22237' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\bri_wren' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5272'. created $dff cell `$procdff$22238' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\bro_rden' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5272'. created $dff cell `$procdff$22239' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\rx_enabled' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5271'. created $adff cell `$procdff$22240' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\rx_mode' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5271'. created $adff cell `$procdff$22241' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\crx_wren' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5263'. created $dff cell `$procdff$22242' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=1\MFW=7.\crx_clear' using process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5263'. created $dff cell `$procdff$22243' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\ack' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5262'. created $dff cell `$procdff$22244' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\shift' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5261'. created $adff cell `$procdff$22245' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\bit_cnt' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5258'. created $dff cell `$procdff$22246' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\div_cnt' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5254'. created $dff cell `$procdff$22247' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\active' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5250'. created $adff cell `$procdff$22248' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\stb' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5244'. created $dff cell `$procdff$22249' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\shift' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5243'. created $dff cell `$procdff$22250' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\bit_cnt' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5240'. created $dff cell `$procdff$22251' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\div_cnt' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5236'. created $dff cell `$procdff$22252' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\active' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5232'. created $adff cell `$procdff$22253' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\rd_valid' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4533'. created $adff cell `$procdff$22254' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\ram_rd_addr' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4527'. created $adff cell `$procdff$22255' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\ram_wr_addr' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4525'. created $adff cell `$procdff$22256' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\full' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4516'. created $adff cell `$procdff$22257' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\level' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4510'. created $adff cell `$procdff$22258' with positive edge clock and positive level reset. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\sync' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4509'. created $dff cell `$procdff$22259' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\rise' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4504'. created $dff cell `$procdff$22260' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\fall' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4504'. created $dff cell `$procdff$22261' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\state' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4500'. created $dff cell `$procdff$22262' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\cnt' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4496'. created $dff cell `$procdff$22263' with positive edge clock. Creating register for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\addr_r' using process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4322'. created $dff cell `$procdff$22264' with positive edge clock. Creating register for signal `\sysmgr.\rst_cnt' using process `\sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1595'. created $adff cell `$procdff$22265' with positive edge clock and negative level reset. Creating register for signal `\misc.\boot_sel' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:116$1593'. created $adff cell `$procdff$22266' with positive edge clock and positive level reset. Creating register for signal `\misc.\boot_now' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:116$1593'. created $adff cell `$procdff$22267' with positive edge clock and positive level reset. Creating register for signal `\misc.\wb_rdata' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:73$1592'. created $dff cell `$procdff$22268' with positive edge clock. Creating register for signal `\misc.\bus_we_boot' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:66$1588'. created $dff cell `$procdff$22269' with positive edge clock. Creating register for signal `\misc.\wb_ack' using process `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:60$1583'. created $dff cell `$procdff$22270' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pkt_done' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1579'. created $dff cell `$procdff$22271' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pkt_data_ack' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1579'. created $dff cell `$procdff$22272' with positive edge clock. Creating register for signal `\usb_tx_pkt.\ll_start' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1576'. created $dff cell `$procdff$22273' with positive edge clock. Creating register for signal `\usb_tx_pkt.\crc_in_first' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1570'. created $dff cell `$procdff$22274' with positive edge clock. Creating register for signal `\usb_tx_pkt.\len' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1566'. created $dff cell `$procdff$22275' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_new_bit' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1560'. created $dff cell `$procdff$22276' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_data_crc' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1553'. created $dff cell `$procdff$22277' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_last_byte' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1553'. created $dff cell `$procdff$22278' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_data' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1551'. created $dff cell `$procdff$22279' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_bit' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1544'. created $dff cell `$procdff$22280' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pid_is_handshake' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1532'. created $dff cell `$procdff$22281' with positive edge clock. Creating register for signal `\usb_tx_pkt.\state' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1531'. created $adff cell `$procdff$22282' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\out_active' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1528'. created $dff cell `$procdff$22283' with positive edge clock. Creating register for signal `\usb_tx_ll.\out_sym' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1526'. created $adff cell `$procdff$22284' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\ll_ack' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1519'. created $dff cell `$procdff$22285' with positive edge clock. Creating register for signal `\usb_tx_ll.\lvl_prev' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1514'. created $dff cell `$procdff$22286' with positive edge clock. Creating register for signal `\usb_tx_ll.\bs_cnt' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1504'. created $adff cell `$procdff$22287' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\bs_now' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1504'. created $adff cell `$procdff$22288' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\br_cnt' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1501'. created $dff cell `$procdff$22289' with positive edge clock. Creating register for signal `\usb_tx_ll.\state' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1498'. created $adff cell `$procdff$22290' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\pkt_pid' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1494'. created $dff cell `$procdff$22291' with positive edge clock. Creating register for signal `\usb_trans.\xfer_length' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1486'. created $dff cell `$procdff$22292' with positive edge clock. Creating register for signal `\usb_trans.\bd_length' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1483'. created $dff cell `$procdff$22293' with positive edge clock. Creating register for signal `\usb_trans.\addr' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1477'. created $dff cell `$procdff$22294' with positive edge clock. Creating register for signal `\usb_trans.\txpkt_start_i' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1476'. created $dff cell `$procdff$22295' with positive edge clock. Creating register for signal `\usb_trans.\txpkt_pid' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1473'. created $dff cell `$procdff$22296' with positive edge clock. Creating register for signal `\usb_trans.\cel_state_i' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1467'. created $adff cell `$procdff$22297' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\epfw_issue_wb' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1465'. created $dff cell `$procdff$22298' with positive edge clock. Creating register for signal `\usb_trans.\ep_type' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1452'. created $dff cell `$procdff$22299' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_dual' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1452'. created $dff cell `$procdff$22300' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_ctrl' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1452'. created $dff cell `$procdff$22301' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_idx_cur' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1452'. created $dff cell `$procdff$22302' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_idx_nxt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1452'. created $dff cell `$procdff$22303' with positive edge clock. Creating register for signal `\usb_trans.\ep_data_toggle' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1452'. created $dff cell `$procdff$22304' with positive edge clock. Creating register for signal `\usb_trans.\bd_state' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1452'. created $dff cell `$procdff$22305' with positive edge clock. Creating register for signal `\usb_trans.\epfw_cap_dl' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1449'. created $adff cell `$procdff$22306' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\epfw_state' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1444'. created $adff cell `$procdff$22307' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\trans_is_setup' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1440'. created $dff cell `$procdff$22308' with positive edge clock. Creating register for signal `\usb_trans.\trans_endp' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1440'. created $dff cell `$procdff$22309' with positive edge clock. Creating register for signal `\usb_trans.\trans_dir' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1440'. created $dff cell `$procdff$22310' with positive edge clock. Creating register for signal `\usb_trans.\trans_cel' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1440'. created $dff cell `$procdff$22311' with positive edge clock. Creating register for signal `\usb_trans.\rto_cnt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1433'. created $adff cell `$procdff$22312' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\evt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1428'. created $adff cell `$procdff$22313' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\mc_a_reg' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1425'. created $dff cell `$procdff$22314' with positive edge clock. Creating register for signal `\usb_trans.\mc_pc_nxt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1416'. created $adff cell `$procdff$22315' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\mc_rst_n' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1407'. created $adff cell `$procdff$22316' with positive edge clock and positive level reset. Creating register for signal `\usb_rx_pkt.\pkt_data_stb' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1404'. created $dff cell `$procdff$22317' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_done_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1395'. created $dff cell `$procdff$22318' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_done_err' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1395'. created $dff cell `$procdff$22319' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_start' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1393'. created $dff cell `$procdff$22320' with positive edge clock. Creating register for signal `\usb_rx_pkt.\token_data [10:8]' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1390'. created $dff cell `$procdff$22321' with positive edge clock. Creating register for signal `\usb_rx_pkt.\token_data [7:0]' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1387'. created $dff cell `$procdff$22322' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1370'. created $dff cell `$procdff$22323' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_sof' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1370'. created $dff cell `$procdff$22324' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_token' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1370'. created $dff cell `$procdff$22325' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_data' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1370'. created $dff cell `$procdff$22326' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_handshake' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1370'. created $dff cell `$procdff$22327' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_cap_r' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1369'. created $dff cell `$procdff$22328' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_valid' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1348'. created $dff cell `$procdff$22329' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc5_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1344'. created $dff cell `$procdff$22330' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc16_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1344'. created $dff cell `$procdff$22331' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc_cap' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1343'. created $dff cell `$procdff$22332' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc_in_first' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1341'. created $dff cell `$procdff$22333' with positive edge clock. Creating register for signal `\usb_rx_pkt.\bit_eop_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1338'. created $dff cell `$procdff$22334' with positive edge clock. Creating register for signal `\usb_rx_pkt.\bit_cnt' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1335'. created $dff cell `$procdff$22335' with positive edge clock. Creating register for signal `\usb_rx_pkt.\data' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1334'. created $dff cell `$procdff$22336' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state_prev_idle' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1326'. created $dff cell `$procdff$22337' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state_prev_error' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1326'. created $dff cell `$procdff$22338' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1325'. created $adff cell `$procdff$22339' with positive edge clock and positive level reset. Creating register for signal `\usb_rx_ll.\dec_bs_skip_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1306'. created $dff cell `$procdff$22340' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_rep_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1304'. created $dff cell `$procdff$22341' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_sync_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1303'. created $dff cell `$procdff$22342' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_eop_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1302'. created $dff cell `$procdff$22343' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_valid_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1301'. created $dff cell `$procdff$22344' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_sym_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1294'. created $dff cell `$procdff$22345' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_bit_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1294'. created $dff cell `$procdff$22346' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_valid_0' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1287'. created $dff cell `$procdff$22347' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_cnt' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1286'. created $dff cell `$procdff$22348' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_active' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1276'. created $adff cell `$procdff$22349' with positive edge clock and positive level reset. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.\rd_data' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5113'. created $dff cell `$procdff$22350' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_ADDR' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5113'. created $dff cell `$procdff$22351' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_DATA' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5113'. created $dff cell `$procdff$22352' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5113'. created $dff cell `$procdff$22353' with positive edge clock. Creating register for signal `\usb_ep_status.\s_dout_3' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1272'. created $dff cell `$procdff$22354' with positive edge clock. Creating register for signal `\usb_ep_status.\p_dout_3' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1270'. created $dff cell `$procdff$22355' with positive edge clock. Creating register for signal `\usb_ep_status.\p_read_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1267'. created $dff cell `$procdff$22356' with positive edge clock. Creating register for signal `\usb_ep_status.\p_zero_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1267'. created $dff cell `$procdff$22357' with positive edge clock. Creating register for signal `\usb_ep_status.\s_read_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1267'. created $dff cell `$procdff$22358' with positive edge clock. Creating register for signal `\usb_ep_status.\s_zero_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1267'. created $dff cell `$procdff$22359' with positive edge clock. Creating register for signal `\usb_ep_status.\addr_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1259'. created $dff cell `$procdff$22360' with positive edge clock. Creating register for signal `\usb_ep_status.\din_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1259'. created $dff cell `$procdff$22361' with positive edge clock. Creating register for signal `\usb_ep_status.\we_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1259'. created $dff cell `$procdff$22362' with positive edge clock. Creating register for signal `\usb_ep_status.\p_read_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1259'. created $dff cell `$procdff$22363' with positive edge clock. Creating register for signal `\usb_ep_status.\p_zero_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1259'. created $dff cell `$procdff$22364' with positive edge clock. Creating register for signal `\usb_ep_status.\s_read_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1259'. created $dff cell `$procdff$22365' with positive edge clock. Creating register for signal `\usb_ep_status.\s_zero_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1259'. created $dff cell `$procdff$22366' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdata_reg' using process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5107'. created $dff cell `$procdff$22367' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdy_reg' using process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5105'. created $dff cell `$procdff$22368' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\ram_rdy' using process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5077'. created $dff cell `$procdff$22369' with positive edge clock. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[4].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4207'. created $adff cell `$procdff$22370' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[4].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4205'. created $adff cell `$procdff$22371' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[3].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4196'. created $adff cell `$procdff$22372' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[3].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4194'. created $adff cell `$procdff$22373' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[2].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4185'. created $adff cell `$procdff$22374' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[2].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4183'. created $adff cell `$procdff$22375' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[1].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4174'. created $adff cell `$procdff$22376' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[1].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4172'. created $adff cell `$procdff$22377' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[4].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4161'. created $adff cell `$procdff$22378' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[4].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4159'. created $adff cell `$procdff$22379' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[3].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4150'. created $adff cell `$procdff$22380' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[3].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4148'. created $adff cell `$procdff$22381' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[2].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4139'. created $adff cell `$procdff$22382' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[2].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4137'. created $adff cell `$procdff$22383' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[1].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4128'. created $adff cell `$procdff$22384' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[1].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4126'. created $adff cell `$procdff$22385' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\wb_rdata' using process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5033'. created $dff cell `$procdff$22386' with positive edge clock. Creating register for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.\wb_ack' using process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:106$5023'. created $dff cell `$procdff$22387' with positive edge clock. Creating register for signal `\xclk_strobe.\out_stb' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1104'. created $adff cell `$procdff$22388' with positive edge clock and positive level reset. Creating register for signal `\xclk_strobe.\dst' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1103'. created $adff cell `$procdff$22389' with positive edge clock and positive level reset. Creating register for signal `\xclk_strobe.\src' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1101'. created $adff cell `$procdff$22390' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\wb_now' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4104'. created $adff cell `$procdff$22391' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\rst_req' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4095'. created $adff cell `$procdff$22392' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\wb_sel' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4095'. created $adff cell `$procdff$22393' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\wb_req' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4095'. created $adff cell `$procdff$22394' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\timer' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4091'. created $adff cell `$procdff$22395' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.\armed' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4089'. created $adff cell `$procdff$22396' with positive edge clock and positive level reset. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\timer' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22397' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\trap' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22398' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22399' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\eoi' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22400' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\trace_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22401' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\trace_data' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22402' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\count_cycle' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22403' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\count_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22404' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_pc' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22405' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_next_pc' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22406' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_op1' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22407' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_op2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22408' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_out' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22409' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\reg_sh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22410' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_delay' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22411' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_active' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22412' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_mask' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22413' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_pending' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22414' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_wordsize' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22415' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_do_prefetch' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22416' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_do_rinst' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22417' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_do_rdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22418' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_do_wdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22419' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoder_trigger' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22420' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoder_trigger_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22421' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoder_pseudo_trigger' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22422' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22423' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_rs1val' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22424' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_rs2val' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22425' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_rs1val_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22426' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_rs2val_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22427' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cpu_state' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22428' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\irq_state' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22429' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\set_mem_do_rinst' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22430' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\set_mem_do_rdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22431' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\set_mem_do_wdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22432' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_store' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22433' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_stalu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22434' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_branch' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22435' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_compr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22436' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_trace' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22437' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_is_lu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22438' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_is_lh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22439' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_is_lb' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22440' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\latched_rd' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22441' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\current_pc' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22442' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_timeout' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22443' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\next_irq_pending' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22444' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\do_waitirq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22445' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_out_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22446' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_out_0_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22447' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_wait' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22448' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\alu_wait_2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. created $dff cell `$procdff$22449' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\clear_prefetched_high_word_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$3877'. created $dff cell `$procdff$22450' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\pcpi_insn' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22451' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lui' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22452' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_auipc' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22453' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_jal' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22454' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_jalr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22455' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_beq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22456' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_bne' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22457' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_blt' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22458' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_bge' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22459' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_bltu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22460' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_bgeu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22461' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lb' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22462' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22463' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lw' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22464' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lbu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22465' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_lhu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22466' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sb' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22467' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22468' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sw' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22469' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_addi' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22470' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_slti' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22471' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sltiu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22472' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_xori' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22473' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_ori' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22474' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_andi' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22475' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_slli' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22476' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_srli' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22477' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_srai' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22478' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_add' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22479' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sub' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22480' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sll' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22481' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_slt' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22482' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sltu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22483' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_xor' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22484' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_srl' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22485' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_sra' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22486' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_or' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22487' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_and' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22488' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_rdcycle' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22489' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_rdcycleh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22490' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_rdinstr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22491' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_rdinstrh' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22492' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_ecall_ebreak' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22493' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_getq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22494' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_setq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22495' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_retirq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22496' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_maskirq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22497' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_waitirq' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22498' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\instr_timer' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22499' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_rd' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22500' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_rs1' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22501' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_rs2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22502' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_imm' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22503' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\decoded_imm_uj' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22504' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\compressed_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22505' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_lui_auipc_jal' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22506' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22507' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_slli_srli_srai' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22508' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22509' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_sb_sh_sw' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22510' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_sll_srl_sra' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22511' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22512' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_slti_blt_slt' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22513' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22514' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22515' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_lbu_lhu_lw' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22516' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_alu_reg_imm' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22517' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_alu_reg_reg' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22518' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\is_compare' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. created $dff cell `$procdff$22519' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_insn_addr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22520' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_ascii_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22521' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_imm' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22522' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_opcode' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22523' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_rs1' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22524' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_rs2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22525' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\q_insn_rd' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22526' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_next' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22527' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\dbg_valid_insn' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22528' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_ascii_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22529' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_imm' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22530' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_opcode' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22531' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_rs1' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22532' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_rs2' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22533' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\cached_insn_rd' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. created $dff cell `$procdff$22534' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_addr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3552'. created $dff cell `$procdff$22535' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3552'. created $dff cell `$procdff$22536' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_instr' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3552'. created $dff cell `$procdff$22537' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_wdata' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3552'. created $dff cell `$procdff$22538' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_wstrb' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3552'. created $dff cell `$procdff$22539' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_state' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3552'. created $dff cell `$procdff$22540' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_la_secondword' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3552'. created $dff cell `$procdff$22541' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\prefetched_high_word' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3552'. created $dff cell `$procdff$22542' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_16bit_buffer' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3552'. created $dff cell `$procdff$22543' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\next_insn_opcode' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3514'. created $dff cell `$procdff$22544' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_rdata_q' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3514'. created $dff cell `$procdff$22545' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\mem_la_firstword_reg' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3506'. created $dff cell `$procdff$22546' with positive edge clock. Creating register for signal `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.\last_mem_valid' using process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3506'. created $dff cell `$procdff$22547' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_pending [1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5014'. created $dff cell `$procdff$22548' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_data_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5014'. created $dff cell `$procdff$22549' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_addr_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5014'. created $dff cell `$procdff$22550' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_pending [0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5013'. created $dff cell `$procdff$22551' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_addr_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5013'. created $dff cell `$procdff$22552' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\tx_data_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5013'. created $dff cell `$procdff$22553' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_pending [1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5008'. created $adff cell `$procdff$22554' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_data_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5007'. created $dff cell `$procdff$22555' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_addr_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5007'. created $dff cell `$procdff$22556' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_pending [0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5002'. created $adff cell `$procdff$22557' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_data_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5001'. created $dff cell `$procdff$22558' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\rx_addr_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5001'. created $dff cell `$procdff$22559' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\wb_addr' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. created $dff cell `$procdff$22560' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4935' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. created $dff cell `$procdff$22561' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4936' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. created $dff cell `$procdff$22562' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\wb_addr_lsb' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. created $dff cell `$procdff$22563' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\wb_wdata_byte' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. created $dff cell `$procdff$22564' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\mux.j' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. created $dff cell `$procdff$22565' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$4937' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. created $dff cell `$procdff$22566' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$4938' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. created $dff cell `$procdff$22567' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4941' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. created $dff cell `$procdff$22568' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4942' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. created $dff cell `$procdff$22569' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$4943' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. created $dff cell `$procdff$22570' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$4944' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. created $dff cell `$procdff$22571' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_chan' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$4955'. created $dff cell `$procdff$22572' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.\t_busy' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4953'. created $adff cell `$procdff$22573' with positive edge clock and positive level reset. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.\rdata' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. created $dff cell `$procdff$22574' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. created $dff cell `$procdff$22575' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. created $dff cell `$procdff$22576' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. created $dff cell `$procdff$22577' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. created $dff cell `$procdff$22578' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. created $dff cell `$procdff$22579' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. created $dff cell `$procdff$22580' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. created $dff cell `$procdff$22581' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. created $dff cell `$procdff$22582' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. created $dff cell `$procdff$22583' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. created $dff cell `$procdff$22584' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. created $dff cell `$procdff$22585' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. created $dff cell `$procdff$22586' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\uart_div' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3313'. created $dff cell `$procdff$22587' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rdata' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3311'. created $dff cell `$procdff$22588' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_ack' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3301'. created $dff cell `$procdff$22589' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rd_data' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3284'. created $dff cell `$procdff$22590' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rd_ctrl' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3284'. created $dff cell `$procdff$22591' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_wr_data' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3284'. created $dff cell `$procdff$22592' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_wr_div' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3284'. created $dff cell `$procdff$22593' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\urf_overflow' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3279'. created $adff cell `$procdff$22594' with positive edge clock and positive level reset. Creating register for signal `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.\led_ctrl' using process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3272'. created $adff cell `$procdff$22595' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\evt_cnt' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3266'. created $adff cell `$procdff$22596' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\sof_pending' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3261'. created $dff cell `$procdff$22597' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\sof_ind' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3259'. created $dff cell `$procdff$22598' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\pad_pu' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3258'. created $dff cell `$procdff$22599' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\rst_pending' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3254'. created $adff cell `$procdff$22600' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\timeout_reset' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3250'. created $dff cell `$procdff$22601' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\timeout_suspend' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3246'. created $dff cell `$procdff$22602' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_ack_wait' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3232'. created $adff cell `$procdff$22603' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_req_ok_dly' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3229'. created $dff cell `$procdff$22604' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_read' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3219'. created $dff cell `$procdff$22605' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_write' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3219'. created $dff cell `$procdff$22606' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_req' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3219'. created $dff cell `$procdff$22607' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\cr_pu_ena' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3217'. created $adff cell `$procdff$22608' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_cel_ena' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3217'. created $adff cell `$procdff$22609' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_addr_chk' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3217'. created $adff cell `$procdff$22610' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_addr' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3217'. created $adff cell `$procdff$22611' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cel_rel' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3195'. created $dff cell `$procdff$22612' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\csr_bus_req' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3195'. created $dff cell `$procdff$22613' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\cr_bus_we' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3195'. created $dff cell `$procdff$22614' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\ir_bus_we' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3195'. created $dff cell `$procdff$22615' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\evt_rd_ack' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3195'. created $dff cell `$procdff$22616' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\rst_clear' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3195'. created $dff cell `$procdff$22617' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\sof_clear' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3195'. created $dff cell `$procdff$22618' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\m_cyc_i' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3191'. created $adff cell `$procdff$22619' with positive edge clock and positive level reset. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_cyc_d' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3187'. created $dff cell `$procdff$22620' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_ack_d' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3187'. created $dff cell `$procdff$22621' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_rdata' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3184'. created $dff cell `$procdff$22622' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\m_rdata_i' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3183'. created $dff cell `$procdff$22623' with positive edge clock. Creating register for signal `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.\ack_i' using process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4922'. created $adff cell `$procdff$22624' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\sel' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4901'. created $adff cell `$procdff$22625' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\busy' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4901'. created $adff cell `$procdff$22626' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_addr' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4889'. created $adff cell `$procdff$22627' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_wdata' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4889'. created $adff cell `$procdff$22628' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_we' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4889'. created $adff cell `$procdff$22629' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_wmsk' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4889'. created $adff cell `$procdff$22630' with positive edge clock and positive level reset. Creating register for signal `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.\pb_rst_n' using process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3095'. created $adff cell `$procdff$22631' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2944'. created $adff cell `$procdff$22632' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2937'. created $dff cell `$procdff$22633' with negative edge clock. Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2933'. created $adff cell `$procdff$22634' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2926'. created $dff cell `$procdff$22635' with negative edge clock. Creating register for signal `\e1_rx_liu.\out_data' using process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:59$179'. created $dff cell `$procdff$22636' with positive edge clock. Creating register for signal `\e1_rx_liu.\out_valid' using process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:59$179'. created $dff cell `$procdff$22637' with positive edge clock. Creating register for signal `\e1_rx_liu.\rx_data_r' using process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:52$178'. created $dff cell `$procdff$22638' with positive edge clock. Creating register for signal `\e1_rx_liu.\rx_clk_r' using process `\e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:52$178'. created $dff cell `$procdff$22639' with positive edge clock. Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2923'. created $adff cell `$procdff$22640' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2920'. created $dff cell `$procdff$22641' with negative edge clock. Creating register for signal `\e1_rx_deframer.\aligned' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$143'. created $dff cell `$procdff$22642' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_data' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$137'. created $dff cell `$procdff$22643' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_frame' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$137'. created $dff cell `$procdff$22644' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_ts' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$137'. created $dff cell `$procdff$22645' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_ts_is0' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$137'. created $dff cell `$procdff$22646' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$137'. created $dff cell `$procdff$22647' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$137'. created $dff cell `$procdff$22648' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_valid' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$137'. created $dff cell `$procdff$22649' with positive edge clock. Creating register for signal `\e1_rx_deframer.\error' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:357$129'. created $dff cell `$procdff$22650' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$111'. created $dff cell `$procdff$22651' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$111'. created $dff cell `$procdff$22652' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$111'. created $dff cell `$procdff$22653' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$111'. created $dff cell `$procdff$22654' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$91'. created $dff cell `$procdff$22655' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$91'. created $dff cell `$procdff$22656' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$91'. created $dff cell `$procdff$22657' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$91'. created $dff cell `$procdff$22658' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$69'. created $dff cell `$procdff$22659' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$69'. created $dff cell `$procdff$22660' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$69'. created $dff cell `$procdff$22661' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$69'. created $dff cell `$procdff$22662' with positive edge clock. Creating register for signal `\e1_rx_deframer.\crc_smf' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$68'. created $dff cell `$procdff$22663' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$57'. created $dff cell `$procdff$22664' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs_match_mf' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$57'. created $dff cell `$procdff$22665' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs_match_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$57'. created $dff cell `$procdff$22666' with positive edge clock. Creating register for signal `\e1_rx_deframer.\mfa_timeout' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$53'. created $dff cell `$procdff$22667' with positive edge clock. Creating register for signal `\e1_rx_deframer.\fas_pos' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$49'. created $dff cell `$procdff$22668' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$39'. created $dff cell `$procdff$22669' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_smf_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$39'. created $dff cell `$procdff$22670' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_smf_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$39'. created $dff cell `$procdff$22671' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_mf_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$39'. created $dff cell `$procdff$22672' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_mf_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$39'. created $dff cell `$procdff$22673' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$35'. created $dff cell `$procdff$22674' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts_is_ts0' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$35'. created $dff cell `$procdff$22675' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts_is_ts31' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$35'. created $dff cell `$procdff$22676' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$31'. created $dff cell `$procdff$22677' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$31'. created $dff cell `$procdff$22678' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$31'. created $dff cell `$procdff$22679' with positive edge clock. Creating register for signal `\e1_rx_deframer.\fsm_state' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$21'. created $dff cell `$procdff$22680' with positive edge clock. Creating register for signal `\e1_rx_deframer.\data_match_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$18'. created $dff cell `$procdff$22681' with positive edge clock. Creating register for signal `\e1_rx_deframer.\data' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$17'. created $dff cell `$procdff$22682' with positive edge clock. Creating register for signal `\e1_rx_deframer.\strobe' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$16'. created $dff cell `$procdff$22683' with positive edge clock. Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2917'. created $adff cell `$procdff$22684' with negative edge clock and positive level reset. Creating register for signal `\e1_crc4.\state' using process `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$10'. created $dff cell `$procdff$22685' with positive edge clock. 73.3.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2916'. Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2914'. Removing empty process `SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$2914'. Removing empty process `SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2913'. Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$2912'. Removing empty process `SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$2912'. Removing empty process `SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2911'. Removing empty process `SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$2910'. Removing empty process `SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2909'. Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2906'. Removing empty process `SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$2906'. Removing empty process `SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2905'. Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2899'. Removing empty process `SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$2899'. Removing empty process `SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2898'. Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2895'. Removing empty process `SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$2895'. Removing empty process `SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2894'. Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2888'. Removing empty process `SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$2888'. Removing empty process `SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2887'. Removing empty process `SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$2885'. Removing empty process `SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2884'. Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2882'. Removing empty process `SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$2882'. Removing empty process `SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2881'. Removing empty process `SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2879'. Removing empty process `SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2878'. Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2876'. Removing empty process `SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2876'. Removing empty process `SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2875'. Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2874'. Removing empty process `SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2874'. Removing empty process `SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2873'. Removing empty process `SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2872'. Removing empty process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$4858'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4847'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4847'. Found and cleaned up 2 empty switches in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4840'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4840'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4837'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4837'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4824'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$4805'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$4801'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$4801'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$4798'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$4798'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$4788'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$4788'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$4784'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$4784'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$4782'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$4782'. Found and cleaned up 4 empty switches in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$4766'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$4766'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$4765'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$4761'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4757'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4753'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4749'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4742'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4737'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4737'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4733'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4733'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4729'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4729'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4721'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4721'. Found and cleaned up 1 empty switch in `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4719'. Removing empty process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4719'. Found and cleaned up 1 empty switch in `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4706'. Removing empty process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4706'. Found and cleaned up 2 empty switches in `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4682'. Removing empty process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4682'. Removing empty process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:203$5312'. Removing empty process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:196$5306'. Removing empty process `$paramod\e1_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:188$5302'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:254$5296'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:247$5292'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:240$5290'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5272'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$5272'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5271'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$5271'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5263'. Removing empty process `$paramod\e1_wb_rx\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$5263'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5262'. Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5261'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5261'. Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5258'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5258'. Found and cleaned up 1 empty switch in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5254'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5254'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5250'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5244'. Found and cleaned up 1 empty switch in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5243'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5243'. Found and cleaned up 2 empty switches in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5240'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5240'. Found and cleaned up 2 empty switches in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5236'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5236'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5232'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4533'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4533'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4527'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4527'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4525'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4525'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4516'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4510'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4509'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4504'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4504'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4500'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4500'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4496'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4496'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4488'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4488'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5224'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5220'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5216'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5212'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5208'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5204'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5200'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5196'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5192'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4479'. Found and cleaned up 16 empty switches in `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4323'. Found and cleaned up 1 empty switch in `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4322'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4322'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5169'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5165'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5161'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5157'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5153'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5149'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5145'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5141'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5137'. Found and cleaned up 1 empty switch in `\sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1595'. Removing empty process `sysmgr.$proc$/build/gateware/e1-tracer/rtl/sysmgr.v:81$1595'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:116$1593'. Removing empty process `misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:116$1593'. Found and cleaned up 2 empty switches in `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:73$1592'. Removing empty process `misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:73$1592'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:66$1588'. Removing empty process `misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:66$1588'. Removing empty process `misc.$proc$/build/gateware/e1-tracer/rtl/misc.v:60$1583'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1579'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1576'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1570'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1566'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1566'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1560'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1553'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1553'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1551'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1551'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1547'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1547'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1544'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1544'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1532'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1531'. Found and cleaned up 8 empty switches in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1529'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1529'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1528'. Found and cleaned up 2 empty switches in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1526'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1526'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1519'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1514'. Found and cleaned up 1 empty switch in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1504'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1504'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1501'. Found and cleaned up 4 empty switches in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1498'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1498'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1494'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1494'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1486'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1483'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1483'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1477'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1476'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1473'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1473'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1467'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1465'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1452'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1452'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1449'. Found and cleaned up 4 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1444'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1444'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1440'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1440'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1433'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1433'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1428'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1425'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1425'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1416'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1407'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1404'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1395'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1393'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1390'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1390'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1387'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1387'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1370'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1370'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1369'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1348'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1348'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1344'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1344'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1343'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1341'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1341'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1338'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1338'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1335'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1335'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1334'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1334'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1326'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1325'. Found and cleaned up 18 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1309'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1309'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1308'. Found and cleaned up 1 empty switch in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1306'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1306'. Found and cleaned up 3 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1304'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1304'. Found and cleaned up 3 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1303'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1303'. Found and cleaned up 2 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1302'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1302'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1301'. Found and cleaned up 1 empty switch in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1294'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1294'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1287'. Found and cleaned up 2 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1286'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1286'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1276'. Found and cleaned up 2 empty switches in `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5113'. Removing empty process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5113'. Found and cleaned up 1 empty switch in `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1272'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1272'. Found and cleaned up 1 empty switch in `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1270'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1270'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1267'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1259'. Found and cleaned up 1 empty switch in `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5107'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5107'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5105'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5080'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5077'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4216'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4207'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4207'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4205'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4205'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4196'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4196'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4194'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4194'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4185'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4185'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4183'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4183'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4174'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4174'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4172'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4172'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4170'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4161'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4161'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4159'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4159'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4150'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4150'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4148'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4148'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4139'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4139'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4137'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4137'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4128'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4128'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4126'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4126'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5038'. Found and cleaned up 1 empty switch in `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5033'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5033'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5028'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:106$5023'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1104'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1103'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1101'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4104'. Found and cleaned up 2 empty switches in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4095'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4095'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4091'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4089'. Found and cleaned up 55 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$3911'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$3897'. Found and cleaned up 2 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3883'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$3883'. Found and cleaned up 2 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$3878'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$3878'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$3877'. Found and cleaned up 2 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3855'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$3855'. Found and cleaned up 8 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$3843'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$3843'. Found and cleaned up 22 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3583'. Found and cleaned up 3 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3581'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3581'. Found and cleaned up 5 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3577'. Found and cleaned up 47 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3576'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3576'. Found and cleaned up 16 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3552'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3552'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1218$4076'. Found and cleaned up 19 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3514'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3514'. Found and cleaned up 3 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3511'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3511'. Found and cleaned up 2 empty switches in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3506'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3506'. Found and cleaned up 1 empty switch in `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3432'. Removing empty process `$paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3432'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5014'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5013'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5008'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5007'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5007'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5002'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5001'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5001'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4991'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$4991'. Found and cleaned up 5 empty switches in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$4958'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$4955'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$4955'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$4953'. Found and cleaned up 4 empty switches in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4951'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$4951'. Found and cleaned up 4 empty switches in `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. Removing empty process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3322'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3313'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3313'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3311'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3311'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3301'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3301'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3284'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3284'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3279'. Found and cleaned up 1 empty switch in `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3272'. Removing empty process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3272'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3266'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3261'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3259'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3258'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3258'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3254'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3250'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3250'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3246'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3246'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3232'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3229'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3219'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3219'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3270'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3217'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3217'. Found and cleaned up 2 empty switches in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3213'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3213'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3195'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3195'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3191'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3187'. Found and cleaned up 1 empty switch in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3184'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3184'. Found and cleaned up 1 empty switch in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3183'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3183'. Removing empty process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$4922'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4901'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$4901'. Found and cleaned up 3 empty switches in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4892'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$4892'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4889'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$4889'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$4870'. Removing empty process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3100'. Removing empty process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3098'. Removing empty process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3096'. Removing empty process `$paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3095'. Removing empty process `SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2947'. Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2944'. Removing empty process `SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$2944'. Removing empty process `SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2943'. Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2937'. Removing empty process `SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$2937'. Removing empty process `SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2936'. Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2933'. Removing empty process `SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$2933'. Removing empty process `SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2932'. Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2926'. Removing empty process `SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$2926'. Removing empty process `e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:59$179'. Removing empty process `e1_rx_liu.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_liu.v:52$178'. Removing empty process `SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2925'. Removing empty process `SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$2923'. Removing empty process `SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2922'. Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2920'. Removing empty process `SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$2920'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$143'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$143'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$137'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$137'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:357$129'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$111'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$111'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$91'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$91'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$69'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$69'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$68'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$68'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$57'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$57'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$53'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$53'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$49'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$49'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$39'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$39'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$35'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$35'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$31'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$31'. Found and cleaned up 10 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$23'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$23'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$21'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$21'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$18'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$18'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$17'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$17'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$16'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$16'. Removing empty process `SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2919'. Removing empty process `SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$2917'. Found and cleaned up 1 empty switch in `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$10'. Removing empty process `e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$10'. Cleaned up 445 empty switches. 73.4. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod\wb_epbuf\AW=9\DW=32. Deleting now unused module $paramod\wb_arbiter\N=2\DW=32\AW=9. Deleting now unused module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Deleting now unused module $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr. Deleting now unused module $paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Deleting now unused module soc_iobuf. Deleting now unused module $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100. Deleting now unused module $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101. Deleting now unused module picorv32_ice40_regs. Deleting now unused module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Deleting now unused module $paramod\e1_rx\LIU=1\MFW=7. Deleting now unused module $paramod\e1_wb_rx\LIU=1\MFW=7. Deleting now unused module $paramod\uart_tx\DIV_WIDTH=12. Deleting now unused module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Deleting now unused module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Deleting now unused module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Deleting now unused module $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf. Deleting now unused module $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32. Deleting now unused module capcnt32_sb_mac16. Deleting now unused module capcnt16_sb_mac16. Deleting now unused module $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf. Deleting now unused module sysmgr. Deleting now unused module misc. Deleting now unused module usb_tx_pkt. Deleting now unused module usb_tx_ll. Deleting now unused module usb_trans. Deleting now unused module usb_rx_pkt. Deleting now unused module usb_rx_ll. Deleting now unused module $paramod\ram_sdp\AWIDTH=9\DWIDTH=8. Deleting now unused module usb_ep_status. Deleting now unused module $paramod\soc_picorv32_bridge\WB_N=10\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4. Deleting now unused module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Deleting now unused module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Deleting now unused module $paramod\e1_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\LIU=1\MFW=7. Deleting now unused module xclk_strobe. Deleting now unused module $paramod\capcnt\W=32. Deleting now unused module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=3\DFU_MODE=0. Deleting now unused module $paramod\capcnt\W=16. Deleting now unused module $paramod$711abfb2e223cd0e32c81a659e40f13bd6a9a423\picorv32. Deleting now unused module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'11\UNIT_HAS_TX=2'00\MFW=7\DW=32. Deleting now unused module $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram. Deleting now unused module $paramod\soc_spram\AW=14. Deleting now unused module $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0. Deleting now unused module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Deleting now unused module $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb. Deleting now unused module $paramod\usb\EPDW=32. Deleting now unused module $paramod\xclk_wb\DW=16\AW=12. Deleting now unused module $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0. Deleting now unused module $paramod\wb_arbiter\N=3\DW=32\AW=14. Deleting now unused module $paramod$718d8a89459f06d0e6c215c6e438500872f54baf\soc_base. Deleting now unused module $paramod\ice40_spi_wb\N_CS=2\WITH_IOB=1\UNIT=1. Deleting now unused module e1_rx_liu. Deleting now unused module e1_rx_deframer. Deleting now unused module e1_crc4. <suppressed ~64 debug messages> 73.5. Executing TRIBUF pass. 73.6. Executing DEMINOUT pass (demote inout ports to input or output). Demoting inout port top.flash_cs_n to output. Demoting inout port top.liu_cs_n to output. 73.7. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~10757 debug messages> 73.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 986 unused cells and 14155 unused wires. <suppressed ~1109 debug messages> 73.9. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 73.10. Executing OPT pass (performing simple optimizations). 73.10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~1413 debug messages> Removed a total of 471 cells. 73.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $flatten\misc_I.\dfu_I.$procmux$11968: \misc_I.dfu_I.wb_req -> 1'1 Replacing known input bits on port B of cell $flatten\sys_mgr_I.$procmux$11403: \sys_mgr_I.rst_cnt -> { 1'1 \sys_mgr_I.rst_cnt [2:0] } Analyzing evaluation results. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12092. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12098. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12101. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12113. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12120. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12123. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12136. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12148. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12151. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12160. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12163. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12171. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12173. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12176. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12237. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12239. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12242. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12324. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12329. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12332. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12371. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12374. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$12385. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12417. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12430. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12443. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12482. dead port 1/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12679. dead port 2/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12679. dead port 3/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12679. dead port 4/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12679. dead port 5/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12679. dead port 6/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12679. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12685. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12685. dead port 3/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12685. dead port 4/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12685. dead port 5/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$12685. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12718. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12718. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12718. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12718. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12718. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12718. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$12718. dead port 1/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12923. dead port 2/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12923. dead port 3/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12923. dead port 4/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12923. dead port 5/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12923. dead port 6/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$12923. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$12987. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13006. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13006. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13006. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13006. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13006. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13006. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13006. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13188. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13204. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13204. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13204. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13204. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13204. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13204. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13204. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13366. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13366. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13366. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13366. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13366. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13366. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13366. dead port 1/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13417. dead port 2/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13417. dead port 3/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13417. dead port 4/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13417. dead port 5/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13417. dead port 7/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13417. dead port 8/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13417. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13514. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13514. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$13519. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13523. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13523. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$13528. dead port 1/8 on $pmux $flatten\soc_I.\cpu_I.$procmux$13543. dead port 2/8 on $pmux $flatten\soc_I.\cpu_I.$procmux$13543. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$14674. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$14681. dead port 1/2 on $mux $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5411. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$14852. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10014. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10014. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10014. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10014. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10014. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10031. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10031. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10031. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10031. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10031. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10050. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10050. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10050. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10050. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10071. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10071. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10071. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10071. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10094. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10094. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10094. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10094. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10094. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10119. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10119. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10119. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10119. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10119. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10146. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10146. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10146. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10146. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10146. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10175. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10175. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10175. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10175. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10175. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10206. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10206. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10206. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10206. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10206. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10239. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10239. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10239. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10239. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10239. dead port 1/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10274. dead port 2/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10274. dead port 3/4 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10274. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10314. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10314. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10314. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10314. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10314. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10324. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10324. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10324. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10324. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10324. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10338. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10338. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10338. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10338. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10338. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10354. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10354. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10354. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10354. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10354. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10374. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10374. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10374. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10374. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10398. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10398. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10398. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10398. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10398. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10426. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10426. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10426. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10426. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10426. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10458. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10458. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10458. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10458. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10458. dead port 1/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10494. dead port 2/3 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10494. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10501. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10501. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10501. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10501. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10501. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10512. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10512. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10512. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10512. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10512. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10534. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10534. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10534. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10534. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10534. dead port 1/5 on $pmux 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on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10206. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10206. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10206. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10239. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10239. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10239. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10239. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10239. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10274. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10274. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10274. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10314. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10314. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10314. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10314. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10314. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10324. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10324. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10324. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10324. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10324. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10338. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10338. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10338. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10338. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10338. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10354. dead port 2/5 on $pmux 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port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10501. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10501. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10512. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10512. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10512. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10512. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10512. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10534. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10534. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10534. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10534. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10534. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10568. dead port 2/5 on $pmux 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on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10628. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10628. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10628. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10636. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10636. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10636. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10636. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10636. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10662. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10662. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10662. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10662. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10662. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10720. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10720. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10720. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10720. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10720. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10733. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10733. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10733. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10733. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10733. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10748. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10748. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10748. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10748. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10748. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10765. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10765. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10765. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10765. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10765. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10784. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10784. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10784. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10784. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10784. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10805. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10805. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10805. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10805. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10805. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10828. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10828. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10828. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10828. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10828. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10853. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10853. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10853. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10853. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10853. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10880. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10880. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10880. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10880. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10880. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10909. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10909. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10909. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10909. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10909. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10940. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10940. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10940. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10940. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10940. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10973. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10973. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10973. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10973. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10973. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11008. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11008. dead port 4/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11008. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11048. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11048. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11048. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11048. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11048. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11058. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11058. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11058. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11058. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11058. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11072. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11072. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11072. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11072. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11072. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11088. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11088. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11088. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11088. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11088. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11108. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11108. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11108. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11108. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11108. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11132. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11132. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11132. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11132. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11132. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11160. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11160. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11160. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11160. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11160. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11192. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11192. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11192. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11192. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11192. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11228. dead port 3/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11228. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11235. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11235. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11235. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11235. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11235. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11246. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11246. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11246. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11246. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11246. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11268. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11268. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11268. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11268. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11268. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11302. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11302. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11302. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11302. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11332. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11332. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11332. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11332. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11332. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11344. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11344. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11344. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11344. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11344. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11362. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11362. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11362. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11362. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11362. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11370. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11370. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11370. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11370. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11370. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11396. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11396. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11396. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11396. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11396. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5582. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5582. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5582. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5582. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5595. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5595. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5595. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5595. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5610. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5610. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5610. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5610. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5627. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5627. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5627. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5627. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5646. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5646. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5646. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5646. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5667. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5667. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5667. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5667. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5690. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5690. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5690. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5690. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5715. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5715. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5715. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5715. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5742. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5742. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5742. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5742. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5771. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5771. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5771. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5771. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5802. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5802. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5802. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5802. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5835. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5835. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5835. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5835. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5870. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5870. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5870. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5910. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5910. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5910. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5910. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5920. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5920. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5920. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5920. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5934. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5934. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5934. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5934. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5950. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5950. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5950. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5950. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5970. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5970. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5970. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5970. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5994. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5994. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5994. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5994. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6022. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6022. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6022. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6022. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6054. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6054. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6054. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6054. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6090. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6090. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6097. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6097. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6097. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6097. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6108. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6108. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6108. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6108. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6130. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6130. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6130. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6130. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6164. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6164. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6164. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6164. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6194. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6194. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6194. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6194. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6206. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6206. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6206. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6206. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6224. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6224. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6224. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6224. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6232. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6232. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6232. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6232. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6258. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6258. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6258. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6258. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6316. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6316. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6316. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6316. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6316. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6329. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6329. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6329. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6329. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6344. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6344. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6344. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6344. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6361. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6361. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6361. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6361. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6380. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6380. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6380. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6380. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6401. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6401. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6401. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6401. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6424. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6424. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6424. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6424. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6449. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6449. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6449. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6449. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6476. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6476. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6476. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6476. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6505. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6505. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6505. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6505. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6536. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6536. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6536. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6536. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6569. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6569. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6569. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6569. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6604. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6604. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6604. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6644. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6644. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6644. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6644. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6644. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6654. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6654. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6654. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6654. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6668. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6668. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6668. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6668. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6684. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6684. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6684. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6684. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6704. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6704. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6704. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6704. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6728. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6728. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6728. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6728. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6756. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6756. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6756. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6756. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6788. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6788. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6788. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6788. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6824. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6824. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6831. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6831. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6831. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6831. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6831. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6842. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6842. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6842. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6842. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6864. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6864. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6864. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6864. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6898. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6898. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6898. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6898. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6928. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6928. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6928. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6928. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6940. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6940. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6940. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6940. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6958. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6958. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6958. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6958. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6966. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6966. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6966. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6966. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6966. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6992. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6992. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6992. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6992. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7050. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7050. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7050. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7050. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7050. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7063. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7063. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7063. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7063. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7078. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7078. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7078. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7078. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7095. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7095. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7095. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7095. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7114. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7114. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7114. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7114. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7135. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7135. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7135. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7135. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7158. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7158. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7158. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7158. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7158. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7183. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7183. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7183. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7183. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7183. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7210. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7210. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7210. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7210. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7239. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7239. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7239. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7239. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7270. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7270. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7270. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7270. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7303. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7303. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7303. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7303. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7338. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7338. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7338. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7378. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7378. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7378. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7378. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7378. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7388. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7388. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7388. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7388. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7402. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7402. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7402. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7402. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7418. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7418. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7418. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7418. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7438. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7438. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7438. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7438. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7462. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7462. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7462. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7462. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7462. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7490. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7490. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7490. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7490. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7522. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7522. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7522. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7522. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7558. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7558. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7565. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7565. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7565. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7565. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7565. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7576. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7576. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7576. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7576. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7598. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7598. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7598. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7598. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7598. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7632. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7632. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7632. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7632. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7662. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7662. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7662. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7662. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7674. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7674. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7674. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7674. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7692. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7692. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7692. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7692. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7700. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7700. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7700. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7700. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7700. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7726. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7726. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7726. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7726. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7784. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7784. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7784. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7784. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7784. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7797. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7797. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7797. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7797. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7797. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7812. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7812. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7812. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7812. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7829. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7829. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7829. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7829. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7848. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7848. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7848. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7848. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7869. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7869. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7869. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7869. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7892. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7892. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7892. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7892. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7892. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7917. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7917. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7917. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7917. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7917. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7944. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7944. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7944. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7944. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7973. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7973. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7973. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7973. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8004. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8004. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8004. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8004. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8037. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8037. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8037. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8037. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8072. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8072. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8072. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8112. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8112. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8112. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8112. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8112. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8122. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8122. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8122. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8122. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8122. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8136. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8136. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8136. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8136. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8152. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8152. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8152. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8152. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8172. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8172. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8172. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8172. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8196. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8196. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8196. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8196. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8196. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8224. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8224. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8224. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8224. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8256. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8256. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8256. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8256. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8292. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8292. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8299. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8299. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8299. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8299. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8299. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8310. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8310. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8310. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8310. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8310. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8332. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8332. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8332. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8332. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8332. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8366. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8366. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8366. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8366. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8396. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8396. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8396. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8396. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8408. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8408. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8408. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8408. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8408. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8426. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8426. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8426. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8426. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8434. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8434. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8434. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8434. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8434. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8460. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8460. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8460. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8460. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8518. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8518. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8518. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8518. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8518. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8531. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8531. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8531. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8531. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8531. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8546. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8546. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8546. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8546. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8563. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8563. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8563. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8563. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8582. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8582. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8582. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8582. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8603. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8603. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8603. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8603. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8626. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8626. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8626. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8626. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8626. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8651. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8651. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8651. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8651. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8651. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8678. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8678. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8678. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8678. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8678. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8707. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8707. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8707. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8707. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8707. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8738. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8738. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8738. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8738. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8771. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8771. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8771. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8771. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8806. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8806. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8806. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8846. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8846. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8846. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8846. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8846. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8856. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8856. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8856. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8856. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8856. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8870. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8870. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8870. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8870. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8886. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8886. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8886. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8886. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8906. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8906. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8906. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8906. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8930. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8930. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8930. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8930. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8930. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8958. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8958. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8958. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8958. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8958. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8990. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8990. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8990. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8990. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9026. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9026. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9033. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9033. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9033. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9033. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9033. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9044. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9044. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9044. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9044. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9044. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9066. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9066. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9066. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9066. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9066. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9100. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9100. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9100. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9100. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9130. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9130. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9130. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9130. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9142. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9142. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9142. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9142. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9142. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9160. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9160. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9160. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9160. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9168. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9168. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9168. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9168. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9168. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9194. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9194. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9194. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9194. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9194. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9252. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9252. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9252. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9252. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9252. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9265. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9265. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9265. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9265. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9265. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9280. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9280. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9280. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9280. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9280. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9297. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9297. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9297. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9297. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9297. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9316. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9316. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9316. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9316. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9337. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9337. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9337. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9337. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9360. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9360. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9360. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9360. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9360. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9385. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9385. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9385. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9385. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9385. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9412. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9412. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9412. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9412. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9412. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9441. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9441. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9441. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9441. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9441. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9472. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9472. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9472. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9472. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9505. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9505. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9505. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9505. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9540. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9540. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9540. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9580. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9580. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9580. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9580. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9580. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9590. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9590. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9590. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9590. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9590. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9604. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9604. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9604. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9604. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9604. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9620. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9620. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9620. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9620. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9620. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9640. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9640. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9640. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9640. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9664. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9664. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9664. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9664. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9664. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9692. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9692. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9692. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9692. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9692. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9724. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9724. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9724. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9724. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9760. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9760. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9767. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9767. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9767. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9767. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9767. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9778. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9778. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9778. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9778. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9778. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9800. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9800. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9800. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9800. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9800. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9834. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9834. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9834. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9834. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9864. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9864. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9864. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9864. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9876. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9876. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9876. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9876. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9876. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9894. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9894. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9894. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9894. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9902. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9902. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9902. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9902. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9902. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9928. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9928. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9928. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9928. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9928. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9986. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9986. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9986. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9986. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9986. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9999. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9999. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9999. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9999. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9999. dead port 1/2 on $mux $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5524. dead port 2/2 on $mux $flatten\soc_I.\usb_I.$procmux$14937. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11650. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11652. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11654. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11661. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11663. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11669. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11677. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11679. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11686. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11695. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11697. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11705. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11715. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11717. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11726. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11736. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11749. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11752. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11755. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11757. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11759. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11772. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11775. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11777. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11779. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11792. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11794. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11796. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11808. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11810. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11821. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11833. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11846. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11441. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11448. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11456. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11467. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11469. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11471. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11481. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11483. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11492. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11503. Removed 2298 multiplexer ports. <suppressed ~528 debug messages> 73.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $flatten\soc_I.\e1_buf_I.$reduce_or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:195$4952: { \soc_I.cpu_I.do_waitirq \soc_I.e1_buf_I.rx_pending } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12126: $auto$opt_reduce.cc:134:opt_mux$22689 Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$14859: Old ports: A=0, B=255, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_EN[31:0]$3325 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_EN[31:0]$3325 [0] New connections: $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_EN[31:0]$3325 [31:1] = { 24'000000000000000000000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_EN[31:0]$3325 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_EN[31:0]$3325 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_EN[31:0]$3325 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_EN[31:0]$3325 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_EN[31:0]$3325 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_EN[31:0]$3325 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_EN[31:0]$3325 [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$14865: Old ports: A=0, B=65280, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN[31:0]$3328 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN[31:0]$3328 [8] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN[31:0]$3328 [31:9] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN[31:0]$3328 [7:0] } = { 16'0000000000000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN[31:0]$3328 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN[31:0]$3328 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN[31:0]$3328 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN[31:0]$3328 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN[31:0]$3328 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN[31:0]$3328 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN[31:0]$3328 [8] 8'00000000 } New ctrl vector for $mux cell $flatten\soc_I.\cpu_I.$procmux$12089: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12407: { $flatten\soc_I.\cpu_I.$procmux$12121_CMP $auto$opt_reduce.cc:134:opt_mux$22691 } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$14871: Old ports: A=0, B=16711680, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN[31:0]$3331 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN[31:0]$3331 [16] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN[31:0]$3331 [31:17] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN[31:0]$3331 [15:0] } = { 8'00000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN[31:0]$3331 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN[31:0]$3331 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN[31:0]$3331 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN[31:0]$3331 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN[31:0]$3331 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN[31:0]$3331 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN[31:0]$3331 [16] 16'0000000000000000 } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$14877: Old ports: A=0, B=32'11111111000000000000000000000000, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN[31:0]$3334 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN[31:0]$3334 [24] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN[31:0]$3334 [31:25] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN[31:0]$3334 [23:0] } = { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN[31:0]$3334 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN[31:0]$3334 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN[31:0]$3334 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN[31:0]$3334 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN[31:0]$3334 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN[31:0]$3334 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN[31:0]$3334 [24] 24'000000000000000000000000 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12420: { $auto$opt_reduce.cc:134:opt_mux$22693 $flatten\soc_I.\cpu_I.$procmux$12099_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12433: { $flatten\soc_I.\cpu_I.$procmux$12130_CMP $auto$opt_reduce.cc:134:opt_mux$22695 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12659: { $flatten\soc_I.\cpu_I.$procmux$12130_CMP $flatten\soc_I.\cpu_I.$procmux$12129_CMP $flatten\soc_I.\cpu_I.$procmux$12099_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12718: { \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$22697 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12760: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3884_Y $flatten\soc_I.\cpu_I.$procmux$12130_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12857: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3884_Y $flatten\soc_I.\cpu_I.$procmux$12130_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12900: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3884_Y $flatten\soc_I.\cpu_I.$procmux$12130_CMP $auto$opt_reduce.cc:134:opt_mux$22699 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12108: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13006: { \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$22701 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13178: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3884_Y $flatten\soc_I.\cpu_I.$procmux$12110_CMP $flatten\soc_I.\cpu_I.$procmux$12109_CMP $flatten\soc_I.\cpu_I.$procmux$12129_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13204: { \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$22703 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13366: { $auto$opt_reduce.cc:134:opt_mux$22707 $auto$opt_reduce.cc:134:opt_mux$22705 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13514: $auto$opt_reduce.cc:134:opt_mux$22709 Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$11915: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] New connections: $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [7:1] = { $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$11915: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] New connections: $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [7:1] = { $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN[7:0]$5116 [0] } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.$procmux$14933: { $flatten\soc_I.\iobuf_I.\dma_I.$eq$/build/gateware/common/rtl/wb_dma.v:183$4803_Y $flatten\soc_I.\iobuf_I.\dma_I.$eq$/build/gateware/common/rtl/wb_dma.v:164$4794_Y } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\phy_I.$procmux$5420: { $auto$opt_reduce.cc:134:opt_mux$22717 $auto$opt_reduce.cc:134:opt_mux$22715 $flatten\soc_I.\usb_I.\phy_I.$procmux$5429_CMP $flatten\soc_I.\usb_I.\phy_I.$procmux$5428_CMP $auto$opt_reduce.cc:134:opt_mux$22713 $auto$opt_reduce.cc:134:opt_mux$22711 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\phy_I.$procmux$5437: { $auto$opt_reduce.cc:134:opt_mux$22725 $auto$opt_reduce.cc:134:opt_mux$22723 $flatten\soc_I.\usb_I.\phy_I.$procmux$5446_CMP $flatten\soc_I.\usb_I.\phy_I.$procmux$5445_CMP $auto$opt_reduce.cc:134:opt_mux$22721 $auto$opt_reduce.cc:134:opt_mux$22719 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11860: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11868_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11867_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11866_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11865_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11864_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11863_CMP $auto$opt_reduce.cc:134:opt_mux$22727 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11892: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11896_CMP $auto$opt_reduce.cc:134:opt_mux$22729 $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11893_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11903: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11910_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11909_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11908_CMP $auto$opt_reduce.cc:134:opt_mux$22731 $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11906_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11905_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11904_CMP } Optimizing cells in module \top. Performed a total of 29 changes. 73.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~39 debug messages> Removed a total of 13 cells. 73.10.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$22445 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$22406 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$22406 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$22405 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$22405 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 16 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 17 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 18 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 19 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 20 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 21 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 22 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 23 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 24 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 25 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 26 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 27 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 28 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 29 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 30 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 31 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 32 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 33 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 34 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 35 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 36 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 37 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 38 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 39 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 40 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 41 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 42 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 43 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 44 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 45 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 46 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 47 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 48 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 49 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 50 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 51 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 52 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 53 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 54 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 55 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 56 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 57 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 58 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 59 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 60 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 61 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 62 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 1-bit at position 63 on $flatten\soc_I.\cpu_I.$procdff$22403 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22364 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$22259 ($dff) from module top. Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21923 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21856 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21789 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21722 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21655 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21444 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21233 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21022 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20811 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20600 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20389 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20178 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19967 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19756 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19545 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19334 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19123 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18912 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18701 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18490 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18279 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18068 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17857 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17646 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17435 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17224 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17013 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16802 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16591 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16380 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16169 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15958 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15747 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15536 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15373 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15258 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21990 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21923 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21856 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21789 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21722 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21655 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21444 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21233 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21022 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20811 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20600 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20389 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20178 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19967 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19756 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19545 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19334 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19123 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18912 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18701 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18490 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18279 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18068 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17857 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17646 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17435 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17224 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17013 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16802 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16591 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16380 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16169 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15958 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15747 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15536 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15373 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$15258 ($dlatch) from module top (changing to combinatorial circuit). Setting constant 0-bit at position 0 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\e1_buf_I.$procdff$22550 ($dff) from module top. 73.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 29 unused cells and 636 unused wires. <suppressed ~83 debug messages> 73.10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~4 debug messages> 73.10.9. Rerunning OPT passes. (Maybe there is more to do..) 73.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~458 debug messages> 73.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $flatten\soc_I.\e1_buf_I.$reduce_or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:195$4952: \soc_I.e1_buf_I.rx_pending New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12530: $auto$opt_reduce.cc:134:opt_mux$22733 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12547: { $flatten\soc_I.\cpu_I.$procmux$12130_CMP $auto$opt_reduce.cc:134:opt_mux$22735 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12965: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3884_Y $flatten\soc_I.\cpu_I.$procmux$12110_CMP $flatten\soc_I.\cpu_I.$procmux$12109_CMP $flatten\soc_I.\cpu_I.$procmux$12130_CMP $flatten\soc_I.\cpu_I.$procmux$12129_CMP $auto$opt_reduce.cc:134:opt_mux$22737 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14428: { $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:364$3481_Y $auto$opt_reduce.cc:134:opt_mux$22739 } Optimizing cells in module \top. Performed a total of 5 changes. 73.10.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 73.10.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22357 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$22259 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$22586 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$22583 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$22580 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$22577 ($dff) from module top. 73.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 6 unused wires. <suppressed ~1 debug messages> 73.10.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~6 debug messages> 73.10.16. Rerunning OPT passes. (Maybe there is more to do..) 73.10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~458 debug messages> 73.10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.10.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.10.20. Executing OPT_DFF pass (perform DFF optimizations). 73.10.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 7 unused wires. <suppressed ~3 debug messages> 73.10.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.10.23. Rerunning OPT passes. (Maybe there is more to do..) 73.10.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~458 debug messages> 73.10.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.10.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.10.27. Executing OPT_DFF pass (perform DFF optimizations). 73.10.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.10.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.10.30. Finished OPT passes. (There is nothing left to do.) 73.11. Executing FSM pass (extract and optimize FSM). 73.11.1. Executing FSM_DETECT pass (finding FSMs in design). Found FSM state register top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.fsm_state. Found FSM state register top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.fsm_state. Not marking top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5112_EN as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.cpu_I.cpu_state. Not marking top.soc_I.cpu_I.mem_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.cpu_I.mem_wordsize. Not marking top.soc_I.e1_buf_I.t_chan as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.iobuf_I.dma_I.state as FSM state register: Users of register don't seem to benefit from recoding. Circuit seems to be self-resetting. Not marking top.soc_I.iobuf_I.epbam_arb_I.sel as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.iobuf_I.spram_arb_I.sel as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.phy_I.dn_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.phy_I.dp_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_eop_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_rep_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_sync_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.samp_cnt as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.usb_I.rx_pkt_I.state. Not marking top.soc_I.usb_I.trans_I.epfw_state as FSM state register: Users of register don't seem to benefit from recoding. Circuit seems to be self-resetting. Not marking top.soc_I.usb_I.tx_ll_I.out_sym as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.tx_ll_I.state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.usb_I.tx_pkt_I.state. 73.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.fsm_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22680 root of input selection tree: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$22_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.crc_I.in_valid found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15160_CMP found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$47_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$46_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.align_frame found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$24_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$30_Y found state code: 3'100 found state code: 3'000 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf found state code: 3'011 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.fas_pos found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.data [6] found state code: 3'001 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.data_match_fas found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.ctrl_mode_mf found state code: 3'010 found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15160_CMP found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$139_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$71_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$70_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$47_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$46_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.align_frame ctrl inputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.data [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.data_match_fas $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.fas_pos $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$22_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$24_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$30_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.crc_I.in_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.ctrl_mode_mf } ctrl outputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.align_frame $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$46_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$47_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$70_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$71_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$139_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15160_CMP } transition: 3'000 10'-----0--0- -> 3'000 10'1000001100 transition: 3'000 10'-0---0--1- -> 3'000 10'1000001100 transition: 3'000 10'-1---0--1- -> 3'001 10'1001001100 transition: 3'000 10'-----1---- -> 3'000 10'1000001100 transition: 3'100 10'-----0--0- -> 3'100 10'0100001010 transition: 3'100 10'-----0--1- -> 3'100 10'0100001010 transition: 3'100 10'-----1---- -> 3'000 10'0000001010 transition: 3'010 10'-----0--0- -> 3'010 10'0010010100 transition: 3'010 10'-----00-1- -> 3'010 10'0010010100 transition: 3'010 10'---0001-1- -> 3'010 10'0010010100 transition: 3'010 10'---0101-1- -> 3'011 10'0011010100 transition: 3'010 10'---1-01-1- -> 3'000 10'0000010100 transition: 3'010 10'-----1---- -> 3'000 10'0000010100 transition: 3'001 10'-----0--0- -> 3'001 10'0001101100 transition: 3'001 10'-----00-1- -> 3'001 10'0001101100 transition: 3'001 10'0-0--01-1- -> 3'000 10'0000101100 transition: 3'001 10'1-0--01-1- -> 3'001 10'0001101100 transition: 3'001 10'-01--01-1- -> 3'000 10'0000101100 transition: 3'001 10'-11--01-10 -> 3'100 10'0100101100 transition: 3'001 10'-11--01-11 -> 3'010 10'0010101100 transition: 3'001 10'-----1---- -> 3'000 10'0000101100 transition: 3'011 10'-----0--0- -> 3'011 10'0011001101 transition: 3'011 10'-----00-1- -> 3'011 10'0011001101 transition: 3'011 10'---0-0101- -> 3'011 10'0011001101 transition: 3'011 10'---0-0111- -> 3'100 10'0100001101 transition: 3'011 10'---1-01-1- -> 3'000 10'0000001101 transition: 3'011 10'-----1---- -> 3'000 10'0000001101 Extracting FSM `$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.fsm_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22680 root of input selection tree: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$22_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.crc_I.in_valid found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15160_CMP found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$47_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$46_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.align_frame found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$24_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.mfa_timeout [6] found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$30_Y found state code: 3'100 found state code: 3'000 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf found state code: 3'011 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.fas_pos found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.data [6] found state code: 3'001 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.data_match_fas found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.ctrl_mode_mf found state code: 3'010 found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15160_CMP found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$139_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$71_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$70_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$47_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$46_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.align_frame ctrl inputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.data [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.data_match_fas $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.fas_pos $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.mfa_timeout [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$22_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$24_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$30_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.crc_I.in_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.ctrl_mode_mf } ctrl outputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.align_frame $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$46_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$47_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$70_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$71_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$139_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15160_CMP } transition: 3'000 10'-----0--0- -> 3'000 10'1000001100 transition: 3'000 10'-0---0--1- -> 3'000 10'1000001100 transition: 3'000 10'-1---0--1- -> 3'001 10'1001001100 transition: 3'000 10'-----1---- -> 3'000 10'1000001100 transition: 3'100 10'-----0--0- -> 3'100 10'0100001010 transition: 3'100 10'-----0--1- -> 3'100 10'0100001010 transition: 3'100 10'-----1---- -> 3'000 10'0000001010 transition: 3'010 10'-----0--0- -> 3'010 10'0010010100 transition: 3'010 10'-----00-1- -> 3'010 10'0010010100 transition: 3'010 10'---0001-1- -> 3'010 10'0010010100 transition: 3'010 10'---0101-1- -> 3'011 10'0011010100 transition: 3'010 10'---1-01-1- -> 3'000 10'0000010100 transition: 3'010 10'-----1---- -> 3'000 10'0000010100 transition: 3'001 10'-----0--0- -> 3'001 10'0001101100 transition: 3'001 10'-----00-1- -> 3'001 10'0001101100 transition: 3'001 10'0-0--01-1- -> 3'000 10'0000101100 transition: 3'001 10'1-0--01-1- -> 3'001 10'0001101100 transition: 3'001 10'-01--01-1- -> 3'000 10'0000101100 transition: 3'001 10'-11--01-10 -> 3'100 10'0100101100 transition: 3'001 10'-11--01-11 -> 3'010 10'0010101100 transition: 3'001 10'-----1---- -> 3'000 10'0000101100 transition: 3'011 10'-----0--0- -> 3'011 10'0011001101 transition: 3'011 10'-----00-1- -> 3'011 10'0011001101 transition: 3'011 10'---0-0101- -> 3'011 10'0011001101 transition: 3'011 10'---0-0111- -> 3'100 10'0100001101 transition: 3'011 10'---1-01-1- -> 3'000 10'0000001101 transition: 3'011 10'-----1---- -> 3'000 10'0000001101 Extracting FSM `\soc_I.cpu_I.cpu_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\cpu_I.$procdff$22428 root of input selection tree: $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] found reset state: 8'10000000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4072_Y found ctrl input: \soc_I.pb_rst_n found state code: 8'01000000 found ctrl input: $auto$opt_reduce.cc:134:opt_mux$22733 found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12129_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12130_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12109_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12110_CMP found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3884_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4031_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4035_Y found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4013_Y found ctrl input: \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu found ctrl input: \soc_I.cpu_I.mem_done found ctrl input: \soc_I.cpu_I.is_sll_srl_sra found ctrl input: \soc_I.cpu_I.is_sb_sh_sw found state code: 8'00001000 found state code: 8'00000100 found state code: 8'00000010 found ctrl input: $auto$opt_reduce.cc:134:opt_mux$22701 found ctrl input: \soc_I.cpu_I.is_slli_srli_srai found ctrl input: \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu found state code: 8'00000001 found ctrl input: \soc_I.cpu_I.decoder_trigger found ctrl input: \soc_I.cpu_I.instr_jal found state code: 8'00100000 found state code: 8'10000000 found ctrl output: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3884_Y found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12099_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12109_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12110_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12121_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12129_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12130_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12134_CMP ctrl inputs: { $auto$opt_reduce.cc:134:opt_mux$22733 $auto$opt_reduce.cc:134:opt_mux$22701 \soc_I.pb_rst_n $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4072_Y $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4035_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4031_Y $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4013_Y \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu \soc_I.cpu_I.is_sll_srl_sra \soc_I.cpu_I.is_sb_sh_sw \soc_I.cpu_I.is_slli_srli_srai \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.decoder_trigger \soc_I.cpu_I.instr_jal \soc_I.cpu_I.mem_done } ctrl outputs: { $flatten\soc_I.\cpu_I.$procmux$12134_CMP $flatten\soc_I.\cpu_I.$procmux$12130_CMP $flatten\soc_I.\cpu_I.$procmux$12129_CMP $flatten\soc_I.\cpu_I.$procmux$12121_CMP $flatten\soc_I.\cpu_I.$procmux$12110_CMP $flatten\soc_I.\cpu_I.$procmux$12109_CMP $flatten\soc_I.\cpu_I.$procmux$12099_CMP $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3884_Y } transition: 8'10000000 15'--00----------- -> 8'01000000 16'1000000010000000 transition: 8'10000000 15'--10----------- -> 8'10000000 16'1000000100000000 transition: 8'10000000 15'---1----------- -> 8'10000000 16'1000000100000000 transition: 8'01000000 15'--00----------- -> 8'01000000 16'0000000010000001 transition: 8'01000000 15'--10--------0-- -> 8'01000000 16'0000000010000001 transition: 8'01000000 15'--10--------10- -> 8'00100000 16'0000000001000001 transition: 8'01000000 15'--10--------11- -> 8'01000000 16'0000000010000001 transition: 8'01000000 15'---1----------- -> 8'10000000 16'0000000100000001 transition: 8'00100000 15'--00----------- -> 8'01000000 16'0000100010000000 transition: 8'00100000 15'-010----0000--- -> 8'00001000 16'0000100000010000 transition: 8'00100000 15'-010-----100--- -> 8'00000010 16'0000100000000100 transition: 8'00100000 15'-010----1-00--- -> 8'00000100 16'0000100000001000 transition: 8'00100000 15'--10-------1--- -> 8'00000001 16'0000100000000010 transition: 8'00100000 15'--10------1---- -> 8'00000100 16'0000100000001000 transition: 8'00100000 15'-110----------- -> 8'00001000 16'0000100000010000 transition: 8'00100000 15'---1----------- -> 8'10000000 16'0000100100000000 transition: 8'00001000 15'--00----------- -> 8'01000000 16'0100000010000000 transition: 8'00001000 15'--10---0------- -> 8'01000000 16'0100000010000000 transition: 8'00001000 15'--10---1------0 -> 8'00001000 16'0100000000010000 transition: 8'00001000 15'--10---1------1 -> 8'01000000 16'0100000010000000 transition: 8'00001000 15'---1----------- -> 8'10000000 16'0100000100000000 transition: 8'00000100 15'--00----------- -> 8'01000000 16'0010000010000000 transition: 8'00000100 15'--10--0-------- -> 8'00000100 16'0010000000001000 transition: 8'00000100 15'--10--1-------- -> 8'01000000 16'0010000010000000 transition: 8'00000100 15'---1----------- -> 8'10000000 16'0010000100000000 transition: 8'00000010 15'--00----------- -> 8'01000000 16'0001000010000000 transition: 8'00000010 15'--10-0--------- -> 8'00000010 16'0001000000000100 transition: 8'00000010 15'--1001--------- -> 8'00000010 16'0001000000000100 transition: 8'00000010 15'--1011--------- -> 8'01000000 16'0001000010000000 transition: 8'00000010 15'---1----------- -> 8'10000000 16'0001000100000000 transition: 8'00000001 15'--00----------- -> 8'01000000 16'0000001010000000 transition: 8'00000001 15'--10-0--------- -> 8'00000001 16'0000001000000010 transition: 8'00000001 15'--1001--------- -> 8'00000001 16'0000001000000010 transition: 8'00000001 15'--1011--------- -> 8'01000000 16'0000001010000000 transition: 8'00000001 15'---1----------- -> 8'10000000 16'0000001100000000 Extracting FSM `\soc_I.cpu_I.mem_wordsize' from module `\top'. found $dff cell for state register: $flatten\soc_I.\cpu_I.$procdff$22415 root of input selection tree: $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] found ctrl input: \soc_I.pb_rst_n found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12099_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12121_CMP found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3884_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4031_Y found ctrl input: \soc_I.cpu_I.mem_do_rdata found ctrl input: \soc_I.cpu_I.instr_lw found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4040_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4039_Y found state code: 2'00 found state code: 2'01 found state code: 2'10 found ctrl input: \soc_I.cpu_I.mem_do_wdata found ctrl input: \soc_I.cpu_I.instr_sw found ctrl input: \soc_I.cpu_I.instr_sh found ctrl input: \soc_I.cpu_I.instr_sb found ctrl output: $flatten\soc_I.\cpu_I.$procmux$14675_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$14682_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$14687_CMP ctrl inputs: { \soc_I.pb_rst_n $flatten\soc_I.\cpu_I.$procmux$12121_CMP $flatten\soc_I.\cpu_I.$procmux$12099_CMP $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4040_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4039_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4031_Y $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3884_Y \soc_I.cpu_I.instr_sw \soc_I.cpu_I.instr_sh \soc_I.cpu_I.instr_sb \soc_I.cpu_I.instr_lw \soc_I.cpu_I.mem_do_wdata \soc_I.cpu_I.mem_do_rdata } ctrl outputs: { $flatten\soc_I.\cpu_I.$procmux$14687_CMP $flatten\soc_I.\cpu_I.$procmux$14682_CMP $flatten\soc_I.\cpu_I.$procmux$14675_CMP $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] } transition: 2'00 13'0------------ -> 2'00 5'10000 transition: 2'00 13'100---0------ -> 2'00 5'10000 transition: 2'00 13'1-----1------ -> 2'00 5'10000 transition: 2'00 13'11---0------- -> 2'00 5'10000 transition: 2'00 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!> transition: 2'00 13'11---1---1-0- -> 2'10 5'10010 transition: 2'00 13'11---1--1--0- -> 2'01 5'10001 transition: 2'00 13'11---1-1---0- -> 2'00 5'10000 transition: 2'00 13'11---1-----1- -> 2'00 5'10000 transition: 2'00 13'1-1--0------- -> 2'00 5'10000 transition: 2'00 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!> transition: 2'00 13'1-1-11------0 -> 2'10 5'10010 transition: 2'00 13'1-11-1------0 -> 2'01 5'10001 transition: 2'00 13'1-1--1----1-0 -> 2'00 5'10000 transition: 2'00 13'1-1--1------1 -> 2'00 5'10000 transition: 2'10 13'0------------ -> 2'10 5'00110 transition: 2'10 13'100---0------ -> 2'10 5'00110 transition: 2'10 13'1-----1------ -> 2'00 5'00100 transition: 2'10 13'11---0------- -> 2'10 5'00110 transition: 2'10 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!> transition: 2'10 13'11---1---1-0- -> 2'10 5'00110 transition: 2'10 13'11---1--1--0- -> 2'01 5'00101 transition: 2'10 13'11---1-1---0- -> 2'00 5'00100 transition: 2'10 13'11---1-----1- -> 2'10 5'00110 transition: 2'10 13'1-1--0------- -> 2'10 5'00110 transition: 2'10 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!> transition: 2'10 13'1-1-11------0 -> 2'10 5'00110 transition: 2'10 13'1-11-1------0 -> 2'01 5'00101 transition: 2'10 13'1-1--1----1-0 -> 2'00 5'00100 transition: 2'10 13'1-1--1------1 -> 2'10 5'00110 transition: 2'01 13'0------------ -> 2'01 5'01001 transition: 2'01 13'100---0------ -> 2'01 5'01001 transition: 2'01 13'1-----1------ -> 2'00 5'01000 transition: 2'01 13'11---0------- -> 2'01 5'01001 transition: 2'01 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!> transition: 2'01 13'11---1---1-0- -> 2'10 5'01010 transition: 2'01 13'11---1--1--0- -> 2'01 5'01001 transition: 2'01 13'11---1-1---0- -> 2'00 5'01000 transition: 2'01 13'11---1-----1- -> 2'01 5'01001 transition: 2'01 13'1-1--0------- -> 2'01 5'01001 transition: 2'01 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!> transition: 2'01 13'1-1-11------0 -> 2'10 5'01010 transition: 2'01 13'1-11-1------0 -> 2'01 5'01001 transition: 2'01 13'1-1--1----1-0 -> 2'00 5'01000 transition: 2'01 13'1-1--1------1 -> 2'01 5'01001 Extracting FSM `\soc_I.usb_I.rx_pkt_I.state' from module `\top'. found $adff cell for state register: $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22339 root of input selection tree: \soc_I.usb_I.rx_pkt_I.state_nxt found reset state: 4'0000 (from async reset) found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1405_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11680_CMP found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1391_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1388_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11760_CMP found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1342_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] found ctrl input: \soc_I.usb_I.rx_ll_I.dec_valid_1 found ctrl input: \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] found ctrl input: \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] found state code: 4'0011 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1323_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1317_Y found ctrl input: \soc_I.usb_I.rx_pkt_I.llu_byte_stb found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1321_Y found state code: 4'0110 found state code: 4'0101 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1316_Y found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_valid found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_sof found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_token found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_data found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_handshake found state code: 4'0111 found state code: 4'0100 found state code: 4'0010 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1312_Y found state code: 4'0001 found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11760_CMP found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11680_CMP found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1405_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1391_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1388_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1342_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] ctrl inputs: { \soc_I.usb_I.rx_pkt_I.llu_byte_stb \soc_I.usb_I.rx_pkt_I.pid_valid \soc_I.usb_I.rx_pkt_I.pid_is_sof \soc_I.usb_I.rx_pkt_I.pid_is_token \soc_I.usb_I.rx_pkt_I.pid_is_data \soc_I.usb_I.rx_pkt_I.pid_is_handshake $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1312_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1316_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1317_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1321_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1323_Y \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] \soc_I.usb_I.rx_ll_I.dec_valid_1 } ctrl outputs: { \soc_I.usb_I.rx_pkt_I.state_nxt $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1342_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1388_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1391_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1405_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11680_CMP $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11760_CMP } transition: 4'0000 14'------0------- -> 4'0000 12'000010000000 transition: 4'0000 14'------1------- -> 4'0001 12'000110000000 transition: 4'0100 14'0-------0----- -> 4'0100 12'010000010000 transition: 4'0100 14'1-------0----- -> 4'0101 12'010100010000 transition: 4'0100 14'--------1----- -> 4'0011 12'001100010000 transition: 4'0010 14'-0------------ -> 4'0011 12'001100000001 transition: 4'0010 14'-10000-------- -> 4'0011 12'001100000001 transition: 4'0010 14'-10001-------- -> 4'0110 12'011000000001 transition: 4'0010 14'-1001--------- -> 4'0111 12'011100000001 transition: 4'0010 14'-101---------- -> 4'0100 12'010000000001 transition: 4'0010 14'-11----------- -> 4'0100 12'010000000001 transition: 4'0110 14'0-------0----- -> 4'0110 12'011000000010 transition: 4'0110 14'1-------0----- -> 4'0011 12'001100000010 transition: 4'0110 14'--------10---- -> 4'0011 12'001100000010 transition: 4'0110 14'--------11---- -> 4'0000 12'000000000010 transition: 4'0001 14'0------------- -> 4'0001 12'000100100000 transition: 4'0001 14'1------------- -> 4'0010 12'001000100000 transition: 4'0101 14'0-------0----- -> 4'0101 12'010100001000 transition: 4'0101 14'1-------0----- -> 4'0110 12'011000001000 transition: 4'0101 14'--------1----- -> 4'0011 12'001100001000 transition: 4'0011 14'-------0------ -> 4'0011 12'001101000000 transition: 4'0011 14'-------1------ -> 4'0000 12'000001000000 transition: 4'0111 14'-------------0 -> 4'0111 12'011100000100 transition: 4'0111 14'-----------001 -> 4'0111 12'011100000100 transition: 4'0111 14'-----------011 -> 4'0011 12'001100000100 transition: 4'0111 14'----------01-1 -> 4'0011 12'001100000100 transition: 4'0111 14'----------11-1 -> 4'0000 12'000000000100 Extracting FSM `\soc_I.usb_I.tx_pkt_I.state' from module `\top'. found $adff cell for state register: $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22282 root of input selection tree: \soc_I.usb_I.tx_pkt_I.state_nxt found reset state: 4'0000 (from async reset) found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1556_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11431_CMP found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1555_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1557_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1573_Y found ctrl input: \soc_I.usb_I.tx_pkt_I.next found state code: 4'0101 found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1530_Y found state code: 4'0100 found ctrl input: \soc_I.usb_I.tx_pkt_I.pid_is_handshake found ctrl input: \soc_I.usb_I.tx_pkt_I.len [10] found state code: 4'0011 found state code: 4'0010 found ctrl input: \soc_I.usb_I.trans_I.txpkt_start_i found state code: 4'0001 found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11431_CMP found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1573_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1557_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1556_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1555_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] ctrl inputs: { \soc_I.usb_I.trans_I.txpkt_start_i \soc_I.usb_I.tx_pkt_I.pid_is_handshake \soc_I.usb_I.tx_pkt_I.next \soc_I.usb_I.tx_pkt_I.len [10] $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1530_Y } ctrl outputs: { \soc_I.usb_I.tx_pkt_I.state_nxt $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1555_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1556_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1557_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1573_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11431_CMP } transition: 4'0000 5'0---- -> 4'0000 10'0000000100 transition: 4'0000 5'1---- -> 4'0001 10'0001000100 transition: 4'0100 5'--0-- -> 4'0100 10'0100000001 transition: 4'0100 5'--1-- -> 4'0101 10'0101000001 transition: 4'0010 5'--0-- -> 4'0010 10'0010001000 transition: 4'0010 5'-010- -> 4'0011 10'0011001000 transition: 4'0010 5'-011- -> 4'0100 10'0100001000 transition: 4'0010 5'-11-- -> 4'0000 10'0000001000 transition: 4'0001 5'----- -> 4'0010 10'0010000010 transition: 4'0101 5'--0-- -> 4'0101 10'0101010000 transition: 4'0101 5'--1-- -> 4'0000 10'0000010000 transition: 4'0011 5'----0 -> 4'0011 10'0011100000 transition: 4'0011 5'----1 -> 4'0100 10'0100100000 73.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22783' from module `\top'. Optimizing FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22773' from module `\top'. Optimizing FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22768' from module `\top'. Optimizing FSM `$fsm$\soc_I.cpu_I.cpu_state$22758' from module `\top'. Removing unused input signal $auto$opt_reduce.cc:134:opt_mux$22733. Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.fsm_state$22749' from module `\top'. Merging pattern 10'-----0--0- and 10'-----0--1- from group (1 1 10'0100001010). Merging pattern 10'-----0--1- and 10'-----0--0- from group (1 1 10'0100001010). Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.fsm_state$22740' from module `\top'. Merging pattern 10'-----0--0- and 10'-----0--1- from group (1 1 10'0100001010). Merging pattern 10'-----0--1- and 10'-----0--0- from group (1 1 10'0100001010). 73.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 123 unused cells and 123 unused wires. <suppressed ~124 debug messages> 73.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.fsm_state$22740' from module `\top'. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15160_CMP. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.fsm_state$22749' from module `\top'. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15160_CMP. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\soc_I.cpu_I.cpu_state$22758' from module `\top'. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [0]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [1]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [2]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [3]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [4]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [5]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [6]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [7]. Optimizing FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22768' from module `\top'. Removing unused output signal $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] [0]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] [1]. Optimizing FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22773' from module `\top'. Removing unused output signal $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11760_CMP. Removing unused output signal $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11680_CMP. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [0]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [1]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [2]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [3]. Optimizing FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22783' from module `\top'. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [0]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [1]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [2]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [3]. 73.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.fsm_state$22740' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 011 -> 1---- Recoding FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.fsm_state$22749' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 011 -> 1---- Recoding FSM `$fsm$\soc_I.cpu_I.cpu_state$22758' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 10000000 -> ------1 01000000 -> -----1- 00100000 -> ----1-- 00001000 -> ---1--- 00000100 -> --1---- 00000010 -> -1----- 00000001 -> 1------ Recoding FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22768' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> --1 10 -> -1- 01 -> 1-- Recoding FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22773' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -------1 0100 -> ------1- 0010 -> -----1-- 0110 -> ----1--- 0001 -> ---1---- 0101 -> --1----- 0011 -> -1------ 0111 -> 1------- Recoding FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22783' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -----1 0100 -> ----1- 0010 -> ---1-- 0001 -> --1--- 0101 -> -1---- 0011 -> 1----- 73.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.fsm_state$22740' from module `top': ------------------------------------- Information on FSM $fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.fsm_state$22740 ($flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.fsm_state): Number of input signals: 10 Number of output signals: 6 Number of state bits: 5 Input signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.ctrl_mode_mf 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.crc_I.in_valid 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$30_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$24_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$22_Y 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf 6: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] 7: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.fas_pos 8: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.data_match_fas 9: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.data [6] Output signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$139_Y 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$71_Y 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$70_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$47_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$46_Y 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.align_frame State encoding: 0: 5'----1 <RESET STATE> 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 10'-----0--0- -> 0 6'100110 1: 0 10'-0---0--1- -> 0 6'100110 2: 0 10'-----1---- -> 0 6'100110 3: 0 10'-1---0--1- -> 3 6'100110 4: 1 10'-----1---- -> 0 6'000101 5: 1 10'-----0---- -> 1 6'000101 6: 2 10'---1-01-1- -> 0 6'001010 7: 2 10'-----1---- -> 0 6'001010 8: 2 10'-----0--0- -> 2 6'001010 9: 2 10'-----00-1- -> 2 6'001010 10: 2 10'---0001-1- -> 2 6'001010 11: 2 10'---0101-1- -> 4 6'001010 12: 3 10'0-0--01-1- -> 0 6'010110 13: 3 10'-01--01-1- -> 0 6'010110 14: 3 10'-----1---- -> 0 6'010110 15: 3 10'-11--01-10 -> 1 6'010110 16: 3 10'-11--01-11 -> 2 6'010110 17: 3 10'-----0--0- -> 3 6'010110 18: 3 10'-----00-1- -> 3 6'010110 19: 3 10'1-0--01-1- -> 3 6'010110 20: 4 10'---1-01-1- -> 0 6'000110 21: 4 10'-----1---- -> 0 6'000110 22: 4 10'---0-0111- -> 1 6'000110 23: 4 10'-----0--0- -> 4 6'000110 24: 4 10'---0-0101- -> 4 6'000110 25: 4 10'-----00-1- -> 4 6'000110 ------------------------------------- FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.fsm_state$22749' from module `top': ------------------------------------- Information on FSM $fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.fsm_state$22749 ($flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.fsm_state): Number of input signals: 10 Number of output signals: 6 Number of state bits: 5 Input signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.ctrl_mode_mf 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.crc_I.in_valid 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$30_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$24_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$22_Y 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf 6: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.mfa_timeout [6] 7: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.fas_pos 8: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.data_match_fas 9: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.data [6] Output signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$139_Y 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$71_Y 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$70_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$47_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$46_Y 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.align_frame State encoding: 0: 5'----1 <RESET STATE> 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 10'-----0--0- -> 0 6'100110 1: 0 10'-0---0--1- -> 0 6'100110 2: 0 10'-----1---- -> 0 6'100110 3: 0 10'-1---0--1- -> 3 6'100110 4: 1 10'-----1---- -> 0 6'000101 5: 1 10'-----0---- -> 1 6'000101 6: 2 10'---1-01-1- -> 0 6'001010 7: 2 10'-----1---- -> 0 6'001010 8: 2 10'-----0--0- -> 2 6'001010 9: 2 10'-----00-1- -> 2 6'001010 10: 2 10'---0001-1- -> 2 6'001010 11: 2 10'---0101-1- -> 4 6'001010 12: 3 10'0-0--01-1- -> 0 6'010110 13: 3 10'-01--01-1- -> 0 6'010110 14: 3 10'-----1---- -> 0 6'010110 15: 3 10'-11--01-10 -> 1 6'010110 16: 3 10'-11--01-11 -> 2 6'010110 17: 3 10'-----0--0- -> 3 6'010110 18: 3 10'-----00-1- -> 3 6'010110 19: 3 10'1-0--01-1- -> 3 6'010110 20: 4 10'---1-01-1- -> 0 6'000110 21: 4 10'-----1---- -> 0 6'000110 22: 4 10'---0-0111- -> 1 6'000110 23: 4 10'-----0--0- -> 4 6'000110 24: 4 10'---0-0101- -> 4 6'000110 25: 4 10'-----00-1- -> 4 6'000110 ------------------------------------- FSM `$fsm$\soc_I.cpu_I.cpu_state$22758' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.cpu_I.cpu_state$22758 (\soc_I.cpu_I.cpu_state): Number of input signals: 14 Number of output signals: 8 Number of state bits: 7 Input signals: 0: \soc_I.cpu_I.mem_done 1: \soc_I.cpu_I.instr_jal 2: \soc_I.cpu_I.decoder_trigger 3: \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu 4: \soc_I.cpu_I.is_slli_srli_srai 5: \soc_I.cpu_I.is_sb_sh_sw 6: \soc_I.cpu_I.is_sll_srl_sra 7: \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu 8: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4013_Y 9: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4031_Y 10: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4035_Y 11: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4072_Y 12: \soc_I.pb_rst_n 13: $auto$opt_reduce.cc:134:opt_mux$22701 Output signals: 0: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3884_Y 1: $flatten\soc_I.\cpu_I.$procmux$12099_CMP 2: $flatten\soc_I.\cpu_I.$procmux$12109_CMP 3: $flatten\soc_I.\cpu_I.$procmux$12110_CMP 4: $flatten\soc_I.\cpu_I.$procmux$12121_CMP 5: $flatten\soc_I.\cpu_I.$procmux$12129_CMP 6: $flatten\soc_I.\cpu_I.$procmux$12130_CMP 7: $flatten\soc_I.\cpu_I.$procmux$12134_CMP State encoding: 0: 7'------1 <RESET STATE> 1: 7'-----1- 2: 7'----1-- 3: 7'---1--- 4: 7'--1---- 5: 7'-1----- 6: 7'1------ Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 14'-10----------- -> 0 8'10000000 1: 0 14'--1----------- -> 0 8'10000000 2: 0 14'-00----------- -> 1 8'10000000 3: 1 14'--1----------- -> 0 8'00000001 4: 1 14'-10--------11- -> 1 8'00000001 5: 1 14'-10--------0-- -> 1 8'00000001 6: 1 14'-00----------- -> 1 8'00000001 7: 1 14'-10--------10- -> 2 8'00000001 8: 2 14'--1----------- -> 0 8'00001000 9: 2 14'-00----------- -> 1 8'00001000 10: 2 14'010----0000--- -> 3 8'00001000 11: 2 14'110----------- -> 3 8'00001000 12: 2 14'010----1-00--- -> 4 8'00001000 13: 2 14'-10------1---- -> 4 8'00001000 14: 2 14'010-----100--- -> 5 8'00001000 15: 2 14'-10-------1--- -> 6 8'00001000 16: 3 14'--1----------- -> 0 8'01000000 17: 3 14'-10---1------1 -> 1 8'01000000 18: 3 14'-10---0------- -> 1 8'01000000 19: 3 14'-00----------- -> 1 8'01000000 20: 3 14'-10---1------0 -> 3 8'01000000 21: 4 14'--1----------- -> 0 8'00100000 22: 4 14'-10--1-------- -> 1 8'00100000 23: 4 14'-00----------- -> 1 8'00100000 24: 4 14'-10--0-------- -> 4 8'00100000 25: 5 14'--1----------- -> 0 8'00010000 26: 5 14'-1011--------- -> 1 8'00010000 27: 5 14'-00----------- -> 1 8'00010000 28: 5 14'-10-0--------- -> 5 8'00010000 29: 5 14'-1001--------- -> 5 8'00010000 30: 6 14'--1----------- -> 0 8'00000010 31: 6 14'-1011--------- -> 1 8'00000010 32: 6 14'-00----------- -> 1 8'00000010 33: 6 14'-10-0--------- -> 6 8'00000010 34: 6 14'-1001--------- -> 6 8'00000010 ------------------------------------- FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22768' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.cpu_I.mem_wordsize$22768 (\soc_I.cpu_I.mem_wordsize): Number of input signals: 13 Number of output signals: 3 Number of state bits: 3 Input signals: 0: \soc_I.cpu_I.mem_do_rdata 1: \soc_I.cpu_I.mem_do_wdata 2: \soc_I.cpu_I.instr_lw 3: \soc_I.cpu_I.instr_sb 4: \soc_I.cpu_I.instr_sh 5: \soc_I.cpu_I.instr_sw 6: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$3884_Y 7: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4031_Y 8: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4039_Y 9: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4040_Y 10: $flatten\soc_I.\cpu_I.$procmux$12099_CMP 11: $flatten\soc_I.\cpu_I.$procmux$12121_CMP 12: \soc_I.pb_rst_n Output signals: 0: $flatten\soc_I.\cpu_I.$procmux$14675_CMP 1: $flatten\soc_I.\cpu_I.$procmux$14682_CMP 2: $flatten\soc_I.\cpu_I.$procmux$14687_CMP State encoding: 0: 3'--1 1: 3'-1- 2: 3'1-- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 13'1-1--1----1-0 -> 0 3'100 1: 0 13'1-1--1------1 -> 0 3'100 2: 0 13'11---1-1---0- -> 0 3'100 3: 0 13'11---1-----1- -> 0 3'100 4: 0 13'100---0------ -> 0 3'100 5: 0 13'1-----1------ -> 0 3'100 6: 0 13'1-1--0------- -> 0 3'100 7: 0 13'11---0------- -> 0 3'100 8: 0 13'0------------ -> 0 3'100 9: 0 13'1-1-11------0 -> 1 3'100 10: 0 13'11---1---1-0- -> 1 3'100 11: 0 13'1-11-1------0 -> 2 3'100 12: 0 13'11---1--1--0- -> 2 3'100 13: 1 13'1-1--1----1-0 -> 0 3'001 14: 1 13'11---1-1---0- -> 0 3'001 15: 1 13'1-----1------ -> 0 3'001 16: 1 13'1-1-11------0 -> 1 3'001 17: 1 13'1-1--1------1 -> 1 3'001 18: 1 13'11---1---1-0- -> 1 3'001 19: 1 13'11---1-----1- -> 1 3'001 20: 1 13'100---0------ -> 1 3'001 21: 1 13'1-1--0------- -> 1 3'001 22: 1 13'11---0------- -> 1 3'001 23: 1 13'0------------ -> 1 3'001 24: 1 13'1-11-1------0 -> 2 3'001 25: 1 13'11---1--1--0- -> 2 3'001 26: 2 13'1-1--1----1-0 -> 0 3'010 27: 2 13'11---1-1---0- -> 0 3'010 28: 2 13'1-----1------ -> 0 3'010 29: 2 13'1-1-11------0 -> 1 3'010 30: 2 13'11---1---1-0- -> 1 3'010 31: 2 13'1-11-1------0 -> 2 3'010 32: 2 13'1-1--1------1 -> 2 3'010 33: 2 13'11---1--1--0- -> 2 3'010 34: 2 13'11---1-----1- -> 2 3'010 35: 2 13'100---0------ -> 2 3'010 36: 2 13'1-1--0------- -> 2 3'010 37: 2 13'11---0------- -> 2 3'010 38: 2 13'0------------ -> 2 3'010 ------------------------------------- FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22773' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.usb_I.rx_pkt_I.state$22773 (\soc_I.usb_I.rx_pkt_I.state): Number of input signals: 14 Number of output signals: 6 Number of state bits: 8 Input signals: 0: \soc_I.usb_I.rx_ll_I.dec_valid_1 1: \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] 2: \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] 3: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1323_Y 4: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1321_Y 5: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1317_Y 6: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1316_Y 7: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1312_Y 8: \soc_I.usb_I.rx_pkt_I.pid_is_handshake 9: \soc_I.usb_I.rx_pkt_I.pid_is_data 10: \soc_I.usb_I.rx_pkt_I.pid_is_token 11: \soc_I.usb_I.rx_pkt_I.pid_is_sof 12: \soc_I.usb_I.rx_pkt_I.pid_valid 13: \soc_I.usb_I.rx_pkt_I.llu_byte_stb Output signals: 0: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1405_Y 1: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1391_Y 2: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1388_Y 3: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1342_Y 4: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] 5: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] State encoding: 0: 8'-------1 <RESET STATE> 1: 8'------1- 2: 8'-----1-- 3: 8'----1--- 4: 8'---1---- 5: 8'--1----- 6: 8'-1------ 7: 8'1------- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 14'------0------- -> 0 6'100000 1: 0 14'------1------- -> 4 6'100000 2: 1 14'0-------0----- -> 1 6'000100 3: 1 14'1-------0----- -> 5 6'000100 4: 1 14'--------1----- -> 6 6'000100 5: 2 14'-101---------- -> 1 6'000000 6: 2 14'-11----------- -> 1 6'000000 7: 2 14'-10001-------- -> 3 6'000000 8: 2 14'-10000-------- -> 6 6'000000 9: 2 14'-0------------ -> 6 6'000000 10: 2 14'-1001--------- -> 7 6'000000 11: 3 14'--------11---- -> 0 6'000000 12: 3 14'0-------0----- -> 3 6'000000 13: 3 14'--------10---- -> 6 6'000000 14: 3 14'1-------0----- -> 6 6'000000 15: 4 14'1------------- -> 2 6'001000 16: 4 14'0------------- -> 4 6'001000 17: 5 14'1-------0----- -> 3 6'000010 18: 5 14'0-------0----- -> 5 6'000010 19: 5 14'--------1----- -> 6 6'000010 20: 6 14'-------1------ -> 0 6'010000 21: 6 14'-------0------ -> 6 6'010000 22: 7 14'----------11-1 -> 0 6'000001 23: 7 14'-----------011 -> 6 6'000001 24: 7 14'----------01-1 -> 6 6'000001 25: 7 14'-------------0 -> 7 6'000001 26: 7 14'-----------001 -> 7 6'000001 ------------------------------------- FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22783' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.usb_I.tx_pkt_I.state$22783 (\soc_I.usb_I.tx_pkt_I.state): Number of input signals: 5 Number of output signals: 6 Number of state bits: 6 Input signals: 0: $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1530_Y 1: \soc_I.usb_I.tx_pkt_I.len [10] 2: \soc_I.usb_I.tx_pkt_I.next 3: \soc_I.usb_I.tx_pkt_I.pid_is_handshake 4: \soc_I.usb_I.trans_I.txpkt_start_i Output signals: 0: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11431_CMP 1: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] 2: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1573_Y 3: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1557_Y 4: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1556_Y 5: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1555_Y State encoding: 0: 6'-----1 <RESET STATE> 1: 6'----1- 2: 6'---1-- 3: 6'--1--- 4: 6'-1---- 5: 6'1----- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 5'0---- -> 0 6'000100 1: 0 5'1---- -> 3 6'000100 2: 1 5'--0-- -> 1 6'000001 3: 1 5'--1-- -> 4 6'000001 4: 2 5'-11-- -> 0 6'001000 5: 2 5'-011- -> 1 6'001000 6: 2 5'--0-- -> 2 6'001000 7: 2 5'-010- -> 5 6'001000 8: 3 5'----- -> 2 6'000010 9: 4 5'--1-- -> 0 6'010000 10: 4 5'--0-- -> 4 6'010000 11: 5 5'----1 -> 1 6'100000 12: 5 5'----0 -> 5 6'100000 ------------------------------------- 73.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.fsm_state$22740' from module `\top'. Mapping FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.fsm_state$22749' from module `\top'. Mapping FSM `$fsm$\soc_I.cpu_I.cpu_state$22758' from module `\top'. Mapping FSM `$fsm$\soc_I.cpu_I.mem_wordsize$22768' from module `\top'. Mapping FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$22773' from module `\top'. Mapping FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$22783' from module `\top'. 73.12. Executing OPT pass (performing simple optimizations). 73.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~38 debug messages> 73.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~96 debug messages> Removed a total of 32 cells. 73.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$12714. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13178. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$13363. Removed 3 multiplexer ports. <suppressed ~451 debug messages> 73.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$22694: { \soc_I.cpu_I.cpu_state [6:4] \soc_I.cpu_I.cpu_state [2:0] } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$22692: \soc_I.cpu_I.cpu_state [5:0] New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$22690: { \soc_I.cpu_I.cpu_state [6] \soc_I.cpu_I.cpu_state [4:0] } Optimizing cells in module \top. Performed a total of 3 changes. 73.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.12.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\sys_mgr_I.$procdff$22265 ($adff) from module top (D = $flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1598_Y [2:0], Q = \sys_mgr_I.rst_cnt [2:0]). Adding EN signal on $flatten\soc_I.\wb_48m_xclk_I.$procdff$22623 ($dff) from module top (D = \soc_I.wb_48m_xclk_I.m_rdata, Q = \soc_I.wb_48m_xclk_I.m_rdata_i). Adding SRST signal on $flatten\soc_I.\wb_48m_xclk_I.$procdff$22622 ($dff) from module top (D = \soc_I.wb_48m_xclk_I.m_rdata_i, Q = \soc_I.wb_48m_xclk_I.s_rdata, rval = 16'0000000000000000). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$procdff$22228 ($dff) from module top (D = \soc_I.usb_I.tx_pkt_I.crc_16_I.state_nxt, Q = \soc_I.usb_I.tx_pkt_I.crc_16_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22280 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1546_Y [3:0], Q = \soc_I.usb_I.tx_pkt_I.shift_bit). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22279 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1552_Y, Q = \soc_I.usb_I.tx_pkt_I.shift_data). Adding SRST signal on $auto$opt_dff.cc:764:run$23349 ($dffe) from module top (D = \soc_I.usb_I.tx_pkt_I.shift_load [7], Q = \soc_I.usb_I.tx_pkt_I.shift_data [7], rval = 1'0). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22278 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$or$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1559_Y, Q = \soc_I.usb_I.tx_pkt_I.shift_last_byte). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22277 ($dff) from module top (D = \soc_I.usb_I.tx_pkt_I.state [5], Q = \soc_I.usb_I.tx_pkt_I.shift_data_crc). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$22275 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1569_Y [10:0], Q = \soc_I.usb_I.tx_pkt_I.len). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22290 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$0\state[2:0], Q = \soc_I.usb_I.tx_ll_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22288 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$and$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:95$1511_Y, Q = \soc_I.usb_I.tx_ll_I.bs_now). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22287 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1509_Y [2:0], Q = \soc_I.usb_I.tx_ll_I.bs_cnt). Adding SRST signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22286 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$xor$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:103$1517_Y, Q = \soc_I.usb_I.tx_ll_I.lvl_prev, rval = 1'1). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$22284 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11513_Y, Q = \soc_I.usb_I.tx_ll_I.out_sym). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22314 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$procmux$11594_Y, Q = \soc_I.usb_I.trans_I.mc_a_reg). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22311 ($dff) from module top (D = \soc_I.usb_I.trans_I.cel_state_i, Q = \soc_I.usb_I.trans_I.trans_cel). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22310 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:286$1443_Y, Q = \soc_I.usb_I.trans_I.trans_dir). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22309 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.token_data [10:7], Q = \soc_I.usb_I.trans_I.trans_endp). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22308 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:284$1442_Y, Q = \soc_I.usb_I.trans_I.trans_is_setup). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22305 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$0\bd_state[2:0], Q = \soc_I.usb_I.trans_I.bd_state). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22302 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:363$1454_Y, Q = \soc_I.usb_I.trans_I.ep_bd_idx_cur). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22301 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [5], Q = \soc_I.usb_I.trans_I.ep_bd_ctrl). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22300 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [4], Q = \soc_I.usb_I.trans_I.ep_bd_dual). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22299 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [2:0], Q = \soc_I.usb_I.trans_I.ep_type). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22296 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$xor$/build/gateware/cores/no2usb//rtl/usb_trans.v:401$1475_Y, Q = \soc_I.usb_I.trans_I.txpkt_pid). Adding SRST signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22293 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1485_Y, Q = \soc_I.usb_I.trans_I.bd_length, rval = 11'00000000000). Adding SRST signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22292 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1487_Y, Q = \soc_I.usb_I.trans_I.xfer_length, rval = 10'0000000000). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$22291 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$procmux$11538_Y, Q = \soc_I.usb_I.trans_I.pkt_pid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$procdff$22227 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc_5_I.state_nxt, Q = \soc_I.usb_I.rx_pkt_I.crc_5_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$procdff$22228 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc_16_I.state_nxt, Q = \soc_I.usb_I.rx_pkt_I.crc_16_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22336 ($dff) from module top (D = { \soc_I.usb_I.rx_ll_I.dec_bit_1 \soc_I.usb_I.rx_pkt_I.data [7:1] }, Q = \soc_I.usb_I.rx_pkt_I.data). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22335 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11637_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_cnt, rval = 4'0110). Adding EN signal on $auto$opt_dff.cc:702:run$23384 ($sdff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1337_Y [3:0], Q = \soc_I.usb_I.rx_pkt_I.bit_cnt). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22334 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11632_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_eop_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23386 ($sdff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:234$1340_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_eop_ok). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22333 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11627_Y, Q = \soc_I.usb_I.rx_pkt_I.crc_in_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23388 ($sdff) from module top (D = 1'0, Q = \soc_I.usb_I.rx_pkt_I.crc_in_first). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22331 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11617_Y, Q = \soc_I.usb_I.rx_pkt_I.crc16_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23390 ($sdff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc16_match, Q = \soc_I.usb_I.rx_pkt_I.crc16_ok). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22330 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11622_Y, Q = \soc_I.usb_I.rx_pkt_I.crc5_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23392 ($sdff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc5_match, Q = \soc_I.usb_I.rx_pkt_I.crc5_ok). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22329 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:306$1368_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_valid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22327 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:329$1386_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_handshake). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22326 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:328$1381_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_data). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22325 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:327$1378_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_token). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22324 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:307$1351_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_sof). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22323 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.data [4:1], Q = \soc_I.usb_I.rx_pkt_I.pid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22322 ($dff) from module top (D = { \soc_I.usb_I.rx_ll_I.dec_bit_1 \soc_I.usb_I.rx_pkt_I.data [7:1] }, Q = \soc_I.usb_I.rx_pkt_I.token_data [7:0]). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$22321 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.data [3:1], Q = \soc_I.usb_I.rx_pkt_I.token_data [10:8]). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22348 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11903_Y, Q = \soc_I.usb_I.rx_ll_I.samp_cnt, rval = 3'101). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22346 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:115$1300_Y, Q = \soc_I.usb_I.rx_ll_I.dec_bit_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22345 ($dff) from module top (D = { \soc_I.usb_I.phy_I.dp_state [1] \soc_I.usb_I.phy_I.dn_state [1] }, Q = \soc_I.usb_I.rx_ll_I.dec_sym_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22343 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11892_Y, Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22342 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11887_Y, Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1). Adding SRST signal on $auto$opt_dff.cc:764:run$23406 ($dffe) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11877_Y, Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1, rval = 4'0000). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22341 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11870_Y, Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1). Adding SRST signal on $auto$opt_dff.cc:764:run$23408 ($dffe) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11860_Y, Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1, rval = 4'0000). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$22340 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:183$1307_Y, Q = \soc_I.usb_I.rx_ll_I.dec_bs_skip_1). Adding EN signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22355 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.dout_2, Q = \soc_I.usb_I.ep_status_I.p_dout_3). Adding EN signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22354 ($dff) from module top (D = $flatten\soc_I.\usb_I.\ep_status_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:82$1273_Y, Q = \soc_I.usb_I.ep_status_I.s_dout_3). Adding SRST signal on $auto$opt_dff.cc:764:run$23412 ($dffe) from module top (D = \soc_I.usb_I.ep_status_I.dout_2, Q = \soc_I.usb_I.ep_status_I.s_dout_3, rval = 16'0000000000000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22618 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:413$3206_Y, Q = \soc_I.usb_I.sof_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22617 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:412$3203_Y, Q = \soc_I.usb_I.rst_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22616 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:414$3209_Y, Q = \soc_I.usb_I.evt_rd_ack, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22614 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:410$3197_Y, Q = \soc_I.usb_I.cr_bus_we, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22612 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:411$3200_Y, Q = \soc_I.usb_I.cel_rel, rval = 1'0). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$22611 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = \soc_I.usb_I.cr_addr). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$22610 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [7], Q = \soc_I.usb_I.cr_addr_chk). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$22609 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [12], Q = \soc_I.usb_I.cr_cel_ena). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$22608 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [15], Q = \soc_I.usb_I.cr_pu_ena). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22607 ($dff) from module top (D = \soc_I.cpu_I.mem_addr [13], Q = \soc_I.usb_I.eps_bus_req, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22606 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:498$3222_Y, Q = \soc_I.usb_I.eps_bus_write, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22605 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:497$3221_Y, Q = \soc_I.usb_I.eps_bus_read, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22602 ($dff) from module top (D = $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3248_Y, Q = \soc_I.usb_I.timeout_suspend, rval = 20'11011100110110000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22601 ($dff) from module top (D = $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3252_Y, Q = \soc_I.usb_I.timeout_reset, rval = 20'10001010110100000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$22599 ($dff) from module top (D = \soc_I.usb_I.cr_pu_ena, Q = \soc_I.usb_I.pad_pu, rval = 1'0). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procdff$22350 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5117_DATA, Q = \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$22256 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4526_Y [8:0], Q = \soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$22255 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528_Y [8:0], Q = \soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$22254 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4531_Y, Q = \soc_I.uart_I.uart_tx_fifo_I.rd_valid). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$22247 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5257_Y [12], Q = \soc_I.uart_I.uart_tx_I.div_cnt [12], rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$22246 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5475_Y, Q = \soc_I.uart_I.uart_tx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$23434 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5260_Y [4:0], Q = \soc_I.uart_I.uart_tx_I.bit_cnt). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$22245 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0], Q = \soc_I.uart_I.uart_tx_I.shift). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procdff$22350 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5117_DATA, Q = \soc_I.uart_I.uart_rx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$22256 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4526_Y [8:0], Q = \soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$22255 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528_Y [8:0], Q = \soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$22254 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4531_Y, Q = \soc_I.uart_I.uart_rx_fifo_I.rd_valid). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$22263 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4497_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.cnt, rval = 2'11). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$22262 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5512_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.state, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23444 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5512_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.state). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.$procdff$22251 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.$procmux$5485_Y, Q = \soc_I.uart_I.uart_rx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$23448 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5242_Y [4:0], Q = \soc_I.uart_I.uart_rx_I.bit_cnt). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_I.$procdff$22250 ($dff) from module top (D = { \soc_I.uart_I.uart_rx_I.gf_I.state \soc_I.uart_I.uart_rx_I.shift [8:1] }, Q = \soc_I.uart_I.uart_rx_I.shift). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22593 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:174$3300_Y, Q = \soc_I.uart_I.ub_wr_div, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22592 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:173$3297_Y, Q = \soc_I.uart_I.ub_wr_data, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22591 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3292_Y, Q = \soc_I.uart_I.ub_rd_ctrl, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22590 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:171$3288_Y, Q = \soc_I.uart_I.ub_rd_data, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22589 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:181$3307_Y, Q = \soc_I.uart_I.ub_ack, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22588 ($dff) from module top (D = { $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3312_Y [31] $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3312_Y [27:12] $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3312_Y [7:0] }, Q = { \soc_I.uart_I.ub_rdata [31] \soc_I.uart_I.ub_rdata [27:12] \soc_I.uart_I.ub_rdata [7:0] }, rval = 25'0000000000000000000000000). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$22588 ($dff) from module top (D = { \soc_I.uart_I.urf_overflow \soc_I.uart_I.uart_tx_fifo_I.rd_empty \soc_I.uart_I.uart_tx_fifo_I.full \soc_I.uart_I.uart_div [11:8] }, Q = { \soc_I.uart_I.ub_rdata [30:28] \soc_I.uart_I.ub_rdata [11:8] }, rval = 7'0000000). Adding EN signal on $flatten\soc_I.\uart_I.$procdff$22587 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:0], Q = \soc_I.uart_I.uart_div). Adding EN signal on $flatten\soc_I.\rgb_I.$procdff$22595 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [4:0], Q = \soc_I.rgb_I.led_ctrl). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22630 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_wmsk, Q = \soc_I.iobuf_I.spram_arb_I.m_wmsk). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22629 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\spram_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:91$4891_Y, Q = \soc_I.iobuf_I.spram_arb_I.m_we). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22628 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_wdata, Q = \soc_I.iobuf_I.spram_arb_I.m_wdata). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22627 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_addr, Q = \soc_I.iobuf_I.spram_arb_I.m_addr). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22626 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\spram_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:121$4904_Y, Q = \soc_I.iobuf_I.spram_arb_I.busy). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22625 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.sel_nxt, Q = \soc_I.iobuf_I.spram_arb_I.sel). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22210 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\epbam_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:91$4839_Y, Q = \soc_I.iobuf_I.epbam_arb_I.m_we). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22209 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.mux_wdata, Q = \soc_I.iobuf_I.epbam_arb_I.m_wdata). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22208 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.mux_addr, Q = \soc_I.iobuf_I.epbam_arb_I.m_addr). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22207 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\epbam_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:121$4850_Y, Q = \soc_I.iobuf_I.epbam_arb_I.busy). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$22206 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.sel_nxt, Q = \soc_I.iobuf_I.epbam_arb_I.sel). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22220 ($adff) from module top (D = \soc_I.iobuf_I.dma_I.state_nxt, Q = \soc_I.iobuf_I.dma_I.state). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22219 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:144$4783_Y, Q = \soc_I.iobuf_I.dma_I.data_reg). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22218 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$4787_Y [13:0], Q = \soc_I.iobuf_I.dma_I.m0_addr_i). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22217 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$4791_Y [8:0], Q = \soc_I.iobuf_I.dma_I.m1_addr_i). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22216 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$4800_Y [12:0], Q = \soc_I.iobuf_I.dma_I.len). Adding SRST signal on $auto$opt_dff.cc:764:run$23487 ($dffe) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4799_Y [12], Q = \soc_I.iobuf_I.dma_I.len [12], rval = 1'0). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$22215 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [14], Q = \soc_I.iobuf_I.dma_I.dir). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22572 ($dff) from module top (D = \soc_I.e1_buf_I.t_nxt_chan, Q = \soc_I.e1_buf_I.t_chan). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22564 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14812_Y, Q = \soc_I.e1_buf_I.wb_wdata_byte). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22563 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14827_Y, Q = \soc_I.e1_buf_I.wb_addr_lsb). Adding SRST signal on $auto$opt_dff.cc:764:run$23492 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14821_Y, Q = \soc_I.e1_buf_I.wb_addr_lsb, rval = 2'00). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22560 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14842_Y, Q = \soc_I.e1_buf_I.wb_addr). Adding SRST signal on $auto$opt_dff.cc:764:run$23496 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$14836_Y, Q = \soc_I.e1_buf_I.wb_addr, rval = 14'00000000000000). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22559 ($dff) from module top (D = { \soc_I.e1_buf_I.buf_rx_mf [6:0] \soc_I.e1_buf_I.buf_rx_frame [3:0] \soc_I.e1_buf_I.buf_rx_ts [4:0] }, Q = \soc_I.e1_buf_I.rx_addr_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22558 ($dff) from module top (D = \soc_I.e1_buf_I.buf_rx_data [7:0], Q = \soc_I.e1_buf_I.rx_data_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22556 ($dff) from module top (D = { \soc_I.e1_buf_I.buf_rx_mf [13:7] \soc_I.e1_buf_I.buf_rx_frame [7:4] \soc_I.e1_buf_I.buf_rx_ts [9:5] }, Q = \soc_I.e1_buf_I.rx_addr_reg[1]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$22555 ($dff) from module top (D = \soc_I.e1_buf_I.buf_rx_data [15:8], Q = \soc_I.e1_buf_I.rx_data_reg[1]). Adding SRST signal on $flatten\soc_I.\e1_I.$procdff$22386 ($dff) from module top (D = \soc_I.e1_I.bus_rdata, Q = \soc_I.e1_I.wb_rdata, rval = 16'0000000000000000). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.\crc_I.$procdff$22685 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$11_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.crc_I.out_crc4). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22683 ($dff) from module top (D = \misc_I.e1_cnt_I[1].sub_I.inc, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.crc_I.in_valid, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22682 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.data [6:0] \soc_I.e1_I.lb_bit [1] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.data). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22681 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:135$20_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.data_match_fas). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22679 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15137_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.bit_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23509 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:215$34_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.bit_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22678 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15142_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.bit_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23511 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$33_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.bit_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22677 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15147_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.bit, rval = 3'000). Adding EN signal on $auto$opt_dff.cc:702:run$23513 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32_Y [2:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.bit). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22676 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15122_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts_is_ts31, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23515 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:227$38_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts_is_ts31). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22675 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15127_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts_is_ts0, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23517 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts_is_ts31, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts_is_ts0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22674 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15132_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts, rval = 5'00001). Adding EN signal on $auto$opt_dff.cc:702:run$23519 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37_Y [4:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22673 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15097_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.frame_mf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23521 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:243$44_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.frame_mf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22672 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15102_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.frame_mf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23523 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.frame_mf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.frame_mf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22671 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15107_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.frame_smf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23525 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:241$43_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.frame_smf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22670 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15112_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.frame_smf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23527 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.frame_smf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.frame_smf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22669 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15117_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.frame, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$23529 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42_Y [3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.frame). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22668 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$xor$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:262$52_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.fas_pos, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22667 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15089_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.mfa_timeout, rval = 7'0111111). Adding EN signal on $auto$opt_dff.cc:702:run$23532 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$56_Y [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.mfa_timeout). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22666 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15074_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23534 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:285$62_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22665 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15079_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23536 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:284$61_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22664 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procmux$15084_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts0_msbs, rval = 16'1111111111111111). Adding EN signal on $auto$opt_dff.cc:702:run$23538 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts0_msbs [14:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.data [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts0_msbs). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22663 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.crc_I.out_crc4, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.crc_smf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22662 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:325$84_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ep_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22661 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:326$90_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ed_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22660 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:323$75_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ep_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22659 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$80_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ed_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22658 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:340$105_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ep_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22657 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:341$110_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ed_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22656 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:338$97_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ep_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22655 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$102_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ed_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22654 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$127_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ec_mfa, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22653 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$123_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ec_crc, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22652 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$119_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ec_nfas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22651 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$115_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ec_fas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22649 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$140_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.out_valid, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22648 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:396$142_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.out_last, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22647 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$141_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.out_first, rval = 1'1). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22645 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.ts, Q = \soc_I.e1_buf_I.buf_rx_ts [9:5], rval = 5'00000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22644 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.frame, Q = \soc_I.e1_buf_I.buf_rx_frame [7:4], rval = 4'0000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22643 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.data, Q = \soc_I.e1_buf_I.buf_rx_data [15:8], rval = 8'00000000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$procdff$22642 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$139_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.aligned, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$procdff$22385 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4127_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.data[1]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$procdff$22384 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4132_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$procdff$22383 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4138_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$procdff$22382 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4143_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$procdff$22381 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4149_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$procdff$22380 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4154_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$procdff$22379 ($adff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.data[5] [8:7] \soc_I.e1_buf_I.buf_rx_mf [13:7] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$procdff$22378 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4165_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.stage[4].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$procdff$22377 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4173_Y, Q = \soc_I.e1_buf_I.buf_rx_mf [13:7]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$procdff$22376 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4178_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_in_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$procdff$22375 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4184_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_in_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$procdff$22374 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4189_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_in_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$procdff$22373 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4195_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_in_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$procdff$22372 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4200_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_in_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$procdff$22371 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_in_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$procdff$22370 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4211_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_in_I.stage[4].l_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$procdff$22243 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:114$5270_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.crx_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$procdff$22242 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:113$5267_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$procmux$5461_CMP, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$procdff$22241 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2:1], Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_mode [1] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.ctrl_mode_mf }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$procdff$22240 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bus_rd_rx_status [0]). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$procdff$22239 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:149$5283_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.rd_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$procdff$22238 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:148$5277_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_in_I.wr_ena, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.\crc_I.$procdff$22685 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$11_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.crc_I.out_crc4). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22683 ($dff) from module top (D = \misc_I.e1_cnt_I[0].sub_I.inc, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.crc_I.in_valid, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22682 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.data [6:0] \soc_I.e1_I.lb_bit [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.data). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22681 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:135$20_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.data_match_fas). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22679 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15137_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.bit_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23594 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:215$34_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.bit_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22678 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15142_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.bit_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23596 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$33_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.bit_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22677 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15147_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.bit, rval = 3'000). Adding EN signal on $auto$opt_dff.cc:702:run$23598 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32_Y [2:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.bit). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22676 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15122_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts_is_ts31, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23600 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:227$38_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts_is_ts31). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22675 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15127_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts_is_ts0, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23602 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts_is_ts31, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts_is_ts0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22674 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15132_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts, rval = 5'00001). Adding EN signal on $auto$opt_dff.cc:702:run$23604 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37_Y [4:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22673 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15097_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.frame_mf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23606 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:243$44_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.frame_mf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22672 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15102_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.frame_mf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23608 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.frame_mf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.frame_mf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22671 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15107_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.frame_smf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23610 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:241$43_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.frame_smf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22670 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15112_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.frame_smf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23612 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.frame_smf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.frame_smf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22669 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15117_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.frame, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$23614 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42_Y [3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.frame). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22668 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$xor$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:262$52_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.fas_pos, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22667 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15089_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.mfa_timeout, rval = 7'0111111). Adding EN signal on $auto$opt_dff.cc:702:run$23617 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$56_Y [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.mfa_timeout). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22666 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15074_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23619 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:285$62_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22665 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15079_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23621 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:284$61_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22664 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procmux$15084_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts0_msbs, rval = 16'1111111111111111). Adding EN signal on $auto$opt_dff.cc:702:run$23623 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts0_msbs [14:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.data [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts0_msbs). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22663 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.crc_I.out_crc4, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.crc_smf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22662 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:325$84_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ep_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22661 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:326$90_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ed_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22660 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:323$75_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ep_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22659 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$80_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ed_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22658 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:340$105_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ep_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22657 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:341$110_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ed_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22656 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:338$97_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ep_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22655 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$102_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ed_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22654 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$127_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ec_mfa, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22653 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$123_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ec_crc, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22652 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$119_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ec_nfas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22651 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$115_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ec_fas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22649 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$140_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.out_valid, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22648 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:396$142_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.out_last, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22647 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$141_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.out_first, rval = 1'1). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22645 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.ts, Q = \soc_I.e1_buf_I.buf_rx_ts [4:0], rval = 5'00000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22644 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.frame, Q = \soc_I.e1_buf_I.buf_rx_frame [3:0], rval = 4'0000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22643 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.data, Q = \soc_I.e1_buf_I.buf_rx_data [7:0], rval = 8'00000000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$procdff$22642 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$139_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.aligned, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$procdff$22385 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4127_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.data[1]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$procdff$22384 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4132_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$procdff$22383 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4138_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$procdff$22382 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4143_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$procdff$22381 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4149_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$procdff$22380 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4154_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$procdff$22379 ($adff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.data[5] [8:7] \soc_I.e1_buf_I.buf_rx_mf [6:0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$procdff$22378 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4165_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.stage[4].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$procdff$22377 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4173_Y, Q = \soc_I.e1_buf_I.buf_rx_mf [6:0]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$procdff$22376 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4178_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_in_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$procdff$22375 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4184_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_in_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$procdff$22374 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4189_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_in_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$procdff$22373 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4195_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_in_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$procdff$22372 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4200_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_in_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$procdff$22371 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_in_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$procdff$22370 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4211_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_in_I.stage[4].l_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$procdff$22243 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:114$5270_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.crx_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$procdff$22242 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:113$5267_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$procmux$5461_CMP, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$procdff$22241 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2:1], Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_mode [1] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.ctrl_mode_mf }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$procdff$22240 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bus_rd_rx_status [0]). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$procdff$22239 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:149$5283_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.rd_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$procdff$22238 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:148$5277_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_in_I.wr_ena, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22545 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata, Q = \soc_I.cpu_I.mem_rdata_q). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22540 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\mem_state[1:0], Q = \soc_I.cpu_I.mem_state). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22539 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14403_Y, Q = \soc_I.cpu_I.mem_wstrb). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22538 ($dff) from module top (D = \soc_I.cpu_I.mem_la_wdata, Q = \soc_I.cpu_I.mem_wdata). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22536 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\mem_valid[0:0], Q = \soc_I.cpu_I.mem_valid). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22535 ($dff) from module top (D = \soc_I.cpu_I.mem_la_addr, Q = \soc_I.cpu_I.mem_addr). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22519 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$reduce_or$/build/gateware/common/rtl/picorv32.v:846$3589_Y, Q = \soc_I.cpu_I.is_compare, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22518 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:860$3609_Y, Q = \soc_I.cpu_I.is_alu_reg_reg). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22517 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:859$3608_Y, Q = \soc_I.cpu_I.is_alu_reg_imm). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22515 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13784_Y, Q = \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23720 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:856$3605_Y, Q = \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22512 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$reduce_or$/build/gateware/common/rtl/picorv32.v:842$3585_Y, Q = \soc_I.cpu_I.is_lui_auipc_jal_jalr_addi_add_sub, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22511 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1091$3838_Y, Q = \soc_I.cpu_I.is_sll_srl_sra). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22510 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:858$3607_Y, Q = \soc_I.cpu_I.is_sb_sh_sw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22509 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1082$3827_Y, Q = \soc_I.cpu_I.is_jalr_addi_slti_sltiu_xori_ori_andi). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22508 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1076$3818_Y, Q = \soc_I.cpu_I.is_slli_srli_srai). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22507 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:857$3606_Y, Q = \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22505 ($dff) from module top (D = 1'0, Q = \soc_I.cpu_I.compressed_instr). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23728 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22504 ($dff) from module top (D = { \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [19:12] \soc_I.cpu_I.mem_rdata_latched [20] \soc_I.cpu_I.mem_rdata_latched [30:21] 1'0 }, Q = \soc_I.cpu_I.decoded_imm_uj). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23729 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22503 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830_Y, Q = \soc_I.cpu_I.decoded_imm). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22502 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [24:20], Q = \soc_I.cpu_I.decoded_rs2). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22501 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [19:15], Q = \soc_I.cpu_I.decoded_rs1). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22500 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [11:7], Q = \soc_I.cpu_I.decoded_rd). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22496 ($dff) from module top (D = 1'0, Q = \soc_I.cpu_I.instr_retirq). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23734 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22493 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1068$3785_Y, Q = \soc_I.cpu_I.instr_ecall_ebreak). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22488 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13940_Y, Q = \soc_I.cpu_I.instr_and, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23736 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1059$3754_Y, Q = \soc_I.cpu_I.instr_and). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22487 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13944_Y, Q = \soc_I.cpu_I.instr_or, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23738 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1058$3750_Y, Q = \soc_I.cpu_I.instr_or). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22486 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13948_Y, Q = \soc_I.cpu_I.instr_sra, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23740 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1057$3746_Y, Q = \soc_I.cpu_I.instr_sra). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22485 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13952_Y, Q = \soc_I.cpu_I.instr_srl, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23742 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1056$3742_Y, Q = \soc_I.cpu_I.instr_srl). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22484 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13956_Y, Q = \soc_I.cpu_I.instr_xor, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23744 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1055$3738_Y, Q = \soc_I.cpu_I.instr_xor). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22483 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13960_Y, Q = \soc_I.cpu_I.instr_sltu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23746 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1054$3734_Y, Q = \soc_I.cpu_I.instr_sltu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22482 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13964_Y, Q = \soc_I.cpu_I.instr_slt, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23748 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1053$3730_Y, Q = \soc_I.cpu_I.instr_slt). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22481 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13968_Y, Q = \soc_I.cpu_I.instr_sll, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23750 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1052$3726_Y, Q = \soc_I.cpu_I.instr_sll). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22480 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13972_Y, Q = \soc_I.cpu_I.instr_sub, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23752 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1051$3722_Y, Q = \soc_I.cpu_I.instr_sub). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22479 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13976_Y, Q = \soc_I.cpu_I.instr_add, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23754 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1050$3718_Y, Q = \soc_I.cpu_I.instr_add). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22478 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1048$3714_Y, Q = \soc_I.cpu_I.instr_srai). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22477 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1047$3710_Y, Q = \soc_I.cpu_I.instr_srli). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22476 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1046$3706_Y, Q = \soc_I.cpu_I.instr_slli). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22475 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13986_Y, Q = \soc_I.cpu_I.instr_andi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23759 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1044$3702_Y, Q = \soc_I.cpu_I.instr_andi). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22474 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13990_Y, Q = \soc_I.cpu_I.instr_ori, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23761 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1043$3700_Y, Q = \soc_I.cpu_I.instr_ori). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22473 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13994_Y, Q = \soc_I.cpu_I.instr_xori, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23763 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1042$3698_Y, Q = \soc_I.cpu_I.instr_xori). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22472 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13998_Y, Q = \soc_I.cpu_I.instr_sltiu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23765 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1041$3696_Y, Q = \soc_I.cpu_I.instr_sltiu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22471 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14002_Y, Q = \soc_I.cpu_I.instr_slti, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23767 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1040$3694_Y, Q = \soc_I.cpu_I.instr_slti). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22470 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14006_Y, Q = \soc_I.cpu_I.instr_addi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23769 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1039$3692_Y, Q = \soc_I.cpu_I.instr_addi). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22469 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1037$3690_Y, Q = \soc_I.cpu_I.instr_sw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22468 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1036$3688_Y, Q = \soc_I.cpu_I.instr_sh). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22467 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1035$3686_Y, Q = \soc_I.cpu_I.instr_sb). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22466 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1033$3684_Y, Q = \soc_I.cpu_I.instr_lhu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22465 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1032$3682_Y, Q = \soc_I.cpu_I.instr_lbu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22464 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1031$3680_Y, Q = \soc_I.cpu_I.instr_lw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22463 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1030$3678_Y, Q = \soc_I.cpu_I.instr_lh). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22462 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1029$3676_Y, Q = \soc_I.cpu_I.instr_lb). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22461 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14026_Y, Q = \soc_I.cpu_I.instr_bgeu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23779 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1027$3674_Y, Q = \soc_I.cpu_I.instr_bgeu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22460 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14030_Y, Q = \soc_I.cpu_I.instr_bltu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23781 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1026$3672_Y, Q = \soc_I.cpu_I.instr_bltu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22459 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14034_Y, Q = \soc_I.cpu_I.instr_bge, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23783 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1025$3670_Y, Q = \soc_I.cpu_I.instr_bge). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22458 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14038_Y, Q = \soc_I.cpu_I.instr_blt, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23785 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1024$3668_Y, Q = \soc_I.cpu_I.instr_blt). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22457 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14042_Y, Q = \soc_I.cpu_I.instr_bne, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23787 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1023$3666_Y, Q = \soc_I.cpu_I.instr_bne). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22456 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14046_Y, Q = \soc_I.cpu_I.instr_beq, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23789 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1022$3664_Y, Q = \soc_I.cpu_I.instr_beq). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22455 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:852$3596_Y, Q = \soc_I.cpu_I.instr_jalr). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22454 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:851$3593_Y, Q = \soc_I.cpu_I.instr_jal). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22453 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:850$3592_Y, Q = \soc_I.cpu_I.instr_auipc). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22452 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:849$3591_Y, Q = \soc_I.cpu_I.instr_lui). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22441 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12760_Y, Q = \soc_I.cpu_I.latched_rd, rval = 5'00010). Adding EN signal on $auto$opt_dff.cc:702:run$23795 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12760_Y, Q = \soc_I.cpu_I.latched_rd). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22440 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12786_Y, Q = \soc_I.cpu_I.latched_is_lb, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23803 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12786_Y, Q = \soc_I.cpu_I.latched_is_lb). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22439 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12799_Y, Q = \soc_I.cpu_I.latched_is_lh, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23813 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12799_Y, Q = \soc_I.cpu_I.latched_is_lh). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22438 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12812_Y, Q = \soc_I.cpu_I.latched_is_lu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23823 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12812_Y, Q = \soc_I.cpu_I.latched_is_lu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22436 ($dff) from module top (D = \soc_I.cpu_I.compressed_instr, Q = \soc_I.cpu_I.latched_compr). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22435 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12857_Y, Q = \soc_I.cpu_I.latched_branch, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23836 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12857_Y, Q = \soc_I.cpu_I.latched_branch). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22434 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12893_Y, Q = \soc_I.cpu_I.latched_stalu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23840 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12893_Y, Q = \soc_I.cpu_I.latched_stalu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22433 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12900_Y, Q = \soc_I.cpu_I.latched_store, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23848 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12900_Y, Q = \soc_I.cpu_I.latched_store). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22422 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12526_Y, Q = \soc_I.cpu_I.decoder_pseudo_trigger, rval = 1'0). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22419 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13164_Y, Q = \soc_I.cpu_I.mem_do_wdata, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23855 ($sdff) from module top (D = 1'0, Q = \soc_I.cpu_I.mem_do_wdata). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22418 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13168_Y, Q = \soc_I.cpu_I.mem_do_rdata, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23857 ($sdff) from module top (D = 1'0, Q = \soc_I.cpu_I.mem_do_rdata). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22417 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13239_Y, Q = \soc_I.cpu_I.mem_do_rinst, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$23859 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13239_Y, Q = \soc_I.cpu_I.mem_do_rinst). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22416 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13264_Y, Q = \soc_I.cpu_I.mem_do_prefetch, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23873 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1552$3967_Y, Q = \soc_I.cpu_I.mem_do_prefetch). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22409 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12659_Y, Q = \soc_I.cpu_I.reg_out, rval = 1024). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22408 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13366_Y, Q = \soc_I.cpu_I.reg_op2). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22407 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13389_Y [31], Q = \soc_I.cpu_I.reg_op1 [31]). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22407 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13389_Y [30:0], Q = \soc_I.cpu_I.reg_op1 [30:0]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22406 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12001_Y, Q = \soc_I.cpu_I.reg_next_pc [31:2], rval = 30'000000000000000000000000000000). Adding EN signal on $auto$opt_dff.cc:702:run$23917 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$11990_Y, Q = \soc_I.cpu_I.reg_next_pc [31:2]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22405 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13437_Y, Q = \soc_I.cpu_I.reg_pc [31:2], rval = 30'000000000000000000000000000000). Adding EN signal on $auto$opt_dff.cc:702:run$23919 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2], Q = \soc_I.cpu_I.reg_pc [31:2]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$22398 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12742_Y, Q = \soc_I.cpu_I.trap, rval = 1'0). Adding SRST signal on $flatten\soc_I.\bridge_I.$procdff$22367 ($dff) from module top (D = \soc_I.bridge_I.wb_rdata_or, Q = \soc_I.bridge_I.wb_rdata_reg, rval = 0). Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top (D = 8'xxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_DATA [31:24], rval = 8'00000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$23923 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$23923 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$23923 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$23923 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$23923 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$23923 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$23923 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$23923 ($sdff) from module top. Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top (D = 16'xxxxxxxxxxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_DATA [31:16], rval = 16'0000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$23924 ($sdff) from module top. Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$22576 ($dff) from module top (D = 24'xxxxxxxxxxxxxxxxxxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_DATA [31:8], rval = 24'000000000000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$23925 ($sdff) from module top. Adding SRST signal on $flatten\misc_I.\dfu_I.\btn_flt_I.$procdff$22225 ($dff) from module top (D = $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5396_Y, Q = \misc_I.dfu_I.btn_flt_I.state, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$23926 ($sdff) from module top (D = 1'1, Q = \misc_I.dfu_I.btn_flt_I.state). Adding EN signal on $flatten\misc_I.\dfu_I.$procdff$22393 ($adff) from module top (D = $flatten\misc_I.\dfu_I.$procmux$11971_Y, Q = \misc_I.dfu_I.wb_sel). Adding EN signal on $flatten\misc_I.\dfu_I.$procdff$22392 ($adff) from module top (D = $flatten\misc_I.\dfu_I.$procmux$11976_Y, Q = \misc_I.dfu_I.rst_req). Adding SRST signal on $flatten\misc_I.$procdff$22269 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/e1-tracer/rtl/misc.v:70$1591_Y, Q = \misc_I.bus_we_boot, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$22268 ($dff) from module top (D = $flatten\misc_I.$procmux$11410_Y, Q = \misc_I.wb_rdata, rval = 0). Adding EN signal on $flatten\misc_I.$procdff$22267 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2], Q = \misc_I.boot_now). Adding EN signal on $flatten\misc_I.$procdff$22266 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [1:0], Q = \misc_I.boot_sel). 73.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 430 unused cells and 506 unused wires. <suppressed ~433 debug messages> 73.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~19 debug messages> 73.12.9. Rerunning OPT passes. (Maybe there is more to do..) 73.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~164 debug messages> 73.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~69 debug messages> Removed a total of 23 cells. 73.12.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23835 ($dffe) from module top. 73.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 27 unused wires. <suppressed ~2 debug messages> 73.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1 debug messages> 73.12.16. Rerunning OPT passes. (Maybe there is more to do..) 73.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~163 debug messages> 73.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.12.20. Executing OPT_DFF pass (perform DFF optimizations). 73.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 1 unused wires. <suppressed ~1 debug messages> 73.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.12.23. Rerunning OPT passes. (Maybe there is more to do..) 73.12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~163 debug messages> 73.12.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.12.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.12.27. Executing OPT_DFF pass (perform DFF optimizations). 73.12.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.12.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.12.30. Finished OPT passes. (There is nothing left to do.) 73.13. Executing WREDUCE pass (reducing word size of cells). Removed top 24 address bits (of 32) from memory init port top.$flatten\soc_I.\bram_I.$meminit$\mem$/build/gateware/common/rtl/soc_bram.v:0$3344 (soc_I.bram_I.mem). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23340 ($eq). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23679 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23309 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22876 ($eq). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22872 ($eq). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22880 ($eq). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23704 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23700 ($ne). Removed top 3 bits (of 5) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23869 ($ne). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22905 ($eq). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22901 ($eq). Removed top 1 bits (of 6) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23052 ($eq). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23476 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22909 ($eq). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23480 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23478 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23240 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23244 ($eq). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$23355 ($ne). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22846 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23279 ($eq). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22806 ($eq). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22810 ($eq). Removed top 1 bits (of 6) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23039 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:233$4979 ($eq). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4997 ($shl). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4999 ($and). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$ne$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:253$5016 ($ne). Removed top 2 bits (of 4) from mux cell top.$flatten\soc_I.\e1_buf_I.$procmux$14724 ($mux). Removed cell top.$flatten\soc_I.\e1_buf_I.$procmux$14809 ($mux). Removed top 1 bits (of 2) from mux cell top.$flatten\soc_I.\e1_buf_I.$procmux$14855 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_I.$eq$/build/gateware/cores/no2e1//rtl/e1_wb.v:149$5035 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9 ($mux). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$11 ($xor). Removed top 1 bits (of 16) from FF cell top.$auto$opt_dff.cc:764:run$23624 ($sdffe). Removed top 1 bits (of 7) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23030 ($eq). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$127 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$123 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$119 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$115 ($add). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.\crc_I.$and$/build/gateware/cores/no2e1//rtl/e1_crc4.v:35$3 ($and). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:284$61 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$56 ($sub). Removed top 25 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$56 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32 ($add). Removed top 1 bits (of 2) from FF cell top.$auto$opt_dff.cc:764:run$23671 ($adffe). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:135$19 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9 ($mux). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$11 ($xor). Removed top 1 bits (of 16) from FF cell top.$auto$opt_dff.cc:764:run$23539 ($sdffe). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$127 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$123 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$119 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$115 ($add). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.\crc_I.$and$/build/gateware/cores/no2e1//rtl/e1_crc4.v:35$3 ($and). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:284$61 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$56 ($sub). Removed top 25 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$56 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32 ($add). Removed top 1 bits (of 2) from FF cell top.$auto$opt_dff.cc:764:run$23586 ($adffe). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:135$19 ($eq). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.$or$/build/gateware/common/rtl/soc_iobuf.v:250$2528 ($or). Removed top 1 bits (of 2) from FF cell top.$auto$opt_dff.cc:764:run$23490 ($dffe). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5386 ($mux). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5383 ($mux). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5379 ($mux). Removed top 20 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$4800 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4799 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4799 ($sub). Removed top 23 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$4791 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4789 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4789 ($add). Removed top 18 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$4787 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4785 ($add). Removed top 18 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4785 ($add). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5452_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5451_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5450_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5449_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5448_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5447_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5446_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5435_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5434_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5433_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5432_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5431_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5430_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5429_CMP0 ($eq). Removed cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11532 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11516_CMP0 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1509 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1507 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1507 ($add). Removed top 30 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1503 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1503 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1503 ($add). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4704 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1569 ($sub). Removed top 21 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1569 ($sub). Removed top 21 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1569 ($sub). Removed top 21 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1568 ($mux). Removed top 1 bits (of 8) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1552 ($mux). Removed top 28 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1546 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1546 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1546 ($sub). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22975 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:137$1533 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11910_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11909_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11908_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11895_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11884_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11883_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11882_CMP0 ($eq). Removed top 3 bits (of 4) from mux cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11875 ($mux). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11867_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11866_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11865_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:98$1288 ($eq). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4704 ($mux). Removed top 1 bits (of 16) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$eq$/build/gateware/cores/no2usb//rtl/usb_crc.v:44$4707 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4717 ($mux). Removed top 2 bits (of 5) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$xor$/build/gateware/cores/no2usb//rtl/usb_crc.v:38$4718 ($xor). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22971 ($eq). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22967 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:313$1362 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:311$1358 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:308$1352 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:307$1351 ($eq). Removed top 29 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1337 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1337 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1337 ($sub). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11597_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11574 ($mux). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11572_CMP0 ($eq). Removed cell top.$flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:375$1464 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:303$1446 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:207$1424 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:206$1423 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:205$1422 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:204$1421 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:203$1420 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:202$1419 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:201$1418 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1417 ($add). Removed top 24 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1417 ($add). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22814 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\uart_I.$eq$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3291 ($eq). Removed top 24 bits (of 32) from mux cell top.$flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3312 ($mux). Removed top 1 bits (of 5) from FF cell top.$auto$opt_dff.cc:764:run$23463 ($adffe). Removed top 1 bits (of 13) from mux cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5481 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5470 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5260 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5260 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5257 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5257 ($sub). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$11917 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$11919 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procdff$22353 ($dff). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4526 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4526 ($add). Removed top 1 bits (of 10) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4515 ($eq). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22825 ($eq). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5509 ($mux). Removed top 1 bits (of 2) from mux cell top.$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$5527 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5242 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5242 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5239 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5239 ($sub). Removed top 21 bits (of 32) from port A of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5238 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5238 ($sub). Removed top 20 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5238 ($sub). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$11917 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$11919 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procdff$22353 ($dff). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4526 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4526 ($add). Removed top 1 bits (of 10) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4515 ($eq). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14861 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14863 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14867 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14869 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14873 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14875 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14879 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$14881 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$22577 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$22580 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$22583 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$22586 ($dff). Removed top 24 bits (of 32) from port A of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5082 ($or). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5084 ($or). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5088 ($or). Removed top 24 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5090 ($or). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5094 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5095 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5096 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5097 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5098 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5099 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5100 ($eq). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\cpu_I.$shl$/build/gateware/common/rtl/picorv32.v:403$3513 ($shl). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:601$3572 ($mux). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:849$3591 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:850$3592 ($eq). Removed top 5 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:857$3606 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:858$3607 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:859$3608 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:860$3609 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1023$3665 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1031$3679 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1041$3695 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1048$3713 ($eq). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$3886 ($add). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$3963 ($add). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4014 ($ge). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4022 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4022 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4029 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4029 ($sub). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22941 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12388 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12391 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12655 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12657 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12662 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12712 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12732 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12755 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12782 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12784 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12795 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12797 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12808 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12810 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12888 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13176 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13237 ($mux). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$22920 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13385 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13387 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13393 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13395 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13410 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13531 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14373 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14377 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14383 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\cpu_I.$procmux$14385_CMP0 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14386 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14392 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14426 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14436 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14438 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14442 ($mux). Removed top 24 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$procmux$14669 ($pmux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\cpu_I.$procmux$14672_CMP0 ($eq). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$procmux$14678 ($pmux). Removed top 11 bits (of 31) from FF cell top.$auto$opt_dff.cc:764:run$23729 ($dffe). Removed top 25 bits (of 26) from port B of cell top.$flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4093 ($add). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11413_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11412_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11411_CMP0 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1598 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1598 ($add). Removed top 1 bits (of 2) from port A of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:233$4979 ($eq). Removed top 1 bits (of 2) from port A of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:241$4982 ($eq). Removed top 1 bits (of 2) from port A of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:241$4985 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4996 ($shl). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4997 ($shl). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5000 ($or). Removed top 2 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5000 ($or). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5000 ($or). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4997 ($shl). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4999 ($and). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4999 ($and). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4998 ($not). Removed top 2 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4998 ($not). Removed top 2 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4996 ($shl). Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_EN[31:0]$3325. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_DATA[31:0]$3327. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_DATA[31:0]$3330. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_EN[31:0]$3331. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3318_DATA. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_DATA. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3320_DATA. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$2\mem_rdata_word[31:0]. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$3\mem_rdata_word[31:0]. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4022_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4029_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$115_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$119_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$123_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$127_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9_Y. Removed top 3 bits (of 16) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bus_rd_rx_status. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$115_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$119_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$123_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$127_Y. Removed top 25 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$56_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9_Y. Removed top 3 bits (of 16) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bus_rd_rx_status. Removed top 2 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4999_Y. Removed top 2 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4998_Y. Removed top 2 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4996_Y. Removed top 2 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$4997_Y. Removed top 18 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4785_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4789_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4799_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$4791_Y. Removed top 20 bits (of 32) from wire top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$4800_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5238_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5239_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5242_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528_Y. Removed top 1 bits (of 13) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$0\div_cnt[12:0]. Removed top 1 bits (of 10) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5470_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5257_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5260_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4526_Y. Removed top 3 bits (of 4) from wire top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11875_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1337_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4717_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11574_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1507_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1509_Y. Removed top 28 bits (of 32) from wire top.$flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1598_Y. Removed top 9 bits (of 32) from wire top.wb_rdata[0]. Removed top 24 bits (of 32) from wire top.wb_rdata[1]. Removed top 24 bits (of 64) from wire top.wb_rdata_flat. 73.14. Executing PEEPOPT pass (run peephole optimizers). 73.15. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 121 unused wires. <suppressed ~1 debug messages> 73.16. Executing SHARE pass (SAT-based resource sharing). 73.17. Executing TECHMAP pass (map to technology primitives). 73.17.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 73.17.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~88 debug messages> 73.18. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 73.19. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 4 unused wires. <suppressed ~1 debug messages> 73.20. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4093 ($add). creating $macc model for $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4730 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1219$4078 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$3886 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$3963 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$3964 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4008 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4033 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1219$4077 ($sub). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4022 ($sub). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4029 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$115 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$119 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$123 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$127 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$56 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$115 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$119 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$123 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$127 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$56 ($sub). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4785 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4789 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4799 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5238 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5239 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5242 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4497 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4511 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4526 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5257 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5260 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4511 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4526 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3267 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3248 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3252 ($add). creating $macc model for $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1337 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1417 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1478 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1487 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1434 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1484 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1503 ($add). creating $macc model for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1507 ($add). creating $macc model for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1546 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1569 ($sub). creating $macc model for $flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1598 ($add). creating $alu model for $macc $flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1598. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1569. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1546. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1507. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1503. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1484. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1434. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1487. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1478. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1417. creating $alu model for $macc $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1337. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3252. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3248. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3267. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4526. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4511. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5260. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5257. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4526. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4511. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4497. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5242. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5239. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5238. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4799. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4789. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4785. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$56. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$127. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$123. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$119. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$115. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$56. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$127. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$123. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$119. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$115. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4029. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4022. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1219$4077. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4033. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4008. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$3964. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$3963. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$3886. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1219$4078. creating $alu model for $macc $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4730. creating $alu model for $macc $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4093. creating $alu model for $flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4014 ($ge): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1221$4081 ($lt): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1222$4082 ($lt): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1220$4080 ($eq): merged with $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1222$4082. creating $alu cell for $flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4014: $auto$alumacc.cc:485:replace_alu$23996 creating $alu cell for $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4093: $auto$alumacc.cc:485:replace_alu$24005 creating $alu cell for $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4730: $auto$alumacc.cc:485:replace_alu$24008 creating $alu cell for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1222$4082, $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1220$4080: $auto$alumacc.cc:485:replace_alu$24011 creating $alu cell for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1221$4081: $auto$alumacc.cc:485:replace_alu$24022 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1219$4078: $auto$alumacc.cc:485:replace_alu$24035 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$3886: $auto$alumacc.cc:485:replace_alu$24038 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$3963: $auto$alumacc.cc:485:replace_alu$24041 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$3964: $auto$alumacc.cc:485:replace_alu$24044 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4008: $auto$alumacc.cc:485:replace_alu$24047 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4033: $auto$alumacc.cc:485:replace_alu$24050 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1219$4077: $auto$alumacc.cc:485:replace_alu$24053 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4022: $auto$alumacc.cc:485:replace_alu$24056 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4029: $auto$alumacc.cc:485:replace_alu$24059 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32: $auto$alumacc.cc:485:replace_alu$24062 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37: $auto$alumacc.cc:485:replace_alu$24065 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42: $auto$alumacc.cc:485:replace_alu$24068 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$115: $auto$alumacc.cc:485:replace_alu$24071 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$119: $auto$alumacc.cc:485:replace_alu$24074 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$123: $auto$alumacc.cc:485:replace_alu$24077 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$127: $auto$alumacc.cc:485:replace_alu$24080 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$56: $auto$alumacc.cc:485:replace_alu$24083 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$32: $auto$alumacc.cc:485:replace_alu$24086 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$37: $auto$alumacc.cc:485:replace_alu$24089 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$42: $auto$alumacc.cc:485:replace_alu$24092 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$115: $auto$alumacc.cc:485:replace_alu$24095 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$119: $auto$alumacc.cc:485:replace_alu$24098 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$123: $auto$alumacc.cc:485:replace_alu$24101 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$127: $auto$alumacc.cc:485:replace_alu$24104 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$56: $auto$alumacc.cc:485:replace_alu$24107 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$4785: $auto$alumacc.cc:485:replace_alu$24110 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$4789: $auto$alumacc.cc:485:replace_alu$24113 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$4799: $auto$alumacc.cc:485:replace_alu$24116 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5238: $auto$alumacc.cc:485:replace_alu$24119 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5239: $auto$alumacc.cc:485:replace_alu$24122 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5242: $auto$alumacc.cc:485:replace_alu$24125 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4497: $auto$alumacc.cc:485:replace_alu$24128 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528: $auto$alumacc.cc:485:replace_alu$24131 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4511: $auto$alumacc.cc:485:replace_alu$24134 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4526: $auto$alumacc.cc:485:replace_alu$24137 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5257: $auto$alumacc.cc:485:replace_alu$24140 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5260: $auto$alumacc.cc:485:replace_alu$24143 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4528: $auto$alumacc.cc:485:replace_alu$24146 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4511: $auto$alumacc.cc:485:replace_alu$24149 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4526: $auto$alumacc.cc:485:replace_alu$24152 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3267: $auto$alumacc.cc:485:replace_alu$24155 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3248: $auto$alumacc.cc:485:replace_alu$24158 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3252: $auto$alumacc.cc:485:replace_alu$24161 creating $alu cell for $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1337: $auto$alumacc.cc:485:replace_alu$24164 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1417: $auto$alumacc.cc:485:replace_alu$24167 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1478: $auto$alumacc.cc:485:replace_alu$24170 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1487: $auto$alumacc.cc:485:replace_alu$24173 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1434: $auto$alumacc.cc:485:replace_alu$24176 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1484: $auto$alumacc.cc:485:replace_alu$24179 creating $alu cell for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1503: $auto$alumacc.cc:485:replace_alu$24182 creating $alu cell for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1507: $auto$alumacc.cc:485:replace_alu$24185 creating $alu cell for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1546: $auto$alumacc.cc:485:replace_alu$24188 creating $alu cell for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1569: $auto$alumacc.cc:485:replace_alu$24191 creating $alu cell for $flatten\sys_mgr_I.$add$/build/gateware/e1-tracer/rtl/sysmgr.v:85$1598: $auto$alumacc.cc:485:replace_alu$24194 created 59 $alu and 0 $macc cells. 73.21. Executing OPT pass (performing simple optimizations). 73.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2 debug messages> 73.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~12 debug messages> Removed a total of 4 cells. 73.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~151 debug messages> 73.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13389: { \soc_I.cpu_I.cpu_state [2] \soc_I.cpu_I.cpu_state [4] $auto$opt_reduce.cc:134:opt_mux$24198 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14375: { $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:364$3481_Y $flatten\soc_I.\cpu_I.$procmux$14385_CMP $auto$opt_reduce.cc:134:opt_mux$24200 } Optimizing cells in module \top. Performed a total of 2 changes. 73.21.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 73.21.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$22585 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$22582 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$22579 ($dff) from module top. Adding SRST signal on $auto$opt_dff.cc:764:run$23707 ($dffe) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14428_Y, Q = \soc_I.cpu_I.mem_valid, rval = 1'0). Adding SRST signal on $auto$opt_dff.cc:764:run$23690 ($dffe) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14375_Y, Q = \soc_I.cpu_I.mem_state, rval = 2'00). Removing never-active SRST on $auto$opt_dff.cc:702:run$23499 ($sdffce) from module top. Removing never-active SRST on $auto$opt_dff.cc:702:run$23495 ($sdffce) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$23456 ($sdff) from module top. 73.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 13 unused wires. <suppressed ~3 debug messages> 73.21.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.21.9. Rerunning OPT passes. (Maybe there is more to do..) 73.21.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~151 debug messages> 73.21.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.21.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.21.13. Executing OPT_DFF pass (perform DFF optimizations). 73.21.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.21.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.21.16. Finished OPT passes. (There is nothing left to do.) 73.22. Executing MEMORY pass. 73.22.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 73.22.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3345' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3346' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3347' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3348' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5118' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5118' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memrd$\mem$/build/gateware/common/rtl/soc_bram.v:32$3335' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5117' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5117' in module `\top': merged data $dff to cell. 73.22.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 18 unused cells and 21 unused wires. <suppressed ~19 debug messages> 73.22.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating write ports of memory top.soc_I.bram_I.mem by address: New clock domain: posedge \misc_I.clk Port 0 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3345) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000000000000000000011111111 Port 1 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3346) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000000000001111111100000000 Merging port 0 into this one. Active bits: 00000000000000001111111111111111 Port 2 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3347) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000111111110000000000000000 Merging port 1 into this one. Active bits: 00000000111111111111111111111111 Port 3 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3348) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 11111111000000000000000000000000 Merging port 2 into this one. Active bits: 11111111111111111111111111111111 73.22.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.22.6. Executing MEMORY_COLLECT pass (generating $mem cells). Collecting $memrd, $memwr and $meminit for memory `\soc_I.bram_I.mem' in module `\top': $flatten\soc_I.\bram_I.$meminit$\mem$/build/gateware/common/rtl/soc_bram.v:0$3344 ($meminit) $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3348 ($memwr) $flatten\soc_I.\bram_I.$memrd$\mem$/build/gateware/common/rtl/soc_bram.v:32$3335 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.uart_I.uart_rx_fifo_I.ram_I.ram' in module `\top': $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5118 ($memwr) $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5117 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.uart_I.uart_tx_fifo_I.ram_I.ram' in module `\top': $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5118 ($memwr) $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5117 ($memrd) 73.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). Processing top.soc_I.bram_I.mem: Properties: ports=2 bits=8192 rports=1 wports=1 dbits=32 abits=8 words=256 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3584 efficiency=12 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=12, cells=16, acells=1 Efficiency for rule 4.2: efficiency=25, cells=8, acells=1 Efficiency for rule 4.1: efficiency=50, cells=4, acells=1 Efficiency for rule 1.1: efficiency=100, cells=2, acells=1 Selected rule 1.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M0 cell at grid position <0 0 0>: soc_I.bram_I.mem.0.0.0 Creating $__ICE40_RAM4K_M0 cell at grid position <1 0 0>: soc_I.bram_I.mem.1.0.0 Processing top.soc_I.uart_I.uart_rx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: soc_I.uart_I.uart_rx_fifo_I.ram_I.ram.0.0.0 Processing top.soc_I.uart_I.uart_tx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \misc_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \misc_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: soc_I.uart_I.uart_tx_fifo_I.ram_I.ram.0.0.0 73.25. Executing TECHMAP pass (map to technology primitives). 73.25.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. Successfully finished Verilog frontend. 73.25.2. Continuing TECHMAP pass. Using template $paramod\$__ICE40_RAM4K_M123\CFG_ABITS=9\CFG_DBITS=8\CLKPOL2=1\CLKPOL3=1 for cells of type $__ICE40_RAM4K_M123. Using template $paramod$b9e8582c288289ac723b215129f56c6fb55d152a\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. Using template $paramod$4db28c01ad2f8fb3d28d8b45acd344e29c76a5e2\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. Using template $paramod$66c3fa288a62dc560ce3ddd26d81551ab195105f\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. Using template $paramod$604ec1e346c2dd44ad2f04f633da753d2abbf02c\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. Using template $paramod$7577afd8fd444532bbc3532c110d9d682708035f\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. No more expansions possible. <suppressed ~207 debug messages> 73.26. Executing ICE40_BRAMINIT pass. Processing soc_I.usb_I.trans_I.mc_rom_I : usb_trans_mc.hex 73.27. Executing OPT pass (performing simple optimizations). 73.27.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~232 debug messages> 73.27.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.27.3. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$22410 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\reg_sh[4:0] [1:0], Q = \soc_I.cpu_I.reg_sh [1:0]). 73.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 38 unused cells and 196 unused wires. <suppressed ~50 debug messages> 73.27.5. Rerunning OPT passes. (Removed registers in this run.) 73.27.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.27.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.27.8. Executing OPT_DFF pass (perform DFF optimizations). 73.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.27.10. Finished fast OPT passes. 73.28. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 73.29. Executing OPT pass (performing simple optimizations). 73.29.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$14818. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$14833. Removed 2 multiplexer ports. <suppressed ~137 debug messages> 73.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $techmap$techmap24224\soc_I.bram_I.mem.0.0.0.$reduce_or$/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v:222$24223: { $auto$wreduce.cc:454:run$23934 [7] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3319_EN[31:0]$3328 [15] } New input vector for $reduce_or cell $techmap$techmap24221\soc_I.bram_I.mem.1.0.0.$reduce_or$/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v:222$24220: { $auto$wreduce.cc:454:run$23937 [23] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3321_EN[31:0]$3334 [31] } Consolidated identical input bits for $mux cell $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5408: Old ports: A=4'0000, B=4'1111, Y=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] New ports: A=1'0, B=1'1, Y=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] New connections: $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [3:1] = { $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] } Consolidated identical input bits for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12651: Old ports: A=\soc_I.cpu_I.mem_rdata_word, B={ \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15:0] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7:0] }, Y=$flatten\soc_I.\cpu_I.$procmux$12651_Y New ports: A=\soc_I.cpu_I.mem_rdata_word [31:8], B={ \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15:7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] }, Y=$flatten\soc_I.\cpu_I.$procmux$12651_Y [31:8] New connections: $flatten\soc_I.\cpu_I.$procmux$12651_Y [7:0] = \soc_I.cpu_I.mem_rdata_word [7:0] Consolidated identical input bits for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14694: Old ports: A=\soc_I.cpu_I.reg_op2, B={ \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] }, Y=\soc_I.cpu_I.mem_la_wdata New ports: A=\soc_I.cpu_I.reg_op2 [31:8], B={ \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] }, Y=\soc_I.cpu_I.mem_la_wdata [31:8] New connections: \soc_I.cpu_I.mem_la_wdata [7:0] = \soc_I.cpu_I.reg_op2 [7:0] Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1192$3854: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B={ \soc_I.cpu_I.reg_out [31:1] 1'0 }, Y=\soc_I.cpu_I.next_pc New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=\soc_I.cpu_I.reg_out [31:1], Y=\soc_I.cpu_I.next_pc [31:1] New connections: \soc_I.cpu_I.next_pc [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3923: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B={ $auto$opt_expr.cc:205:group_cell_inputs$24289 1'0 }, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3923_Y New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=$auto$opt_expr.cc:205:group_cell_inputs$24289, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3923_Y [31:1] New connections: $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3923_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$3976: Old ports: A={ \soc_I.cpu_I.reg_pc [31:2] 2'00 }, B=0, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$3976_Y New ports: A=\soc_I.cpu_I.reg_pc [31:2], B=30'000000000000000000000000000000, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$3976_Y [31:2] New connections: $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$3976_Y [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:366$3497: Old ports: A={ \soc_I.cpu_I.reg_op1 [31:2] 2'00 }, B={ \soc_I.cpu_I.next_pc [31:2] 2'00 }, Y=\soc_I.cpu_I.mem_la_addr New ports: A=\soc_I.cpu_I.reg_op1 [31:2], B=\soc_I.cpu_I.next_pc [31:2], Y=\soc_I.cpu_I.mem_la_addr [31:2] New connections: \soc_I.cpu_I.mem_la_addr [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3512: Old ports: A=4'0011, B=4'1100, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3512_Y New ports: A=2'01, B=2'10, Y={ $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3512_Y [2] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3512_Y [0] } New connections: { $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3512_Y [3] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3512_Y [1] } = { $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3512_Y [2] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3512_Y [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:601$3572: Old ports: A=2'11, B=2'00, Y=$flatten\soc_I.\cpu_I.$procmux$14381_Y New ports: A=1'1, B=1'0, Y=$flatten\soc_I.\cpu_I.$procmux$14381_Y [0] New connections: $flatten\soc_I.\cpu_I.$procmux$14381_Y [1] = $flatten\soc_I.\cpu_I.$procmux$14381_Y [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285: Old ports: A={ 3'000 $auto$wreduce.cc:454:run$23953 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_in_I.rd_empty 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$23953 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.data[1] [8:7] 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y New ports: A={ 3'000 $auto$wreduce.cc:454:run$23953 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_in_I.rd_empty 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$23953 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.data[1] [8:7] 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y [6:0] } New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1] = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285: Old ports: A={ 3'000 $auto$wreduce.cc:454:run$23963 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_in_I.rd_empty 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$23963 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.data[1] [8:7] 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y New ports: A={ 3'000 $auto$wreduce.cc:454:run$23963 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_in_I.rd_empty 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$23963 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.data[1] [8:7] 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y [6:0] } New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$9: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1] = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:115$4767: Old ports: A=2'10, B=2'00, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5379_Y New ports: A=1'1, B=1'0, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5379_Y [1] New connections: $flatten\soc_I.\iobuf_I.\dma_I.$procmux$5379_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:205$4817: Old ports: A=16'0000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir 1'0 \soc_I.iobuf_I.dma_I.len }, Y=\soc_I.iobuf_I.wb_rdata_dma [15:0] New ports: A=15'000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir \soc_I.iobuf_I.dma_I.len }, Y={ \soc_I.iobuf_I.wb_rdata_dma [15:14] \soc_I.iobuf_I.wb_rdata_dma [12:0] } New connections: \soc_I.iobuf_I.wb_rdata_dma [13] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4885: Old ports: A=0, B={ \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte }, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4885_Y New ports: A=8'00000000, B=\soc_I.e1_buf_I.wb_wdata_byte, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4885_Y [7:0] New connections: $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4885_Y [31:8] = { $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4885_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4885_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$4885_Y [7:0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_tx_I.$procmux$5473: Old ports: A={ 1'1 \soc_I.uart_I.uart_tx_I.shift [9:1] }, B={ 1'1 \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] New ports: A=\soc_I.uart_I.uart_tx_I.shift [9:1], B={ \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [8:0] New connections: $flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [9] = 1'1 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4704: Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] New connections: \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4717: Old ports: A=3'000, B=3'101, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:0] New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0] New connections: \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:1] = { \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11574: Old ports: A=3'000, B=3'110, Y=$auto$wreduce.cc:454:run$23986 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:454:run$23986 [1] New connections: { $auto$wreduce.cc:454:run$23986 [2] $auto$wreduce.cc:454:run$23986 [0] } = { $auto$wreduce.cc:454:run$23986 [1] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11577: Old ports: A={ 1'0 $auto$wreduce.cc:454:run$23986 [2:0] }, B=4'0100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11577_Y New ports: A=$auto$wreduce.cc:454:run$23986 [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11577_Y [2:0] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11577_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:340$1448: Old ports: A={ 8'00000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup 2'00 \soc_I.usb_I.trans_I.xfer_length }, Y=\soc_I.usb_I.ep_status_I.p_din_0 New ports: A={ 6'000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup \soc_I.usb_I.trans_I.xfer_length }, Y={ \soc_I.usb_I.ep_status_I.p_din_0 [15:12] \soc_I.usb_I.ep_status_I.p_din_0 [9:0] } New connections: \soc_I.usb_I.ep_status_I.p_din_0 [11:10] = 2'00 Consolidated identical input bits for $pmux cell $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11525: Old ports: A=3'000, B=6'110111, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11525_Y New ports: A=2'00, B=4'1011, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11525_Y [1:0] New connections: $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11525_Y [2] = $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11525_Y [1] Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4704: Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] New connections: \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5414: Old ports: A=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0], B=4'0001, Y=\misc_I.dfu_I.btn_flt_I.cnt_move New ports: A={ $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] }, B=2'01, Y=\misc_I.dfu_I.btn_flt_I.cnt_move [1:0] New connections: \misc_I.dfu_I.btn_flt_I.cnt_move [3:2] = { \misc_I.dfu_I.btn_flt_I.cnt_move [1] \misc_I.dfu_I.btn_flt_I.cnt_move [1] } Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$procmux$12385: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3923_Y, Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$24042 [1:0] } New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$3923_Y [31:1], Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$24042 [1] } New connections: $auto$alumacc.cc:501:replace_alu$24042 [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5286: Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y, Y=\soc_I.e1_I.bus_rdata_rx[0] New ports: A=15'000000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5021[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_rx[0] [15:8] \soc_I.e1_I.bus_rdata_rx[0] [6:0] } New connections: \soc_I.e1_I.bus_rdata_rx[0] [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5286: Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y, Y=\soc_I.e1_I.bus_rdata_rx[1] New ports: A=15'000000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5022[1].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$5285_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_rx[1] [15:8] \soc_I.e1_I.bus_rdata_rx[1] [6:0] } New connections: \soc_I.e1_I.bus_rdata_rx[1] [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11577: Old ports: A=$auto$wreduce.cc:454:run$23986 [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11577_Y [2:0] New ports: A={ $auto$wreduce.cc:454:run$23986 [1] $auto$wreduce.cc:454:run$23986 [1] }, B=2'10, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11577_Y [2:1] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11577_Y [0] = 1'0 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11580: Old ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11577_Y, B=4'1000, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11580_Y New ports: A={ 1'0 $flatten\soc_I.\usb_I.\trans_I.$procmux$11577_Y [2:1] }, B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11580_Y [3:1] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11580_Y [0] = 1'0 Optimizing cells in module \top. Performed a total of 32 changes. 73.29.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$22361 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:10], Q = \soc_I.usb_I.ep_status_I.din_1 [11:10], rval = 2'00). 73.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 2 unused wires. <suppressed ~1 debug messages> 73.29.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~28 debug messages> 73.29.9. Rerunning OPT passes. (Maybe there is more to do..) 73.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~138 debug messages> 73.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.29.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$23712 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$23712 ($dffe) from module top. Setting constant 1-bit at position 9 on $auto$opt_dff.cc:764:run$23438 ($adffe) from module top. 73.29.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 10 unused wires. <suppressed ~1 debug messages> 73.29.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.16. Rerunning OPT passes. (Maybe there is more to do..) 73.29.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~138 debug messages> 73.29.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.29.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$23504 ($sdff) from module top. 73.29.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.29.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 73.29.23. Rerunning OPT passes. (Maybe there is more to do..) 73.29.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~138 debug messages> 73.29.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.29.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.27. Executing OPT_DFF pass (perform DFF optimizations). 73.29.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 2 unused wires. <suppressed ~1 debug messages> 73.29.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.30. Rerunning OPT passes. (Maybe there is more to do..) 73.29.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~138 debug messages> 73.29.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 73.29.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.29.34. Executing OPT_DFF pass (perform DFF optimizations). 73.29.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.29.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.29.37. Finished OPT passes. (There is nothing left to do.) 73.30. Executing ICE40_WRAPCARRY pass (wrap carries). 73.31. Executing TECHMAP pass (map to technology primitives). 73.31.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 73.31.2. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 73.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $xor. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $adffe. Using extmapper simplemap for cells of type $adff. Using extmapper simplemap for cells of type $mux. Using template $paramod$constmap:a4d8bd4c83ae7aadb9a39a6a6c198c7f62a08526$paramod$39430ff77e1846062046cba1eb3ce5685e03f0fe\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=1\Y_WIDTH=7 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu. Using extmapper simplemap for cells of type $logic_or. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=14\Y_WIDTH=14 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=12 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=1\Y_WIDTH=13 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu. Using extmapper simplemap for cells of type $reduce_xor. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=20\Y_WIDTH=20 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=16\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=4 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=11 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=6 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=8 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=6 for cells of type $pmux. Using extmapper simplemap for cells of type $reduce_xnor. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=1\Y_WIDTH=9 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=1\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using template $paramod$constmap:66d421c313e4e958be776b99540ac2de3b59fdbc$paramod$9b74a473ccd678a23e1df4cc12019cbbece20051\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=31\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=30\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=26\Y_WIDTH=26 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=4 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu. No more expansions possible. <suppressed ~4122 debug messages> 73.32. Executing OPT pass (performing simple optimizations). 73.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2751 debug messages> 73.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3519 debug messages> Removed a total of 1173 cells. 73.32.3. Executing OPT_DFF pass (perform DFF optimizations). 73.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 621 unused cells and 3857 unused wires. <suppressed ~633 debug messages> 73.32.5. Finished fast OPT passes. 73.33. Executing ICE40_OPT pass (performing simple optimizations). 73.33.1. Running ICE40 specific optimizations. Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$23996.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$23996.BB [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24038.slice[0].carry: CO=\soc_I.cpu_I.reg_pc [2] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24041.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24041.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24056.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [2] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24059.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24062.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24062.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24065.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24065.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24068.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24068.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24083.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24083.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24086.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24086.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24089.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24089.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24092.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24092.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24107.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24107.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24110.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m0_addr_i [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24113.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m1_addr_i [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24116.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.len [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24119.slice[0].carry: CO=\soc_I.uart_I.uart_div [1] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24119.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$24119.C [11] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24122.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24125.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24131.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24137.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24140.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24143.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24146.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24152.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24164.slice[0].carry: CO=\soc_I.usb_I.rx_pkt_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24164.slice[3].carry: CO=$auto$alumacc.cc:485:replace_alu$24164.C [3] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24167.slice[0].carry: CO=\soc_I.usb_I.trans_I.mc_pc [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24182.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24182.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24182.slice[2].carry: CO=1'0 Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24185.slice[0].carry: CO=\soc_I.usb_I.tx_ll_I.bs_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24188.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24188.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24191.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24191.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24194.slice[0].carry: CO=\sys_mgr_I.rst_cnt [0] 73.33.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~38 debug messages> 73.33.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.33.4. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29577 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11860.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29576 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11860.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29575 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11860.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29573 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11877.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29572 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11877.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$29571 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11877.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34006 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [31], Q = \misc_I.wb_rdata [31], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34005 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [30], Q = \misc_I.wb_rdata [30], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34004 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [29], Q = \misc_I.wb_rdata [29], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34003 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [28], Q = \misc_I.wb_rdata [28], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34002 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [27], Q = \misc_I.wb_rdata [27], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34001 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [26], Q = \misc_I.wb_rdata [26], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$34000 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [25], Q = \misc_I.wb_rdata [25], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33999 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [24], Q = \misc_I.wb_rdata [24], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33998 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [23], Q = \misc_I.wb_rdata [23], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33997 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [22], Q = \misc_I.wb_rdata [22], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33996 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [21], Q = \misc_I.wb_rdata [21], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33995 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [20], Q = \misc_I.wb_rdata [20], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33994 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [19], Q = \misc_I.wb_rdata [19], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33993 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [18], Q = \misc_I.wb_rdata [18], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33992 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [17], Q = \misc_I.wb_rdata [17], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$33991 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11410.B_AND_S [16], Q = \misc_I.wb_rdata [16], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$30170 ($_SDFF_PP0_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11903.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.samp_cnt [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33803 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [31], Q = \soc_I.cpu_I.decoded_imm [31], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33802 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [30], Q = \soc_I.cpu_I.decoded_imm [30], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33801 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [29], Q = \soc_I.cpu_I.decoded_imm [29], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33800 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [28], Q = \soc_I.cpu_I.decoded_imm [28], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33799 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [27], Q = \soc_I.cpu_I.decoded_imm [27], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33798 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [26], Q = \soc_I.cpu_I.decoded_imm [26], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33797 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [25], Q = \soc_I.cpu_I.decoded_imm [25], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33796 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [24], Q = \soc_I.cpu_I.decoded_imm [24], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33795 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [23], Q = \soc_I.cpu_I.decoded_imm [23], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33794 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [22], Q = \soc_I.cpu_I.decoded_imm [22], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33793 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [21], Q = \soc_I.cpu_I.decoded_imm [21], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33792 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [20], Q = \soc_I.cpu_I.decoded_imm [20], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33791 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [19], Q = \soc_I.cpu_I.decoded_imm [19], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33790 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [18], Q = \soc_I.cpu_I.decoded_imm [18], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33789 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [17], Q = \soc_I.cpu_I.decoded_imm [17], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33788 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [16], Q = \soc_I.cpu_I.decoded_imm [16], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33787 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [15], Q = \soc_I.cpu_I.decoded_imm [15], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33786 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [14], Q = \soc_I.cpu_I.decoded_imm [14], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33785 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [13], Q = \soc_I.cpu_I.decoded_imm [13], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33784 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [12], Q = \soc_I.cpu_I.decoded_imm [12], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33783 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [11], Q = \soc_I.cpu_I.decoded_imm [11], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33782 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [10], Q = \soc_I.cpu_I.decoded_imm [10], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33781 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [9], Q = \soc_I.cpu_I.decoded_imm [9], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33780 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [8], Q = \soc_I.cpu_I.decoded_imm [8], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33779 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [7], Q = \soc_I.cpu_I.decoded_imm [7], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33778 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [6], Q = \soc_I.cpu_I.decoded_imm [6], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33777 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [5], Q = \soc_I.cpu_I.decoded_imm [5], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33776 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [4], Q = \soc_I.cpu_I.decoded_imm [4], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33775 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [3], Q = \soc_I.cpu_I.decoded_imm [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33774 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [2], Q = \soc_I.cpu_I.decoded_imm [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$33773 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13830.Y_B [1], Q = \soc_I.cpu_I.decoded_imm [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$29567 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11892.B_AND_S [2], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$29566 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11892.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$29565 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$11892.Y_B [0], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [0], rval = 1'0). 73.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 58 unused cells and 27 unused wires. <suppressed ~59 debug messages> 73.33.6. Rerunning OPT passes. (Removed registers in this run.) 73.33.7. Running ICE40 specific optimizations. 73.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.33.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~108 debug messages> Removed a total of 36 cells. 73.33.10. Executing OPT_DFF pass (perform DFF optimizations). 73.33.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 36 unused wires. <suppressed ~1 debug messages> 73.33.12. Rerunning OPT passes. (Removed registers in this run.) 73.33.13. Running ICE40 specific optimizations. 73.33.14. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.33.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.33.16. Executing OPT_DFF pass (perform DFF optimizations). 73.33.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.33.18. Finished OPT passes. (There is nothing left to do.) 73.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 73.35. Executing TECHMAP pass (map to technology primitives). 73.35.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 73.35.2. Continuing TECHMAP pass. Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_. Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_. Using template \$_DFF_P_ for cells of type $_DFF_P_. Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_. Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_. Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_. No more expansions possible. <suppressed ~1813 debug messages> 73.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping top.$auto$alumacc.cc:485:replace_alu$24038.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24041.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24056.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24059.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24062.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24065.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24068.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24083.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24086.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24089.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24092.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24107.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24110.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24113.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24116.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24119.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24119.slice[11].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24122.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24125.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24131.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24137.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24140.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24143.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24146.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24152.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24164.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24164.slice[3].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24167.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24182.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24182.slice[2].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24185.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24188.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24191.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24194.slice[0].carry ($lut). 73.38. Executing ICE40_OPT pass (performing simple optimizations). 73.38.1. Running ICE40 specific optimizations. 73.38.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1026 debug messages> 73.38.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~1320 debug messages> Removed a total of 440 cells. 73.38.4. Executing OPT_DFF pass (perform DFF optimizations). 73.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 9866 unused wires. <suppressed ~1 debug messages> 73.38.6. Rerunning OPT passes. (Removed registers in this run.) 73.38.7. Running ICE40 specific optimizations. 73.38.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 73.38.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 73.38.10. Executing OPT_DFF pass (perform DFF optimizations). 73.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 73.38.12. Finished OPT passes. (There is nothing left to do.) 73.39. Executing TECHMAP pass (map to technology primitives). 73.39.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 73.39.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 73.40. Executing ABC pass (technology mapping using ABC). 73.40.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'.. Extracted 5849 gates and 7965 wires to a netlist network with 2114 inputs and 1578 outputs. 73.40.1.1. Executing ABC. Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_blif <abc-temp-dir>/input.blif ABC: + read_lut <abc-temp-dir>/lutdefs.txt ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + lutpack -S 1 ABC: + dress ABC: Total number of equiv classes = 1946. ABC: Participating nodes from both networks = 4090. ABC: Participating nodes from the first network = 1956. ( 77.28 % of nodes) ABC: Participating nodes from the second network = 2134. ( 84.31 % of nodes) ABC: Node pairs (any polarity) = 1956. ( 77.28 % of names can be moved) ABC: Node pairs (same polarity) = 1702. ( 67.25 % of names can be moved) ABC: Total runtime = 0.07 sec ABC: + write_blif <abc-temp-dir>/output.blif 73.40.1.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 2530 ABC RESULTS: internal signals: 4273 ABC RESULTS: input signals: 2114 ABC RESULTS: output signals: 1578 Removing temp directory. 73.41. Executing ICE40_WRAPCARRY pass (wrap carries). 73.42. Executing TECHMAP pass (map to technology primitives). 73.42.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 73.42.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~22 debug messages> Removed 112 unused cells and 5265 unused wires. 73.43. Executing OPT_LUT pass (optimize LUTs). Discovering LUTs. Number of LUTs: 3016 1-LUT 121 2-LUT 766 3-LUT 1033 4-LUT 1096 Eliminating LUTs. Number of LUTs: 3016 1-LUT 121 2-LUT 766 3-LUT 1033 4-LUT 1096 Combining LUTs. Number of LUTs: 2862 1-LUT 120 2-LUT 581 3-LUT 952 4-LUT 1209 Eliminated 0 LUTs. Combined 154 LUTs. <suppressed ~16358 debug messages> 73.44. Executing TECHMAP pass (map to technology primitives). 73.44.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 73.44.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000101110111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110010100011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101110111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011111110011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001011001101001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000110011001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110101100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101100001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001111110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011101110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101011111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100111110100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100111000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011110011111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000100011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111011111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001011010010110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011001100110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111000001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101111100001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101001000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11100111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111110001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100010111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11110001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011010111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100000011001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011110010101010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010101111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1101111111000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110011111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010101010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100010011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011101100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000011101110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100011101110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011011100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010001111001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010001000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110110000110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00011000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110101110111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010101011000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011101000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001110010011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001101011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101110001010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010010111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100110101 for cells of type $lut. No more expansions possible. <suppressed ~5550 debug messages> Removed 0 unused cells and 6079 unused wires. 73.45. Executing AUTONAME pass. Renamed 160231 objects in module top (112 iterations). <suppressed ~6994 debug messages> 73.46. Executing HIERARCHY pass (managing design hierarchy). 73.46.1. Analyzing design hierarchy.. Top module: \top 73.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 73.47. Printing statistics. === top === Number of wires: 3137 Number of wire bits: 16141 Number of public wires: 3137 Number of public wire bits: 16141 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 5277 SB_CARRY 545 SB_DFF 201 SB_DFFE 535 SB_DFFER 295 SB_DFFES 10 SB_DFFESR 192 SB_DFFESS 56 SB_DFFR 143 SB_DFFS 29 SB_DFFSR 302 SB_DFFSS 28 SB_GB 1 SB_GB_IO 1 SB_IO 13 SB_LEDDA_IP 1 SB_LUT4 2895 SB_MAC16 3 SB_PLL40_2F_CORE 1 SB_RAM40_4K 14 SB_RAM40_4KNR 4 SB_RGBA_DRV 1 SB_SPI 2 SB_SPRAM256KA 4 SB_WARMBOOT 1 73.48. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 73.49. Executing JSON backend. Warnings: 9 unique messages, 15 total End of script. Logfile hash: 73f54a06c9, CPU: user 21.00s system 0.15s, MEM: 281.46 MB peak Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os) Time spent: 21% 33x opt_expr (4 sec), 18% 31x opt_clean (4 sec), ... nextpnr-ice40 --no-promote-globals --pre-pack data/clocks.py --seed 19 --timing-allow-fail \ --up5k --package sg48 \ -l /build/gateware/e1-tracer/build-tmp/e1-tracer.pnr.rpt \ --json /build/gateware/e1-tracer/build-tmp/e1-tracer.json \ --pcf /build/gateware/e1-tracer/data/top-e1-tracer.pcf \ --asc /build/gateware/e1-tracer/build-tmp/e1-tracer.asc Info: constrained 'e1A_rx_data' to bel 'X7/Y0/io1' Info: constrained 'e1A_rx_clk' to bel 'X6/Y0/io1' Info: constrained 'e1B_rx_data' to bel 'X6/Y0/io0' Info: constrained 'e1B_rx_clk' to bel 'X5/Y0/io0' Info: constrained 'liu_mosi' to bel 'X16/Y31/io1' Info: constrained 'liu_miso' to bel 'X16/Y31/io0' Info: constrained 'liu_clk' to bel 'X13/Y31/io1' Info: constrained 'liu_cs_n[0]' to bel 'X8/Y31/io0' Info: constrained 'liu_cs_n[1]' to bel 'X9/Y31/io0' Info: constrained 'usb_dp' to bel 'X16/Y0/io0' Info: constrained 'usb_dn' to bel 'X15/Y0/io0' Info: constrained 'usb_pu' to bel 'X13/Y0/io1' Info: constrained 'flash_mosi' to bel 'X23/Y0/io0' Info: constrained 'flash_miso' to bel 'X23/Y0/io1' Info: constrained 'flash_clk' to bel 'X24/Y0/io0' Info: constrained 'flash_cs_n' to bel 'X24/Y0/io1' Info: constrained 'vio_pdm' to bel 'X21/Y0/io1' Info: constrained 'btn' to bel 'X19/Y31/io1' Info: constrained 'clk_in' to bel 'X19/Y0/io1' Info: constrained 'dbg_tx' to bel 'X8/Y31/io1' Info: constrained 'rgb[0]' to bel 'X4/Y31/io0' Info: constrained 'rgb[1]' to bel 'X5/Y31/io0' Info: constrained 'rgb[2]' to bel 'X6/Y31/io0' Info: constraining clock net 'clk_sys' to 24.00 MHz Info: constraining clock net 'clk_48m' to 48.00 MHz Info: Packing constants.. Info: Packing IOs.. Info: btn feeds SB_IO misc_I.dfu_I.btn_iob_I, removing $nextpnr_ibuf btn. Info: clk_in feeds SB_IO sys_mgr_I.gb_in, removing $nextpnr_ibuf clk_in. Info: e1A_rx_clk feeds SB_IO e1A_rx_clk_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_clk. Info: e1A_rx_data feeds SB_IO e1A_rx_data_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_data. Info: e1B_rx_clk feeds SB_IO e1B_rx_clk_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1B_rx_clk. Info: e1B_rx_data feeds SB_IO e1B_rx_data_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1B_rx_data. Info: flash_clk feeds SB_IO spi_io_I[0], removing $nextpnr_iobuf flash_clk. Info: flash_miso feeds SB_IO spi_io_I[1], removing $nextpnr_iobuf flash_miso. Info: flash_mosi feeds SB_IO spi_io_I[2], removing $nextpnr_iobuf flash_mosi. Info: liu_clk feeds SB_IO spi_I.spi_io_I[0], removing $nextpnr_iobuf liu_clk. Info: liu_miso feeds SB_IO spi_I.spi_io_I[1], removing $nextpnr_iobuf liu_miso. Info: liu_mosi feeds SB_IO spi_I.spi_io_I[2], removing $nextpnr_iobuf liu_mosi. Info: usb_dn feeds SB_IO soc_I.usb_I.phy_I.io_dn_I, removing $nextpnr_iobuf usb_dn. Info: usb_dp feeds SB_IO soc_I.usb_I.phy_I.io_dp_I, removing $nextpnr_iobuf usb_dp. Info: rgb[0] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: rgb[1] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: rgb[2] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: Packing LUT-FFs.. Info: 1574 LCs used as LUT4 only Info: 1321 LCs used as LUT4 and DFF Info: Packing non-LUT FFs.. Info: 470 LCs used as DFF only Info: Packing carries.. Info: 193 LCs used as CARRY only Info: Packing RAMs.. Info: Placing PLLs.. Info: constrained PLL 'sys_mgr_I.pll_I' to X12/Y31/pll_3 Info: Packing special functions.. Info: constrained SB_LEDDA_IP 'soc_I.rgb_I.led_I' to X0/Y31/ledda_ip_2 Info: constrained SB_RGBA_DRV 'soc_I.rgb_I.rgb_drv_I' to X0/Y30/rgba_drv_0 Info: constrained SB_SPI 'soc_I.spi_I.spi_I' to X0/Y0/spi_0 Info: constrained SB_SPI 'spi_I.spi_I' to X25/Y0/spi_1 Info: PLL 'sys_mgr_I.pll_I' has LOCK output, need to pass all outputs via LUT Info: constrained 'sys_mgr_I.pll_lock_SB_LUT4_I3_LC' to X1/Y30/lc0 Info: Constraining chains... Info: 135 LCs used to legalise carry chains. Info: Checksum: 0xc8d6cc0b Info: Annotating ports with timing budgets for target frequency 12.00 MHz Info: Checksum: 0xace579fc Info: Device utilisation: Info: ICESTORM_LC: 3695/ 5280 69% Info: ICESTORM_RAM: 18/ 30 60% Info: SB_IO: 20/ 96 20% Info: SB_GB: 4/ 8 50% Info: ICESTORM_PLL: 1/ 1 100% Info: SB_WARMBOOT: 1/ 1 100% Info: ICESTORM_DSP: 3/ 8 37% Info: ICESTORM_HFOSC: 0/ 1 0% Info: ICESTORM_LFOSC: 0/ 1 0% Info: SB_I2C: 0/ 2 0% Info: SB_SPI: 2/ 2 100% Info: IO_I3C: 0/ 2 0% Info: SB_LEDDA_IP: 1/ 1 100% Info: SB_RGBA_DRV: 1/ 1 100% Info: ICESTORM_SPRAM: 4/ 4 100% Info: Placed 29 cells based on constraints. Info: Creating initial analytic placement for 3044 cells, random placement wirelen = 93587. Info: at initial placer iter 0, wirelen = 3471 Info: at initial placer iter 1, wirelen = 3303 Info: at initial placer iter 2, wirelen = 3281 Info: at initial placer iter 3, wirelen = 3304 Info: Running main analytical placer. Info: at iteration #1, type ALL: wirelen solved = 3291, spread = 32493, legal = 46311; time = 0.17s Info: at iteration #2, type ALL: wirelen solved = 4219, spread = 33579, legal = 42274; time = 0.23s Info: at iteration #3, type ALL: wirelen solved = 5240, spread = 29321, legal = 41637; time = 0.14s Info: at iteration #4, type ALL: wirelen solved = 6139, spread = 28817, legal = 41882; time = 0.14s Info: at iteration #5, type ALL: wirelen solved = 7072, spread = 27447, legal = 37678; time = 0.12s Info: at iteration #6, type ALL: wirelen solved = 7260, spread = 27491, legal = 38486; time = 0.12s Info: at iteration #7, type ALL: wirelen solved = 8051, spread = 27319, legal = 38253; time = 0.13s Info: at iteration #8, type ALL: wirelen solved = 8606, spread = 26417, legal = 35574; time = 0.11s Info: at iteration #9, type ALL: wirelen solved = 9313, spread = 25497, legal = 34318; time = 0.11s Info: at iteration #10, type ALL: wirelen solved = 10017, spread = 25022, legal = 35985; time = 0.12s Info: at iteration #11, type ALL: wirelen solved = 10126, spread = 25607, legal = 34302; time = 0.11s Info: at iteration #12, type ALL: wirelen solved = 11131, spread = 24331, legal = 33593; time = 0.11s Info: at iteration #13, type ALL: wirelen solved = 11759, spread = 24170, legal = 35849; time = 0.10s Info: at iteration #14, type ALL: wirelen solved = 12223, spread = 24165, legal = 38461; time = 0.12s Info: at iteration #15, type ALL: wirelen solved = 12980, spread = 23813, legal = 31849; time = 0.09s Info: at iteration #16, type ALL: wirelen solved = 13254, spread = 23219, legal = 32395; time = 0.09s Info: at iteration #17, type ALL: wirelen solved = 13770, spread = 23830, legal = 32362; time = 0.09s Info: at iteration #18, type ALL: wirelen solved = 14053, spread = 24008, legal = 35149; time = 0.10s Info: at iteration #19, type ALL: wirelen solved = 14402, spread = 23103, legal = 32522; time = 0.08s Info: at iteration #20, type ALL: wirelen solved = 14709, spread = 23097, legal = 32359; time = 0.09s Info: HeAP Placer Time: 3.17s Info: of which solving equations: 1.18s Info: of which spreading cells: 0.20s Info: of which strict legalisation: 1.07s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 496, wirelen = 31849 Info: at iteration #5: temp = 0.000000, timing cost = 469, wirelen = 26290 Info: at iteration #10: temp = 0.000000, timing cost = 413, wirelen = 25083 Info: at iteration #15: temp = 0.000000, timing cost = 400, wirelen = 24392 Info: at iteration #20: temp = 0.000000, timing cost = 381, wirelen = 24070 Info: at iteration #25: temp = 0.000000, timing cost = 372, wirelen = 23970 Info: at iteration #30: temp = 0.000000, timing cost = 374, wirelen = 23915 Info: at iteration #30: temp = 0.000000, timing cost = 374, wirelen = 23917 Info: SA placement time 7.33s Info: Max frequency for clock 'clk_sys': 27.54 MHz (PASS at 24.00 MHz) Info: Max frequency for clock 'clk_48m': 50.28 MHz (PASS at 48.00 MHz) Info: Max delay <async> -> posedge clk_sys: 9.50 ns Info: Max delay posedge clk_48m -> <async> : 4.43 ns Info: Max delay posedge clk_48m -> posedge clk_sys: 7.49 ns Info: Max delay posedge clk_sys -> <async> : 10.15 ns Info: Max delay posedge clk_sys -> posedge clk_48m: 16.62 ns Info: Slack histogram: Info: legend: * represents 29 endpoint(s) Info: + represents [1,29) endpoint(s) Info: [ 944, 4842) |*+ Info: [ 4842, 8740) |******+ Info: [ 8740, 12638) |**********+ Info: [ 12638, 16536) |***********************************+ Info: [ 16536, 20434) |*******+ Info: [ 20434, 24332) |************+ Info: [ 24332, 28230) |********************************+ Info: [ 28230, 32128) |***********************************+ Info: [ 32128, 36026) |************************************************************ Info: [ 36026, 39924) |****************************************************+ Info: [ 39924, 43822) | Info: [ 43822, 47720) | Info: [ 47720, 51618) | Info: [ 51618, 55516) | Info: [ 55516, 59414) | Info: [ 59414, 63312) | Info: [ 63312, 67210) | Info: [ 67210, 71108) | Info: [ 71108, 75006) |+ Info: [ 75006, 78904) |+ Info: Checksum: 0xf9846af1 Info: Routing.. Info: Setting up routing queue. Info: Routing 12755 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 13 986 | 13 986 | 11769| 0.14 0.14| Info: 2000 | 55 1944 | 42 958 | 10814| 0.25 0.39| Info: 3000 | 109 2890 | 54 946 | 9879| 0.25 0.64| Info: 4000 | 249 3750 | 140 860 | 9078| 0.27 0.91| Info: 5000 | 429 4570 | 180 820 | 8324| 0.28 1.19| Info: 6000 | 712 5287 | 283 717 | 7709| 0.42 1.61| Info: 7000 | 993 6006 | 281 719 | 7098| 0.54 2.15| Info: 8000 | 1318 6681 | 325 675 | 6612| 0.58 2.73| Info: 9000 | 1734 7265 | 416 584 | 6247| 0.80 3.53| Info: 10000 | 2121 7878 | 387 613 | 5976| 0.63 4.16| Info: 11000 | 2604 8395 | 483 517 | 5720| 0.50 4.66| Info: 12000 | 3054 8945 | 450 550 | 5530| 0.71 5.37| Info: 13000 | 3509 9490 | 455 545 | 5367| 0.59 5.96| Info: 14000 | 3979 10020 | 470 530 | 5155| 0.70 6.67| Info: 15000 | 4439 10560 | 460 540 | 4976| 0.49 7.16| Info: 16000 | 4897 11102 | 458 542 | 4708| 0.40 7.56| Info: 17000 | 5362 11637 | 465 535 | 4459| 0.65 8.20| Info: 18000 | 5822 12177 | 460 540 | 4265| 0.74 8.94| Info: 19000 | 6210 12789 | 388 612 | 3869| 0.55 9.50| Info: 20000 | 6690 13309 | 480 520 | 3700| 0.59 10.09| Info: 21000 | 7124 13875 | 434 566 | 3355| 1.52 11.61| Info: 22000 | 7710 14289 | 586 414 | 3279| 1.38 12.99| Info: 23000 | 8234 14765 | 524 476 | 3176| 0.96 13.95| Info: 24000 | 8786 15213 | 552 448 | 3108| 1.53 15.48| Info: 25000 | 9298 15701 | 512 488 | 2971| 0.91 16.39| Info: 26000 | 9783 16216 | 485 515 | 2893| 1.08 17.46| Info: 27000 | 10325 16674 | 542 458 | 2824| 1.17 18.64| Info: 28000 | 10908 17091 | 583 417 | 2774| 1.05 19.69| Info: 29000 | 11473 17526 | 565 435 | 2759| 1.47 21.15| Info: 30000 | 12010 17989 | 537 463 | 2639| 1.13 22.28| Info: 31000 | 12522 18477 | 512 488 | 2603| 1.37 23.65| Info: 32000 | 13131 18868 | 609 391 | 2536| 1.41 25.06| Info: 33000 | 13646 19353 | 515 485 | 2478| 1.07 26.13| Info: 34000 | 14240 19759 | 594 406 | 2444| 1.49 27.63| Info: 35000 | 14789 20210 | 549 451 | 2442| 1.16 28.78| Info: 36000 | 15311 20688 | 522 478 | 2343| 1.76 30.54| Info: 37000 | 15836 21163 | 525 475 | 2216| 0.94 31.48| Info: 38000 | 16368 21631 | 532 468 | 2095| 1.35 32.83| Info: 39000 | 16885 22114 | 517 483 | 1996| 1.13 33.95| Info: 40000 | 17394 22605 | 509 491 | 1897| 0.86 34.81| Info: 41000 | 17984 23015 | 590 410 | 1815| 1.03 35.84| Info: 42000 | 18481 23518 | 497 503 | 1602| 0.96 36.81| Info: 43000 | 19005 23994 | 524 476 | 1388| 0.78 37.59| Info: 44000 | 19532 24467 | 527 473 | 1110| 0.62 38.21| Info: 45000 | 19965 25034 | 433 567 | 740| 1.51 39.72| Info: 46000 | 20254 25745 | 289 711 | 233| 0.75 40.47| Info: 46293 | 20294 25999 | 40 254 | 0| 0.14 40.61| Info: Routing complete. Info: Router1 time 40.61s Info: Checksum: 0xd1465324 Info: Critical path report for clock 'clk_sys' (posedge -> posedge): Info: curr total Info: 1.4 1.4 Source soc_I.cpu_I.instr_sra_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_24_LC.O Info: 5.5 6.8 Net soc_I.cpu_I.alu_out_SB_LUT4_O_28_I2_SB_LUT4_O_I3[1] budget 0.000000 ns (10,12) -> (11,24) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_28_LC.I3 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:160.34-160.41 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: 0.9 7.7 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_28_LC.O Info: 1.8 9.5 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I2[3] budget 0.000000 ns (11,24) -> (10,25) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_6$CARRY.I2 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1222.14-1222.31 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:49.21-49.23 Info: 0.6 10.1 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_6$CARRY.COUT Info: 0.0 10.1 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[3] budget 0.000000 ns (10,25) -> (10,25) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_5$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 10.4 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_5$CARRY.COUT Info: 0.0 10.4 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[4] budget 0.000000 ns (10,25) -> (10,25) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_4$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 10.6 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_4$CARRY.COUT Info: 0.0 10.6 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[5] budget 0.000000 ns (10,25) -> (10,25) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_3$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 10.9 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_3$CARRY.COUT Info: 0.0 10.9 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[6] budget 0.000000 ns (10,25) -> (10,25) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_2$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 11.2 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_2$CARRY.COUT Info: 0.6 11.8 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[7] budget 0.560000 ns (10,25) -> (10,26) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_1$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 12.0 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_1$CARRY.COUT Info: 0.0 12.0 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[8] budget 0.000000 ns (10,26) -> (10,26) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 12.3 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO$CARRY.COUT Info: 0.0 12.3 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[9] budget 0.000000 ns (10,26) -> (10,26) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_29$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 12.6 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_29$CARRY.COUT Info: 0.0 12.6 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[10] budget 0.000000 ns (10,26) -> (10,26) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_28$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 12.9 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_28$CARRY.COUT Info: 0.0 12.9 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[11] budget 0.000000 ns (10,26) -> (10,26) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_27$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 13.1 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_27$CARRY.COUT Info: 0.0 13.1 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[12] budget 0.000000 ns (10,26) -> (10,26) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_26$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 13.4 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_26$CARRY.COUT Info: 0.0 13.4 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[13] budget 0.000000 ns (10,26) -> (10,26) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_25$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 13.7 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_25$CARRY.COUT Info: 0.0 13.7 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[14] budget 0.000000 ns (10,26) -> (10,26) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_24$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.0 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_24$CARRY.COUT Info: 0.6 14.5 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[15] budget 0.560000 ns (10,26) -> (10,27) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_23$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.8 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_23$CARRY.COUT Info: 0.0 14.8 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[16] budget 0.000000 ns (10,27) -> (10,27) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_22$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.1 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_22$CARRY.COUT Info: 0.0 15.1 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[17] budget 0.000000 ns (10,27) -> (10,27) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_21$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.4 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_21$CARRY.COUT Info: 0.0 15.4 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[18] budget 0.000000 ns (10,27) -> (10,27) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_20$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.6 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_20$CARRY.COUT Info: 0.0 15.6 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[19] budget 0.000000 ns (10,27) -> (10,27) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_18$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.9 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_18$CARRY.COUT Info: 0.0 15.9 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[20] budget 0.000000 ns (10,27) -> (10,27) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_17$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.2 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_17$CARRY.COUT Info: 0.0 16.2 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[21] budget 0.000000 ns (10,27) -> (10,27) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_16$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.5 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_16$CARRY.COUT Info: 0.0 16.5 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[22] budget 0.000000 ns (10,27) -> (10,27) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_15$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.8 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_15$CARRY.COUT Info: 0.6 17.3 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[23] budget 0.560000 ns (10,27) -> (10,28) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_14$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.6 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_14$CARRY.COUT Info: 0.0 17.6 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[24] budget 0.000000 ns (10,28) -> (10,28) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_13$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.9 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_13$CARRY.COUT Info: 0.0 17.9 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[25] budget 0.000000 ns (10,28) -> (10,28) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_12$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.1 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_12$CARRY.COUT Info: 0.0 18.1 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[26] budget 0.000000 ns (10,28) -> (10,28) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_11$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.4 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_11$CARRY.COUT Info: 0.0 18.4 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[27] budget 0.000000 ns (10,28) -> (10,28) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_10$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.7 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_10$CARRY.COUT Info: 0.0 18.7 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[28] budget 0.000000 ns (10,28) -> (10,28) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_9$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 19.0 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_9$CARRY.COUT Info: 0.0 19.0 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[29] budget 0.000000 ns (10,28) -> (10,28) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_7$CARRY.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 19.3 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_CARRY_CO_7$CARRY.COUT Info: 0.0 19.3 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[30] budget 0.000000 ns (10,28) -> (10,28) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 19.5 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_LC.COUT Info: 1.2 20.8 Net $nextpnr_ICESTORM_LC_28$I3 budget 1.220000 ns (10,28) -> (10,29) Info: Sink $nextpnr_ICESTORM_LC_28.I3 Info: 0.9 21.6 Source $nextpnr_ICESTORM_LC_28.O Info: 1.8 23.4 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_I0[31] budget 0.751000 ns (10,29) -> (10,28) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_LC.I0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1221.14-1221.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:37.23-37.25 Info: 1.3 24.7 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2_SB_LUT4_O_LC.O Info: 3.7 28.4 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_I2[3] budget 2.667000 ns (10,28) -> (10,19) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_LC.I3 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.9 29.3 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_LC.O Info: 1.8 31.0 Net soc_I.cpu_I.instr_bge_SB_LUT4_I1_O[1] budget 1.845000 ns (10,19) -> (11,18) Info: Sink soc_I.cpu_I.instr_bge_SB_LUT4_I1_O_SB_LUT4_I1_LC.I1 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 32.2 Source soc_I.cpu_I.instr_bge_SB_LUT4_I1_O_SB_LUT4_I1_LC.O Info: 3.6 35.8 Net soc_I.pb_rst_n_SB_LUT4_I3_2_O[2] budget 1.938000 ns (11,18) -> (14,11) Info: Sink soc_I.cpu_I.mem_do_rinst_SB_DFFSS_Q_S_SB_LUT4_O_LC.I2 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 37.1 Source soc_I.cpu_I.mem_do_rinst_SB_DFFSS_Q_S_SB_LUT4_O_LC.O Info: 1.7 38.8 Net soc_I.cpu_I.mem_do_rinst_SB_DFFSS_Q_S budget 2.286000 ns (14,11) -> (14,10) Info: Sink soc_I.cpu_I.mem_do_rinst_SB_DFFSS_Q_D_SB_LUT4_O_LC.SR Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/common/rtl/picorv32.v:1375.2-1947.5 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: 0.1 38.9 Setup soc_I.cpu_I.mem_do_rinst_SB_DFFSS_Q_D_SB_LUT4_O_LC.SR Info: 16.2 ns logic, 22.7 ns routing Info: Critical path report for clock 'clk_48m' (posedge -> posedge): Info: curr total Info: 1.4 1.4 Source soc_I.usb_I.trans_I.trans_cel_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_LC.O Info: 2.3 3.7 Net soc_I.usb_I.trans_I.mc_a_reg[0] budget 1.119000 ns (20,12) -> (18,12) Info: Sink soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_3_LC.I2 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:82.14-82.22 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: 1.2 4.9 Source soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_3_LC.O Info: 1.8 6.7 Net soc_I.usb_I.trans_I.mc_match_bits[0] budget 1.097000 ns (18,12) -> (18,12) Info: Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.I0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:85.32-85.45 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: 1.3 7.9 Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.O Info: 1.8 9.7 Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0[0] budget 1.323000 ns (18,12) -> (18,12) Info: Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.I0 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.3 11.0 Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.O Info: 1.8 12.8 Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_O[0] budget 1.236000 ns (18,12) -> (18,12) Info: Sink soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.I2 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 14.0 Source soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.O Info: 1.8 15.7 Net soc_I.usb_I.trans_I.mc_pc[0] budget 0.947000 ns (18,12) -> (17,11) Info: Sink $nextpnr_ICESTORM_LC_121.I1 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.7 16.4 Source $nextpnr_ICESTORM_LC_121.COUT Info: 0.0 16.4 Net $nextpnr_ICESTORM_LC_121$O budget 0.000000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.CIN Info: 0.3 16.7 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.COUT Info: 0.0 16.7 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[2] budget 0.000000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.9 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.COUT Info: 0.0 16.9 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[3] budget 0.000000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.2 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.COUT Info: 0.0 17.2 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[4] budget 0.000000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.5 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.COUT Info: 0.0 17.5 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[5] budget 0.000000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.8 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.COUT Info: 0.0 17.8 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[6] budget 0.000000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.CIN Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.1 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.COUT Info: 0.7 18.7 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[7] budget 0.660000 ns (17,11) -> (17,11) Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3 Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.8 19.5 Setup soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3 Info: 9.5 ns logic, 10.0 ns routing Info: Critical path report for cross-domain path '<async>' -> 'posedge clk_sys': Info: curr total Info: 0.0 0.0 Source spi_io_I[2].D_IN_0 Info: 8.8 8.8 Net flash_mosi_i budget 40.166000 ns (23,0) -> (0,0) Info: Sink soc_I.spi_I.spi_I.SI Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v:30.21-30.31 Info: /build/gateware/common/rtl/soc_base.v:304.4-324.3 Info: 1.5 10.3 Setup soc_I.spi_I.spi_I.SI Info: 1.5 ns logic, 8.8 ns routing Info: Critical path report for cross-domain path 'posedge clk_48m' -> '<async>': Info: curr total Info: 1.4 1.4 Source soc_I.usb_I.pad_pu_SB_DFFSR_Q_DFFLC.O Info: 3.1 4.4 Net usb_pu$SB_IO_OUT budget 81.943001 ns (14,4) -> (13,0) Info: Sink usb_pu$sb_io.D_OUT_0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:33.14-33.20 Info: 1.4 ns logic, 3.1 ns routing Info: Critical path report for cross-domain path 'posedge clk_48m' -> 'posedge clk_sys': Info: curr total Info: 1.4 1.4 Source soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_15_LC.O Info: 5.4 6.8 Net soc_I.wb_48m_xclk_I.m_rdata_i[0] budget 39.042000 ns (13,7) -> (16,20) Info: Sink soc_I.wb_48m_xclk_I.s_rdata_SB_DFFSR_Q_15_DFFLC.I0 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2misc//rtl/xclk_wb.v:53.15-53.24 Info: /build/gateware/common/rtl/soc_base.v:400.4-416.3 Info: 1.2 8.1 Setup soc_I.wb_48m_xclk_I.s_rdata_SB_DFFSR_Q_15_DFFLC.I0 Info: 2.6 ns logic, 5.4 ns routing Info: Critical path report for cross-domain path 'posedge clk_sys' -> '<async>': Info: curr total Info: 1.5 1.5 Source soc_I.spi_I.spi_I.MOE Info: 8.2 9.7 Net flash_mosi_oe budget 81.833000 ns (0,0) -> (23,0) Info: Sink spi_io_I[2].OUTPUT_ENABLE Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:105.4-145.3 Info: /build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v:32.21-32.32 Info: /build/gateware/common/rtl/soc_base.v:304.4-324.3 Info: 1.5 ns logic, 8.2 ns routing Info: Critical path report for cross-domain path 'posedge clk_sys' -> 'posedge clk_48m': Info: curr total Info: 1.4 1.4 Source soc_I.cpu_I.mem_la_addr_SB_LUT4_O_19_LC.O Info: 5.3 6.7 Net wb_addr[0] budget 4.333000 ns (5,24) -> (17,15) Info: Sink soc_I.e1_I.bus_rdata_SB_LUT4_O_7_I3_SB_LUT4_O_LC.I2 Info: Defined in: Info: /build/gateware/e1-tracer/rtl/top.v:72.18-72.25 Info: 1.2 7.9 Source soc_I.e1_I.bus_rdata_SB_LUT4_O_7_I3_SB_LUT4_O_LC.O Info: 1.8 9.7 Net misc_I.bus_we_boot_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_DFFSR_D_Q_SB_LUT4_I1_O_SB_DFFR_D_Q[3] budget 3.474000 ns (17,15) -> (16,14) Info: Sink soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_1_I1_SB_LUT4_O_LC.I2 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 10.9 Source soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_1_I1_SB_LUT4_O_LC.O Info: 4.1 15.0 Net soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_1_I1[1] budget 2.995000 ns (16,14) -> (12,9) Info: Sink soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_1_LC.I1 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 16.2 Setup soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_1_LC.I1 Info: 5.0 ns logic, 11.2 ns routing Info: Max frequency for clock 'clk_sys': 25.72 MHz (PASS at 24.00 MHz) Info: Max frequency for clock 'clk_48m': 51.17 MHz (PASS at 48.00 MHz) Info: Max delay <async> -> posedge clk_sys: 10.33 ns Info: Max delay posedge clk_48m -> <async> : 4.45 ns Info: Max delay posedge clk_48m -> posedge clk_sys: 8.06 ns Info: Max delay posedge clk_sys -> <async> : 9.74 ns Info: Max delay posedge clk_sys -> posedge clk_48m: 16.22 ns Info: Slack histogram: Info: legend: * represents 30 endpoint(s) Info: + represents [1,30) endpoint(s) Info: [ 1290, 5176) |*+ Info: [ 5176, 9062) |****+ Info: [ 9062, 12948) |*************+ Info: [ 12948, 16834) |********************************+ Info: [ 16834, 20720) |********+ Info: [ 20720, 24606) |*************+ Info: [ 24606, 28492) |*******************+ Info: [ 28492, 32378) |***************************************************+ Info: [ 32378, 36264) |************************************************************ Info: [ 36264, 40150) |*****************************************+ Info: [ 40150, 44036) | Info: [ 44036, 47922) | Info: [ 47922, 51808) | Info: [ 51808, 55694) | Info: [ 55694, 59580) | Info: [ 59580, 63466) | Info: [ 63466, 67352) | Info: [ 67352, 71238) | Info: [ 71238, 75124) |+ Info: [ 75124, 79010) |+ icepack -s /build/gateware/e1-tracer/build-tmp/e1-tracer.asc /build/gateware/e1-tracer/build-tmp/e1-tracer.bin make: Leaving directory '/build/gateware/e1-tracer' =============== gateware/icE1usb GATEWARE ============== make: Entering directory '/build/gateware/icE1usb' make: Leaving directory '/build/gateware/icE1usb' make: Entering directory '/build/gateware/icE1usb' /build/gateware/cores/no2usb//utils/microcode.py > /build/gateware/icE1usb/build-tmp/usb_trans_mc.hex cp -a /build/gateware/cores/no2usb//data/usb_ep_status.hex /build/gateware/icE1usb/build-tmp/usb_ep_status.hex cp ../common/fw/boot.hex /build/gateware/icE1usb/build-tmp/boot.hex cd /build/gateware/icE1usb/build-tmp && \ yosys -s /build/gateware/icE1usb/build-tmp/icE1usb.ys \ -l /build/gateware/icE1usb/build-tmp/icE1usb.synth.rpt /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os) -- Executing script file `/build/gateware/icE1usb/build-tmp/icE1usb.ys' -- 1. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/top.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/top.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_crc4.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_crc4.v' to AST representation. Generating RTLIL representation for module `\e1_crc4'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v' to AST representation. Generating RTLIL representation for module `\e1_rx_clock_recovery'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v' to AST representation. Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:68) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:209) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:215) is not recognized unless read_verilog is called with -sv! Generating RTLIL representation for module `\e1_rx_deframer'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_filter.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_filter.v' to AST representation. Generating RTLIL representation for module `\e1_rx_filter'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_phy.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_phy.v' to AST representation. Generating RTLIL representation for module `\e1_rx_phy'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx_liu.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx_liu.v' to AST representation. Generating RTLIL representation for module `\e1_rx_liu'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_rx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_rx.v' to AST representation. Generating RTLIL representation for module `\e1_rx'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_framer.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_framer.v' to AST representation. Generating RTLIL representation for module `\e1_tx_framer'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_phy.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_phy.v' to AST representation. Generating RTLIL representation for module `\e1_tx_phy'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx_liu.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx_liu.v' to AST representation. Generating RTLIL representation for module `\e1_tx_liu'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_tx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_tx.v' to AST representation. Generating RTLIL representation for module `\e1_tx'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v' to AST representation. Generating RTLIL representation for module `\e1_buf_if_wb'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb_rx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb_rx.v' to AST representation. Generating RTLIL representation for module `\e1_wb_rx'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb_tx.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb_tx.v' to AST representation. Generating RTLIL representation for module `\e1_wb_tx'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/e1_wb.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/e1_wb.v' to AST representation. Generating RTLIL representation for module `\e1_wb'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/hdb3_dec.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/hdb3_dec.v' to AST representation. Generating RTLIL representation for module `\hdb3_dec'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: /build/gateware/cores/no2e1//rtl/hdb3_enc.v Parsing Verilog input from `/build/gateware/cores/no2e1//rtl/hdb3_enc.v' to AST representation. Generating RTLIL representation for module `\hdb3_enc'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_ebr.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_ebr.v' to AST representation. Generating RTLIL representation for module `\ice40_ebr'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_i2c_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_i2c_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_i2c_wb'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_rgb_wb'. Successfully finished Verilog frontend. 22. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spi_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_spi_wb'. Successfully finished Verilog frontend. 23. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v' to AST representation. Generating RTLIL representation for module `\ice40_spram_gen'. ice40_spram_gen: (32768x32) -> 2x2 array of SPRAM Successfully finished Verilog frontend. 24. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v' to AST representation. Generating RTLIL representation for module `\ice40_spram_wb'. Successfully finished Verilog frontend. 25. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_iserdes.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_iserdes.v' to AST representation. Generating RTLIL representation for module `\ice40_iserdes'. Successfully finished Verilog frontend. 26. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_oserdes.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_oserdes.v' to AST representation. Generating RTLIL representation for module `\ice40_oserdes'. Successfully finished Verilog frontend. 27. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_crg.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_crg.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_crg'. Successfully finished Verilog frontend. 28. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_dff.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_dff.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_dff'. Successfully finished Verilog frontend. 29. Executing Verilog-2005 frontend: /build/gateware/cores/no2ice40//rtl/ice40_serdes_sync.v Parsing Verilog input from `/build/gateware/cores/no2ice40//rtl/ice40_serdes_sync.v' to AST representation. Generating RTLIL representation for module `\ice40_serdes_sync'. Successfully finished Verilog frontend. 30. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/delay.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/delay.v' to AST representation. Generating RTLIL representation for module `\delay_bit'. Generating RTLIL representation for module `\delay_bus'. Warning: Replacing memory \dl with list of registers. See /build/gateware/cores/no2misc//rtl/delay.v:59 Generating RTLIL representation for module `\delay_toggle'. Successfully finished Verilog frontend. 31. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/fifo_sync_ram.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v' to AST representation. Generating RTLIL representation for module `\fifo_sync_ram'. Successfully finished Verilog frontend. 32. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/fifo_sync_shift.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v' to AST representation. Generating RTLIL representation for module `\fifo_sync_shift'. Successfully finished Verilog frontend. 33. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/glitch_filter.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/glitch_filter.v' to AST representation. Generating RTLIL representation for module `\glitch_filter'. Successfully finished Verilog frontend. 34. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/i2c_master.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/i2c_master.v' to AST representation. Generating RTLIL representation for module `\i2c_master'. Successfully finished Verilog frontend. 35. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/i2c_master_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/i2c_master_wb.v' to AST representation. Generating RTLIL representation for module `\i2c_master_wb'. Successfully finished Verilog frontend. 36. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/muacm2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/muacm2wb.v' to AST representation. Generating RTLIL representation for module `\muacm2wb'. Successfully finished Verilog frontend. 37. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/prims.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/prims.v' to AST representation. Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:31) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:75) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:117) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:150) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:186) is not recognized unless read_verilog is called with -sv! Lexer warning: The SystemVerilog keyword `bit' (at /build/gateware/cores/no2misc//rtl/prims.v:237) is not recognized unless read_verilog is called with -sv! Generating RTLIL representation for module `\lut4_n'. Generating RTLIL representation for module `\lut4_carry_n'. Generating RTLIL representation for module `\dff_n'. Generating RTLIL representation for module `\dffe_n'. Generating RTLIL representation for module `\dffer_n'. Generating RTLIL representation for module `\dffesr_n'. Successfully finished Verilog frontend. 38. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/pdm.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/pdm.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/build/gateware/cores/no2misc//rtl/pdm.v:91) Generating RTLIL representation for module `\pdm'. Generating RTLIL representation for module `\pdm_lfsr'. Successfully finished Verilog frontend. 39. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/pwm.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/pwm.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (/build/gateware/cores/no2misc//rtl/pwm.v:69) Generating RTLIL representation for module `\pwm'. Successfully finished Verilog frontend. 40. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/ram_sdp.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/ram_sdp.v' to AST representation. Generating RTLIL representation for module `\ram_sdp'. Successfully finished Verilog frontend. 41. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/stream2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/stream2wb.v' to AST representation. Generating RTLIL representation for module `\stream2wb'. Successfully finished Verilog frontend. 42. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart2wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart2wb.v' to AST representation. Generating RTLIL representation for module `\uart2wb'. Successfully finished Verilog frontend. 43. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_rx.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_rx'. Successfully finished Verilog frontend. 44. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_tx.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. 45. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/uart_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/uart_wb.v' to AST representation. Generating RTLIL representation for module `\uart_wb'. Successfully finished Verilog frontend. 46. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/xclk_strobe.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/xclk_strobe.v' to AST representation. Generating RTLIL representation for module `\xclk_strobe'. Successfully finished Verilog frontend. 47. Executing Verilog-2005 frontend: /build/gateware/cores/no2misc//rtl/xclk_wb.v Parsing Verilog input from `/build/gateware/cores/no2misc//rtl/xclk_wb.v' to AST representation. Generating RTLIL representation for module `\xclk_wb'. Successfully finished Verilog frontend. 48. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb.v' to AST representation. Generating RTLIL representation for module `\usb'. Successfully finished Verilog frontend. 49. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_crc.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_crc.v' to AST representation. Generating RTLIL representation for module `\usb_crc'. Successfully finished Verilog frontend. 50. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_ep_buf.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_ep_buf.v' to AST representation. Generating RTLIL representation for module `\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 3 Successfully finished Verilog frontend. 51. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_ep_status.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_ep_status.v' to AST representation. Generating RTLIL representation for module `\usb_ep_status'. Successfully finished Verilog frontend. 52. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_phy.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_phy.v' to AST representation. Generating RTLIL representation for module `\usb_phy'. Successfully finished Verilog frontend. 53. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_rx_ll.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_rx_ll.v' to AST representation. Generating RTLIL representation for module `\usb_rx_ll'. Successfully finished Verilog frontend. 54. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_rx_pkt.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v' to AST representation. Generating RTLIL representation for module `\usb_rx_pkt'. Successfully finished Verilog frontend. 55. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_trans.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_trans.v' to AST representation. Generating RTLIL representation for module `\usb_trans'. Successfully finished Verilog frontend. 56. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_tx_ll.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_tx_ll.v' to AST representation. Generating RTLIL representation for module `\usb_tx_ll'. Successfully finished Verilog frontend. 57. Executing Verilog-2005 frontend: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v Parsing Verilog input from `/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v' to AST representation. Generating RTLIL representation for module `\usb_tx_pkt'. Successfully finished Verilog frontend. 58. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/led_blinker.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/led_blinker.v' to AST representation. Generating RTLIL representation for module `\led_blinker'. Successfully finished Verilog frontend. 59. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/misc.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/misc.v' to AST representation. Generating RTLIL representation for module `\misc'. Warning: Replacing memory \pdm_e1 with list of registers. See /build/gateware/icE1usb/rtl/misc.v:264 Warning: Replacing memory \pdm_clk with list of registers. See /build/gateware/icE1usb/rtl/misc.v:262 Successfully finished Verilog frontend. 60. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/sr_btn_if.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/sr_btn_if.v' to AST representation. Generating RTLIL representation for module `\sr_btn_if'. Successfully finished Verilog frontend. 61. Executing Verilog-2005 frontend: /build/gateware/icE1usb/rtl/sysmgr.v Parsing Verilog input from `/build/gateware/icE1usb/rtl/sysmgr.v' to AST representation. Generating RTLIL representation for module `\sysmgr'. Successfully finished Verilog frontend. 62. Executing Verilog-2005 frontend: /build/gateware/common/rtl/capcnt.v Parsing Verilog input from `/build/gateware/common/rtl/capcnt.v' to AST representation. Generating RTLIL representation for module `\capcnt'. Successfully finished Verilog frontend. 63. Executing Verilog-2005 frontend: /build/gateware/common/rtl/capcnt_sb_mac16.v Parsing Verilog input from `/build/gateware/common/rtl/capcnt_sb_mac16.v' to AST representation. Generating RTLIL representation for module `\capcnt16_sb_mac16'. Generating RTLIL representation for module `\capcnt32_sb_mac16'. Successfully finished Verilog frontend. 64. Executing Verilog-2005 frontend: /build/gateware/common/rtl/dfu_helper.v Parsing Verilog input from `/build/gateware/common/rtl/dfu_helper.v' to AST representation. Generating RTLIL representation for module `\dfu_helper'. Successfully finished Verilog frontend. 65. Executing Verilog-2005 frontend: /build/gateware/common/rtl/picorv32.v Parsing Verilog input from `/build/gateware/common/rtl/picorv32.v' to AST representation. Generating RTLIL representation for module `\picorv32'. Generating RTLIL representation for module `\picorv32_regs'. Generating RTLIL representation for module `\picorv32_pcpi_mul'. Generating RTLIL representation for module `\picorv32_pcpi_fast_mul'. Generating RTLIL representation for module `\picorv32_pcpi_div'. Generating RTLIL representation for module `\picorv32_axi'. Generating RTLIL representation for module `\picorv32_axi_adapter'. Generating RTLIL representation for module `\picorv32_wb'. Successfully finished Verilog frontend. 66. Executing Verilog-2005 frontend: /build/gateware/common/rtl/picorv32_ice40_regs.v Parsing Verilog input from `/build/gateware/common/rtl/picorv32_ice40_regs.v' to AST representation. Generating RTLIL representation for module `\picorv32_ice40_regs'. Successfully finished Verilog frontend. 67. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_base.v Parsing Verilog input from `/build/gateware/common/rtl/soc_base.v' to AST representation. Generating RTLIL representation for module `\soc_base'. Successfully finished Verilog frontend. 68. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_bram.v Parsing Verilog input from `/build/gateware/common/rtl/soc_bram.v' to AST representation. Generating RTLIL representation for module `\soc_bram'. Successfully finished Verilog frontend. 69. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_iobuf.v Parsing Verilog input from `/build/gateware/common/rtl/soc_iobuf.v' to AST representation. Generating RTLIL representation for module `\soc_iobuf'. Successfully finished Verilog frontend. 70. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_picorv32_bridge.v Parsing Verilog input from `/build/gateware/common/rtl/soc_picorv32_bridge.v' to AST representation. Generating RTLIL representation for module `\soc_picorv32_bridge'. Successfully finished Verilog frontend. 71. Executing Verilog-2005 frontend: /build/gateware/common/rtl/soc_spram.v Parsing Verilog input from `/build/gateware/common/rtl/soc_spram.v' to AST representation. Generating RTLIL representation for module `\soc_spram'. Successfully finished Verilog frontend. 72. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_arbiter.v Parsing Verilog input from `/build/gateware/common/rtl/wb_arbiter.v' to AST representation. Generating RTLIL representation for module `\wb_arbiter'. Successfully finished Verilog frontend. 73. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_dma.v Parsing Verilog input from `/build/gateware/common/rtl/wb_dma.v' to AST representation. Generating RTLIL representation for module `\wb_dma'. Successfully finished Verilog frontend. 74. Executing Verilog-2005 frontend: /build/gateware/common/rtl/wb_epbuf.v Parsing Verilog input from `/build/gateware/common/rtl/wb_epbuf.v' to AST representation. Generating RTLIL representation for module `\wb_epbuf'. Successfully finished Verilog frontend. 75. Executing SYNTH_ICE40 pass. 75.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. Generating RTLIL representation for module `\SB_GB'. Generating RTLIL representation for module `\SB_LUT4'. Generating RTLIL representation for module `\SB_CARRY'. Generating RTLIL representation for module `\SB_DFF'. Generating RTLIL representation for module `\SB_DFFE'. Generating RTLIL representation for module `\SB_DFFSR'. Generating RTLIL representation for module `\SB_DFFR'. Generating RTLIL representation for module `\SB_DFFSS'. Generating RTLIL representation for module `\SB_DFFS'. Generating RTLIL representation for module `\SB_DFFESR'. Generating RTLIL representation for module `\SB_DFFER'. Generating RTLIL representation for module `\SB_DFFESS'. Generating RTLIL representation for module `\SB_DFFES'. Generating RTLIL representation for module `\SB_DFFN'. Generating RTLIL representation for module `\SB_DFFNE'. Generating RTLIL representation for module `\SB_DFFNSR'. Generating RTLIL representation for module `\SB_DFFNR'. Generating RTLIL representation for module `\SB_DFFNSS'. Generating RTLIL representation for module `\SB_DFFNS'. Generating RTLIL representation for module `\SB_DFFNESR'. Generating RTLIL representation for module `\SB_DFFNER'. Generating RTLIL representation for module `\SB_DFFNESS'. Generating RTLIL representation for module `\SB_DFFNES'. Generating RTLIL representation for module `\SB_RAM40_4K'. Generating RTLIL representation for module `\SB_RAM40_4KNR'. Generating RTLIL representation for module `\SB_RAM40_4KNW'. Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. Generating RTLIL representation for module `\ICESTORM_LC'. Generating RTLIL representation for module `\SB_PLL40_CORE'. Generating RTLIL representation for module `\SB_PLL40_PAD'. Generating RTLIL representation for module `\SB_PLL40_2_PAD'. Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. Generating RTLIL representation for module `\SB_WARMBOOT'. Generating RTLIL representation for module `\SB_SPRAM256KA'. Generating RTLIL representation for module `\SB_HFOSC'. Generating RTLIL representation for module `\SB_LFOSC'. Generating RTLIL representation for module `\SB_RGBA_DRV'. Generating RTLIL representation for module `\SB_LED_DRV_CUR'. Generating RTLIL representation for module `\SB_RGB_DRV'. Generating RTLIL representation for module `\SB_I2C'. Generating RTLIL representation for module `\SB_SPI'. Generating RTLIL representation for module `\SB_LEDDA_IP'. Generating RTLIL representation for module `\SB_FILTER_50NS'. Generating RTLIL representation for module `\SB_IO_I3C'. Generating RTLIL representation for module `\SB_IO_OD'. Generating RTLIL representation for module `\SB_MAC16'. Generating RTLIL representation for module `\ICESTORM_RAM'. Successfully finished Verilog frontend. 75.2. Executing HIERARCHY pass (managing design hierarchy). 75.2.1. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: \sr_btn_if Used module: \led_blinker Used module: \i2c_master_wb Used module: \i2c_master Used module: \uart_wb Used module: \fifo_sync_ram Used module: \ram_sdp Used module: \uart_rx Used module: \glitch_filter Used module: \uart_tx Used module: \misc Used module: \pdm Used module: \capcnt Used module: \capcnt16_sb_mac16 Used module: \dfu_helper Used module: \soc_base Used module: \e1_buf_if_wb Used module: \e1_wb Used module: \e1_wb_tx Used module: \e1_tx Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: \e1_wb_rx Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: \wb_dma Used module: \wb_arbiter Used module: \wb_epbuf Used module: \ice40_spram_wb Used module: \ice40_spram_gen Used module: \xclk_strobe Used module: \xclk_wb Used module: \usb Used module: \usb_ep_status Used module: \usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: \usb_crc Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: \usb_phy Used module: \ice40_rgb_wb Used module: \ice40_spi_wb Used module: \soc_spram Used module: \soc_bram Used module: \soc_picorv32_bridge Used module: \picorv32 Used module: \picorv32_ice40_regs Used module: \ice40_ebr Parameter \TICK_LOG2_DIV = 3 75.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\sr_btn_if'. Parameter \TICK_LOG2_DIV = 3 Generating RTLIL representation for module `$paramod\sr_btn_if\TICK_LOG2_DIV=3'. Parameter \DW = 4 Parameter \FIFO_DEPTH = 0 75.2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\i2c_master_wb'. Parameter \DW = 4 Parameter \FIFO_DEPTH = 0 Generating RTLIL representation for module `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 75.2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \WB_N = 3 Parameter \E1_N = 2 Parameter \E1_UNIT_HAS_RX = 2'01 Parameter \E1_UNIT_HAS_TX = 2'01 Parameter \E1_LIU = 0 75.2.5. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_base'. Parameter \WB_N = 3 Parameter \E1_N = 2 Parameter \E1_UNIT_HAS_RX = 2'01 Parameter \E1_UNIT_HAS_TX = 2'01 Parameter \E1_LIU = 0 Generating RTLIL representation for module `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \MFW = 7 Parameter \DW = 32 75.2.6. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_buf_if_wb'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \MFW = 7 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\e1_buf_if_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\MFW=7\DW=32'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \LIU = 0 Parameter \MFW = 7 75.2.7. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb'. Parameter \N = 1 Parameter \UNIT_HAS_RX = 1'1 Parameter \UNIT_HAS_TX = 1'1 Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\LIU=0\MFW=7'. Parameter \DW = 16 Parameter \AW = 12 75.2.8. Executing AST frontend in derive mode using pre-parsed AST for module `\xclk_wb'. Parameter \DW = 16 Parameter \AW = 12 Generating RTLIL representation for module `$paramod\xclk_wb\DW=16\AW=12'. Parameter \EPDW = 32 75.2.9. Executing AST frontend in derive mode using pre-parsed AST for module `\usb'. Parameter \EPDW = 32 Generating RTLIL representation for module `$paramod\usb\EPDW=32'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 75.2.10. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_rgb_wb'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Generating RTLIL representation for module `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Found cached RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 75.2.11. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spi_wb'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 Generating RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0'. Parameter \AW = 14 75.2.12. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_spram'. Parameter \AW = 14 Generating RTLIL representation for module `$paramod\soc_spram\AW=14'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 75.2.13. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_bram'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 Generating RTLIL representation for module `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram'. Parameter \WB_N = 9 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 75.2.14. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_picorv32_bridge'. Parameter \WB_N = 9 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 Generating RTLIL representation for module `$paramod\soc_picorv32_bridge\WB_N=9\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 1 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 75.2.15. Executing AST frontend in derive mode using pre-parsed AST for module `\picorv32'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 1 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 Generating RTLIL representation for module `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32'. Parameter \WIDTH = 8 Parameter \DITHER = 16'0100111001001111 Parameter \PHY = 40'0100100101000011010001010011010000110000 75.2.16. Executing AST frontend in derive mode using pre-parsed AST for module `\pdm'. Parameter \WIDTH = 8 Parameter \DITHER = 16'0100111001001111 Parameter \PHY = 40'0100100101000011010001010011010000110000 Generating RTLIL representation for module `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm'. Parameter \WIDTH = 8 Parameter \DITHER = 16'0100111001001111 Parameter \PHY = 40'0100100101000011010001010011010000110000 Found cached RTLIL representation for module `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm'. Parameter \WIDTH = 12 Parameter \DITHER = 24'010110010100010101010011 Parameter \PHY = 40'0100100101000011010001010011010000110000 75.2.17. Executing AST frontend in derive mode using pre-parsed AST for module `\pdm'. Parameter \WIDTH = 12 Parameter \DITHER = 24'010110010100010101010011 Parameter \PHY = 40'0100100101000011010001010011010000110000 Generating RTLIL representation for module `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm'. Parameter \WIDTH = 12 Parameter \DITHER = 24'010110010100010101010011 Parameter \PHY = 40'0100100101000011010001010011010000110000 Found cached RTLIL representation for module `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm'. Parameter \W = 16 75.2.18. Executing AST frontend in derive mode using pre-parsed AST for module `\capcnt'. Parameter \W = 16 Generating RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \W = 16 Found cached RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \W = 16 Found cached RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \W = 16 Found cached RTLIL representation for module `$paramod\capcnt\W=16'. Parameter \TIMER_WIDTH = 26 Parameter \BTN_MODE = 0 Parameter \DFU_MODE = 0 75.2.19. Executing AST frontend in derive mode using pre-parsed AST for module `\dfu_helper'. Parameter \TIMER_WIDTH = 26 Parameter \BTN_MODE = 0 Parameter \DFU_MODE = 0 Generating RTLIL representation for module `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0'. Parameter \W = 32 75.2.20. Executing AST frontend in derive mode using pre-parsed AST for module `\capcnt'. Parameter \W = 32 Generating RTLIL representation for module `$paramod\capcnt\W=32'. Parameter \L = 2 Parameter \RST_VAL = 1'0 Parameter \WITH_SYNCHRONIZER = 1 75.2.21. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 2 Parameter \RST_VAL = 1'0 Parameter \WITH_SYNCHRONIZER = 1 Generating RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 75.2.22. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_ram'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 8 Parameter \GLITCH_FILTER = 2 75.2.23. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \DIV_WIDTH = 8 Parameter \GLITCH_FILTER = 2 Generating RTLIL representation for module `$paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 8 75.2.24. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \DIV_WIDTH = 8 Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=8'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 75.2.25. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Generating RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \DW = 3 Parameter \TW = 0 Parameter \CLOCK_STRETCH = 0 75.2.26. Executing AST frontend in derive mode using pre-parsed AST for module `\i2c_master'. Parameter \DW = 3 Parameter \TW = 0 Parameter \CLOCK_STRETCH = 0 Generating RTLIL representation for module `$paramod\i2c_master\DW=3\TW=0\CLOCK_STRETCH=0'. Parameter \LIU = 0 Parameter \MFW = 7 75.2.27. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_rx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_rx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 75.2.28. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Generating RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 75.2.29. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Generating RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \LIU = 0 Parameter \MFW = 7 75.2.30. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_tx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_tx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \LIU = 0 Parameter \MFW = 7 75.2.31. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_tx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_tx\LIU=0\MFW=7'. Parameter \LIU = 0 Parameter \MFW = 7 75.2.32. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb_rx'. Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb_rx\LIU=0\MFW=7'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 75.2.33. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spram_gen'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Generating RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. ice40_spram_gen: (16384x32) -> 1x2 array of SPRAM Parameter \AWIDTH = 8 Parameter \DWIDTH = 16 75.2.34. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'. Parameter \AWIDTH = 8 Parameter \DWIDTH = 16 Generating RTLIL representation for module `$paramod\ram_sdp\AWIDTH=8\DWIDTH=16'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 16 Parameter \WWIDTH = 8 75.2.35. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 16 Parameter \WWIDTH = 8 Generating RTLIL representation for module `$paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf'. READ_MODE : 2 WRITE_MODE : 3 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 16 75.2.36. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 16 Generating RTLIL representation for module `$paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 2 Parameter \TARGET = 40'0100100101000011010001010011010000110000 75.2.37. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_phy'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Generating RTLIL representation for module `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 75.2.38. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_crc'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 Generating RTLIL representation for module `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101'. Parameter \WIDTH = 16 Parameter \POLY = 16'1000000000000101 Parameter \MATCH = 16'1000000000001101 Found cached RTLIL representation for module `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101'. Parameter \WIDTH = 5 Parameter \POLY = 5'00101 Parameter \MATCH = 5'01100 75.2.39. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_crc'. Parameter \WIDTH = 5 Parameter \POLY = 5'00101 Parameter \MATCH = 5'01100 Generating RTLIL representation for module `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100'. Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 75.2.40. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 4 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 Generating RTLIL representation for module `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 75.2.41. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Generating RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \READ_MODE = 0 Parameter \WRITE_MODE = 0 Parameter \MASK_WORKAROUND = 0 Parameter \NEG_WR_CLK = 0 Parameter \NEG_RD_CLK = 1 Found cached RTLIL representation for module `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. Parameter \A0W = 14 Parameter \A1W = 9 Parameter \DW = 32 75.2.42. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_dma'. Parameter \A0W = 14 Parameter \A1W = 9 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\wb_dma\A0W=14\A1W=9\DW=32'. Parameter \N = 2 Parameter \DW = 32 Parameter \AW = 9 75.2.43. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_arbiter'. Parameter \N = 2 Parameter \DW = 32 Parameter \AW = 9 Generating RTLIL representation for module `$paramod\wb_arbiter\N=2\DW=32\AW=9'. Parameter \AW = 9 Parameter \DW = 32 75.2.44. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_epbuf'. Parameter \AW = 9 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\wb_epbuf\AW=9\DW=32'. Parameter \N = 3 Parameter \DW = 32 Parameter \AW = 14 75.2.45. Executing AST frontend in derive mode using pre-parsed AST for module `\wb_arbiter'. Parameter \N = 3 Parameter \DW = 32 Parameter \AW = 14 Generating RTLIL representation for module `$paramod\wb_arbiter\N=3\DW=32\AW=14'. Parameter \AW = 14 Parameter \DW = 32 Parameter \ZERO_RDATA = 0 75.2.46. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spram_wb'. Parameter \AW = 14 Parameter \DW = 32 Parameter \ZERO_RDATA = 0 Generating RTLIL representation for module `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0'. 75.2.47. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\sr_btn_if\TICK_LOG2_DIV=3 Used module: \led_blinker Used module: $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0 Used module: \i2c_master Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: \fifo_sync_ram Used module: $paramod\ram_sdp\AWIDTH=8\DWIDTH=16 Used module: \uart_rx Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: \uart_tx Used module: \misc Used module: $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm Used module: $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm Used module: \pdm_lfsr Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0 Used module: \glitch_filter Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1 Used module: $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base Used module: \e1_buf_if_wb Used module: \e1_wb Used module: $paramod\e1_wb_tx\LIU=0\MFW=7 Used module: \e1_tx Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: \fifo_sync_shift Used module: $paramod\e1_wb_rx\LIU=0\MFW=7 Used module: \e1_rx Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: \ice40_spram_gen Used module: \xclk_strobe Used module: \xclk_wb Used module: \usb Used module: \usb_ep_status Used module: $paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf Used module: $paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: \ice40_rgb_wb Used module: \uart_wb Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: \ram_sdp Used module: $paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2 Used module: $paramod\uart_tx\DIV_WIDTH=8 Used module: \ice40_spi_wb Used module: \soc_spram Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \soc_bram Used module: \soc_picorv32_bridge Used module: \picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \L = 4 Parameter \RST_VAL = 1'0 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 75.2.48. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'. Parameter \L = 4 Parameter \RST_VAL = 1'0 Parameter \WITH_SYNCHRONIZER = 1 Parameter \WITH_SAMP_COND = 1'0 Generating RTLIL representation for module `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Parameter \WIDTH = 8 Parameter \POLY = 8'01110001 75.2.49. Executing AST frontend in derive mode using pre-parsed AST for module `\pdm_lfsr'. Parameter \WIDTH = 8 Parameter \POLY = 8'01110001 Generating RTLIL representation for module `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001'. Parameter \DW = 4 Parameter \TW = 0 Parameter \CLOCK_STRETCH = 0 75.2.50. Executing AST frontend in derive mode using pre-parsed AST for module `\i2c_master'. Parameter \DW = 4 Parameter \TW = 0 Parameter \CLOCK_STRETCH = 0 Generating RTLIL representation for module `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 12 Parameter \GLITCH_FILTER = 2 75.2.51. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \DIV_WIDTH = 12 Parameter \GLITCH_FILTER = 2 Generating RTLIL representation for module `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2'. Parameter \DEPTH = 512 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8'. Parameter \DIV_WIDTH = 12 75.2.52. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \DIV_WIDTH = 12 Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=12'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'01 Parameter \UNIT_HAS_TX = 2'01 Parameter \MFW = 7 Parameter \DW = 32 75.2.53. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_buf_if_wb'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'01 Parameter \UNIT_HAS_TX = 2'01 Parameter \MFW = 7 Parameter \DW = 32 Generating RTLIL representation for module `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32'. Warning: Replacing memory \tx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:165 Warning: Replacing memory \tx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:145 Warning: Replacing memory \rx_addr_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:103 Warning: Replacing memory \rx_data_reg with list of registers. See /build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:102 Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'01 Parameter \UNIT_HAS_TX = 2'01 Parameter \LIU = 0 Parameter \MFW = 7 75.2.54. Executing AST frontend in derive mode using pre-parsed AST for module `\e1_wb'. Parameter \N = 2 Parameter \UNIT_HAS_RX = 2'01 Parameter \UNIT_HAS_TX = 2'01 Parameter \LIU = 0 Parameter \MFW = 7 Generating RTLIL representation for module `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7'. Parameter \DW = 16 Parameter \AW = 12 Found cached RTLIL representation for module `$paramod\xclk_wb\DW=16\AW=12'. Parameter \EPDW = 32 Found cached RTLIL representation for module `$paramod\usb\EPDW=32'. Parameter \CURRENT_MODE = 24'001100000110001000110001 Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001 Found cached RTLIL representation for module `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb'. Parameter \DIV_WIDTH = 12 Parameter \DW = 32 Found cached RTLIL representation for module `$paramod\uart_wb\DIV_WIDTH=12\DW=32'. Parameter \N_CS = 1 Parameter \WITH_IOB = 0 Parameter \UNIT = 0 Found cached RTLIL representation for module `$paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0'. Parameter \AW = 14 Found cached RTLIL representation for module `$paramod\soc_spram\AW=14'. Parameter \AW = 8 Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000 Found cached RTLIL representation for module `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram'. Parameter \WB_N = 11 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 75.2.55. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_picorv32_bridge'. Parameter \WB_N = 11 Parameter \WB_DW = 32 Parameter \WB_AW = 16 Parameter \WB_AI = 2 Parameter \WB_REG = 4 Generating RTLIL representation for module `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Parameter \ENABLE_COUNTERS = 0 Parameter \BARREL_SHIFTER = 0 Parameter \TWO_CYCLE_COMPARE = 0 Parameter \TWO_CYCLE_ALU = 1 Parameter \COMPRESSED_ISA = 0 Parameter \CATCH_MISALIGN = 0 Parameter \CATCH_ILLINSN = 0 Parameter \ENABLE_MUL = 0 Parameter \ENABLE_DIV = 0 Parameter \ENABLE_IRQ = 0 Parameter \ENABLE_IRQ_QREGS = 0 Parameter \PROGADDR_RESET = 0 Parameter \STACKADDR = 1024 Found cached RTLIL representation for module `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32'. Parameter \AWIDTH = 9 Parameter \DWIDTH = 8 75.2.56. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'. Parameter \AWIDTH = 9 Parameter \DWIDTH = 8 Generating RTLIL representation for module `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Found cached RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_tx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_rx\LIU=0\MFW=7'. Parameter \DEPTH = 4 Parameter \WIDTH = 9 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9'. Parameter \DEPTH = 4 Parameter \WIDTH = 7 Found cached RTLIL representation for module `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. 75.2.57. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\sr_btn_if\TICK_LOG2_DIV=3 Used module: \led_blinker Used module: $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0 Used module: $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0 Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: \glitch_filter Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: \misc Used module: $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm Used module: $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm Used module: $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001 Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1 Used module: $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7 Used module: \e1_wb_tx Used module: $paramod\e1_tx\LIU=0\MFW=7 Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: \e1_wb_rx Used module: $paramod\e1_rx\LIU=0\MFW=7 Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: \usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: \usb_phy Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: \ice40_spram_gen Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 32 Parameter \WWIDTH = 8 75.2.58. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 32 Parameter \WWIDTH = 8 Generating RTLIL representation for module `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf'. READ_MODE : 1 WRITE_MODE : 3 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 32 75.2.59. Executing AST frontend in derive mode using pre-parsed AST for module `\usb_ep_buf'. Parameter \TARGET = 40'0100100101000011010001010011010000110000 Parameter \RWIDTH = 8 Parameter \WWIDTH = 32 Generating RTLIL representation for module `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf'. READ_MODE : 3 WRITE_MODE : 1 Parameter \TARGET = 40'0100100101000011010001010011010000110000 Found cached RTLIL representation for module `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000'. Parameter \ADDR_WIDTH = 14 Parameter \DATA_WIDTH = 32 Found cached RTLIL representation for module `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32'. Parameter \L = 2 Parameter \RST_VAL = 1'1 Parameter \WITH_SYNCHRONIZER = 1 Found cached RTLIL representation for module `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_wb_tx\LIU=0\MFW=7'. Parameter \LIU = 0 Parameter \MFW = 7 Found cached RTLIL representation for module `$paramod\e1_wb_rx\LIU=0\MFW=7'. 75.2.60. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\sr_btn_if\TICK_LOG2_DIV=3 Used module: \led_blinker Used module: $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0 Used module: $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0 Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: \misc Used module: $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm Used module: $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm Used module: $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001 Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1 Used module: $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7 Used module: $paramod\e1_wb_tx\LIU=0\MFW=7 Used module: $paramod\e1_tx\LIU=0\MFW=7 Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\e1_wb_rx\LIU=0\MFW=7 Used module: $paramod\e1_rx\LIU=0\MFW=7 Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr 75.2.61. Analyzing design hierarchy.. Top module: \top Used module: \sysmgr Used module: $paramod\sr_btn_if\TICK_LOG2_DIV=3 Used module: \led_blinker Used module: $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0 Used module: $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0 Used module: $paramod\uart_wb\DIV_WIDTH=12\DW=32 Used module: $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8 Used module: $paramod\ram_sdp\AWIDTH=9\DWIDTH=8 Used module: $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1 Used module: $paramod\uart_tx\DIV_WIDTH=12 Used module: \misc Used module: $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm Used module: $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm Used module: $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001 Used module: $paramod\capcnt\W=16 Used module: \capcnt16_sb_mac16 Used module: $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0 Used module: $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0 Used module: $paramod\capcnt\W=32 Used module: \capcnt32_sb_mac16 Used module: $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1 Used module: $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base Used module: $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32 Used module: $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7 Used module: $paramod\e1_wb_tx\LIU=0\MFW=7 Used module: $paramod\e1_tx\LIU=0\MFW=7 Used module: \e1_tx_phy Used module: \hdb3_enc Used module: \e1_tx_framer Used module: \e1_crc4 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7 Used module: $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9 Used module: $paramod\e1_wb_rx\LIU=0\MFW=7 Used module: $paramod\e1_rx\LIU=0\MFW=7 Used module: \hdb3_dec Used module: \e1_rx_clock_recovery Used module: \e1_rx_filter Used module: \e1_rx_phy Used module: \e1_rx_deframer Used module: \soc_iobuf Used module: $paramod\wb_dma\A0W=14\A1W=9\DW=32 Used module: $paramod\wb_arbiter\N=2\DW=32\AW=9 Used module: $paramod\wb_epbuf\AW=9\DW=32 Used module: $paramod\wb_arbiter\N=3\DW=32\AW=14 Used module: $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0 Used module: $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32 Used module: \xclk_strobe Used module: $paramod\xclk_wb\DW=16\AW=12 Used module: $paramod\usb\EPDW=32 Used module: \usb_ep_status Used module: $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf Used module: $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf Used module: \usb_trans Used module: \usb_rx_pkt Used module: $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101 Used module: $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100 Used module: \usb_rx_ll Used module: \usb_tx_pkt Used module: \usb_tx_ll Used module: $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000 Used module: $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb Used module: $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0 Used module: $paramod\soc_spram\AW=14 Used module: $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram Used module: $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4 Used module: $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32 Used module: \picorv32_ice40_regs Used module: $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr Removing unused module `$paramod\glitch_filter\L=4\RST_VAL=1'1\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0'. Removing unused module `$paramod$e9a8417cc0e9fc03e370009e77135e9e1e2b5499\usb_ep_buf'. Removing unused module `$paramod$7d82212fad3e4929db14b64ca83adffce21ba555\usb_ep_buf'. Removing unused module `$paramod\ram_sdp\AWIDTH=8\DWIDTH=16'. Removing unused module `$paramod\i2c_master\DW=3\TW=0\CLOCK_STRETCH=0'. Removing unused module `$paramod\uart_tx\DIV_WIDTH=8'. Removing unused module `$paramod\uart_rx\DIV_WIDTH=8\GLITCH_FILTER=2'. Removing unused module `$paramod\soc_picorv32_bridge\WB_N=9\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4'. Removing unused module `$paramod\e1_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\LIU=0\MFW=7'. Removing unused module `$paramod\e1_buf_if_wb\N=1\UNIT_HAS_RX=1'1\UNIT_HAS_TX=1'1\MFW=7\DW=32'. Removing unused module `\wb_epbuf'. Removing unused module `\wb_dma'. Removing unused module `\wb_arbiter'. Removing unused module `\soc_spram'. Removing unused module `\soc_picorv32_bridge'. Removing unused module `\soc_bram'. Removing unused module `\soc_base'. Removing unused module `\picorv32_wb'. Removing unused module `\picorv32_axi_adapter'. Removing unused module `\picorv32_axi'. Removing unused module `\picorv32_pcpi_div'. Removing unused module `\picorv32_pcpi_fast_mul'. Removing unused module `\picorv32_pcpi_mul'. Removing unused module `\picorv32_regs'. Removing unused module `\picorv32'. Removing unused module `\dfu_helper'. Removing unused module `\capcnt'. Removing unused module `\sr_btn_if'. Removing unused module `\usb_phy'. Removing unused module `\usb_ep_buf'. Removing unused module `\usb_crc'. Removing unused module `\usb'. Removing unused module `\xclk_wb'. Removing unused module `\uart_wb'. Removing unused module `\uart_tx'. Removing unused module `\uart_rx'. Removing unused module `\uart2wb'. Removing unused module `\stream2wb'. Removing unused module `\ram_sdp'. Removing unused module `\pwm'. Removing unused module `\pdm_lfsr'. Removing unused module `\pdm'. Removing unused module `\dffesr_n'. Removing unused module `\dffer_n'. Removing unused module `\dffe_n'. Removing unused module `\dff_n'. Removing unused module `\lut4_carry_n'. Removing unused module `\lut4_n'. Removing unused module `\muacm2wb'. Removing unused module `\i2c_master_wb'. Removing unused module `\i2c_master'. Removing unused module `\glitch_filter'. Removing unused module `\fifo_sync_shift'. Removing unused module `\fifo_sync_ram'. Removing unused module `\delay_bus'. Removing unused module `\delay_bit'. Removing unused module `\ice40_serdes_sync'. Removing unused module `\ice40_serdes_dff'. Removing unused module `\ice40_serdes_crg'. Removing unused module `\ice40_oserdes'. Removing unused module `\ice40_iserdes'. Removing unused module `\ice40_spram_wb'. Removing unused module `\ice40_spram_gen'. Removing unused module `\ice40_spi_wb'. Removing unused module `\ice40_rgb_wb'. Removing unused module `\ice40_i2c_wb'. Removing unused module `\ice40_ebr'. Removing unused module `\e1_wb'. Removing unused module `\e1_wb_tx'. Removing unused module `\e1_wb_rx'. Removing unused module `\e1_buf_if_wb'. Removing unused module `\e1_tx'. Removing unused module `\e1_tx_liu'. Removing unused module `\e1_rx'. Removing unused module `\e1_rx_liu'. Removed 75 unused modules. 75.3. Executing PROC pass (convert processes to netlists). 75.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5573'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5518'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4813'. Found and cleaned up 1 empty switch in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4290'. Found and cleaned up 15 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. Found and cleaned up 1 empty switch in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4083'. Found and cleaned up 6 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:530$3729'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:530$3729'. Found and cleaned up 1 empty switch in `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:0$3535'. Removing empty process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:0$3535'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:471$3445'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:471$3445'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$140'. Cleaned up 26 empty switches. 75.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3064 in module SB_DFFNES. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3057 in module SB_DFFNESS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3053 in module SB_DFFNER. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3046 in module SB_DFFNESR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3043 in module SB_DFFNS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3040 in module SB_DFFNSS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3037 in module SB_DFFNR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3034 in module SB_DFFNSR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3026 in module SB_DFFES. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3019 in module SB_DFFESS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3015 in module SB_DFFER. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3008 in module SB_DFFESR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$3005 in module SB_DFFS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$3002 in module SB_DFFSS. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2999 in module SB_DFFR. Marked 1 switch rules as full_case in process $proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2996 in module SB_DFFSR. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5190 in module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5186 in module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5182 in module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5174 in module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5171 in module $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:116$5150 in module $paramod\wb_arbiter\N=3\DW=32\AW=14. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:80$5138 in module $paramod\wb_arbiter\N=3\DW=32\AW=14. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_epbuf.v:51$5107 in module $paramod\wb_epbuf\AW=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:116$5096 in module $paramod\wb_arbiter\N=2\DW=32\AW=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_arbiter.v:80$5086 in module $paramod\wb_arbiter\N=2\DW=32\AW=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:190$5054 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:98$5015 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:92$5014 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/wb_dma.v:86$5010 in module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Removed 2 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4931 in module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4931 in module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5452 in module $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4. Marked 16 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656 in module $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:247$4634 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:240$4632 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4614 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4613 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4605 in module $paramod\e1_wb_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4599 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4597 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4574 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4573 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4565 in module $paramod\e1_wb_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1719 in module sysmgr. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1714 in module sysmgr. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4560 in module $paramod\e1_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4550 in module $paramod\e1_tx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:302$1639 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:260$1638 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:183$1637 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:170$1636 in module misc. Marked 2 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:130$1635 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/misc.v:110$1625 in module misc. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1607 in module led_blinker. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1550 in module usb_tx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1534 in module usb_tx_pkt. Marked 8 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1532 in module usb_tx_pkt. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1529 in module usb_tx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1529 in module usb_tx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1507 in module usb_tx_ll. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1501 in module usb_tx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1497 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1486 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1470 in module usb_trans. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1455 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1452 in module usb_trans. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1447 in module usb_trans. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1436 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1431 in module usb_trans. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1428 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1428 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1419 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1410 in module usb_trans. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1347 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1344 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1341 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1338 in module usb_rx_pkt. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1328 in module usb_rx_pkt. Marked 18 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1312 in module usb_rx_pkt. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1307 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1307 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1306 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1305 in module usb_rx_ll. Removed 1 dead cases from process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1289 in module usb_rx_ll. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1289 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1279 in module usb_rx_ll. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4540 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4538 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4529 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4527 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4518 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4516 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4507 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4505 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4494 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4492 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4483 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4481 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4472 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4470 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4461 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4459 in module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:203$4448 in module $paramod\e1_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:188$4438 in module $paramod\e1_rx\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5374 in module $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4400 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4396 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4392 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4384 in module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1107 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1106 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1104 in module xclk_strobe. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5349 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5342 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5331 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5293 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5291 in module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5263 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5260 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5256 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5252 in module $paramod\uart_tx\DIV_WIDTH=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4345 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4339 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4337 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4328 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4322 in module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4316 in module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4312 in module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4308 in module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4300 in module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:149$4299 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:120$4290 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:109$4286 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/dfu_helper.v:103$4284 in module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4277 in module $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4273 in module $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm. Marked 37 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1375$4097 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1288$4069 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1274$4064 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 8 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:1165$4029 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 3 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:840$3769 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 3 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:791$3767 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:760$3763 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 47 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:684$3762 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 4 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:549$3738 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:414$3700 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Removed 2 dead cases from process $proc$/build/gateware/common/rtl/picorv32.v:385$3697 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 2 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:385$3697 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:374$3692 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/picorv32.v:309$3618 in module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5242 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5238 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5234 in module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3499 in module $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3493 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3485 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3481 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3477 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3473 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3459 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3446 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3444 in module $paramod\usb\EPDW=32. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3440 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3422 in module $paramod\usb\EPDW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3418 in module $paramod\xclk_wb\DW=16\AW=12. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3411 in module $paramod\xclk_wb\DW=16\AW=12. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5221 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5218 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5214 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Removed 1 dead cases from process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5210 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5210 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5206 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 7 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5200 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5199 in module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5198 in module $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001. Marked 1 switch rules as full_case in process $proc$/build/gateware/common/rtl/soc_base.v:185$3322 in module $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3306 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3296 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3279 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3274 in module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3269 in module $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0. Marked 9 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3205 in module $paramod\sr_btn_if\TICK_LOG2_DIV=3. Marked 1 switch rules as full_case in process $proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3204 in module $paramod\sr_btn_if\TICK_LOG2_DIV=3. Marked 4 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$447 in module hdb3_enc. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$443 in module hdb3_dec. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:253$252 in module e1_tx_framer. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:241$250 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:209$237 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:199$234 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:192$230 in module e1_tx_framer. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:167$227 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:148$223 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$218 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$215 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:113$213 in module e1_tx_framer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:97$205 in module e1_tx_framer. Marked 2 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$168 in module e1_rx_filter. Marked 5 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$149 in module e1_rx_filter. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$146 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$140 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$114 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$94 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$72 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$60 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$56 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$52 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$42 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$38 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$34 in module e1_rx_deframer. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$26 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$24 in module e1_rx_deframer. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$19 in module e1_rx_deframer. Marked 3 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:39$17 in module e1_rx_clock_recovery. Marked 1 switch rules as full_case in process $proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:33$15 in module e1_rx_clock_recovery. Removed a total of 9 dead cases. 75.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 153 redundant assignments. Promoted 315 assignments to connections. 75.3.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3067'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3063'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3056'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3052'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3045'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3042'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3039'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3036'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3033'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3031'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3029'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3025'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3018'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3014'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3007'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3004'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3001'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2998'. Set init value: \Q = 1'0 Found init rule in `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2995'. Set init value: \Q = 1'0 Found init rule in `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2993'. Set init value: \Q = 1'0 Found init rule in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1311'. Set init value: \dec_sym_1 = 2'00 75.3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \S in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3064'. Found async reset \R in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3053'. Found async reset \S in `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3043'. Found async reset \R in `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3037'. Found async reset \S in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3026'. Found async reset \R in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3015'. Found async reset \S in `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$3005'. Found async reset \R in `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2999'. Found async reset \rst in `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5171'. Found async reset \rst in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5150'. Found async reset \rst in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5138'. Found async reset \rst in `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$5107'. Found async reset \rst in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5096'. Found async reset \rst in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5086'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5054'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$5014'. Found async reset \rst in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$5010'. Found async reset \rst in `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4931'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:247$4634'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:240$4632'. Found async reset \rst in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4613'. Found async reset \rst in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4599'. Found async reset \rst in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4597'. Found async reset \rst in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4573'. Found async reset \rst_30m72_i in `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1719'. Found async reset \pll_lock in `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1714'. Found async reset \rst in `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4550'. Found async reset \rst in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:302$1639'. Found async reset \rst in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1638'. Found async reset \rst in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:183$1637'. Found async reset \rst in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:170$1636'. Found async reset \rst in `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1607'. Found async reset \rst in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1534'. Found async reset \rst in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1529'. Found async reset \ll_start in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1507'. Found async reset \rst in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1501'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1470'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1452'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1447'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1436'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1431'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1419'. Found async reset \rst in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1410'. Found async reset \rst in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1328'. Found async reset \rst in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1279'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4540'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4538'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4529'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4527'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4518'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4516'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4507'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4505'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4494'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4492'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4483'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4481'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4472'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4470'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4461'. Found async reset \rst in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4459'. Found async reset \rst in `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:203$4448'. Found async reset \rst in `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:188$4438'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1107'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1106'. Found async reset \rst in `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1104'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5349'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5342'. Found async reset \rst in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5293'. Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5263'. Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5252'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4345'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4339'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4337'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4328'. Found async reset \rst in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4322'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4299'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4290'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4286'. Found async reset \rst in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4284'. Found async reset \rst in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5234'. Found async reset \rst in `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3499'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3493'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3481'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3459'. Found async reset \rst in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3444'. Found async reset \rst in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3418'. Found async reset \rst_sys in `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3322'. Found async reset \rst in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3274'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:253$252'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:241$250'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:209$237'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:199$234'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:192$230'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:148$223'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$218'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$215'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:113$213'. Found async reset \rst in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:97$205'. 75.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3067'. Creating decoders for process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3064'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3063'. Creating decoders for process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3057'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3056'. Creating decoders for process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3053'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3052'. Creating decoders for process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3046'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3045'. Creating decoders for process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3043'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3042'. Creating decoders for process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3040'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3039'. Creating decoders for process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3037'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3036'. Creating decoders for process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3034'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3033'. Creating decoders for process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$3032'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3031'. Creating decoders for process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$3030'. Creating decoders for process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3029'. Creating decoders for process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3026'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3025'. Creating decoders for process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3019'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3018'. Creating decoders for process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3015'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3014'. Creating decoders for process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3008'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3007'. Creating decoders for process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$3005'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3004'. Creating decoders for process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$3002'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3001'. Creating decoders for process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2999'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2998'. Creating decoders for process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2996'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2995'. Creating decoders for process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2994'. 1/1: $0\Q[0:0] Creating decoders for process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2993'. Creating decoders for process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2992'. Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$5195'. Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5190'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5186'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5182'. 1/1: $0\cnt[3:0] Creating decoders for process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5174'. 1/2: $2\cnt_move[3:0] 2/2: $1\cnt_move[3:0] Creating decoders for process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5171'. 1/1: $0\ack_i[0:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5150'. 1/2: $0\busy[0:0] 2/2: $0\sel[2:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5141'. 1/3: $0\sel_nxt[2:0] [2] 2/3: $0\sel_nxt[2:0] [0] 3/3: $0\sel_nxt[2:0] [1] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5138'. 1/4: $0\m_wmsk[3:0] 2/4: $0\m_we[0:0] 3/4: $0\m_wdata[31:0] 4/4: $0\m_addr[13:0] Creating decoders for process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5119'. Creating decoders for process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$5107'. 1/1: $0\ack_i[0:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5096'. 1/2: $0\busy[0:0] 2/2: $0\sel[1:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5089'. 1/2: $0\sel_nxt[1:0] [1] 2/2: $0\sel_nxt[1:0] [0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5086'. 1/4: $0\m_wmsk[3:0] 2/4: $0\m_we[0:0] 3/4: $0\m_wdata[31:0] 4/4: $0\m_addr[8:0] Creating decoders for process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5073'. Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5054'. 1/3: $0\ctl_ack_i[0:0] 2/3: $0\ctl_do_read[0:0] 3/3: $0\ctl_do_write[0:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$5050'. 1/1: $0\dir[0:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$5047'. 1/1: $0\len[12:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$5037'. 1/1: $0\m1_addr_i[8:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$5033'. 1/1: $0\m0_addr_i[13:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$5031'. 1/1: $0\data_reg[31:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$5015'. 1/1: $0\state_nxt[1:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$5014'. 1/1: $0\state[1:0] Creating decoders for process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$5010'. 1/1: $0\go[0:0] Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5006'. Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5002'. Creating decoders for process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4998'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5569'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5565'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5561'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5557'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5553'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5549'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5545'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5541'. Creating decoders for process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5537'. Creating decoders for process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4968'. 1/1: $0\state[4:0] Creating decoders for process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4955'. 1/1: $0\state[15:0] Creating decoders for process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4931'. 1/2: $0\dn_state[2:0] 2/2: $0\dp_state[2:0] Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5514'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5510'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5506'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5502'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5498'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5494'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5490'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5486'. Creating decoders for process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5482'. Creating decoders for process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5458'. 1/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 2/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_DATA[7:0]$5460 3/4: $0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_ADDR[8:0]$5459 4/4: $0\rd_data[7:0] Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5452'. 1/1: $0\wb_rdata_reg[31:0] Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5450'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5423'. Creating decoders for process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5420'. Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4812'. Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656'. 1/320: $8\mem_dm_w[7:0] [7] 2/320: $8\mem_dm_w[7:0] [4] 3/320: $8\mem_dm_w[7:0] [2] 4/320: $8\mem_dm_w[7:0] [0] 5/320: $8\mem_dm_w[7:0] [6] 6/320: $8\mem_dm_w[7:0] [1] 7/320: $8\mem_dm_w[7:0] [3] 8/320: $8\mem_dm_w[7:0] [5] 9/320: $8\mem_di_w[31:0] [31] 10/320: $8\mem_di_w[31:0] [24] 11/320: $8\mem_di_w[31:0] [22] 12/320: $8\mem_di_w[31:0] [20] 13/320: $8\mem_di_w[31:0] [18] 14/320: $8\mem_di_w[31:0] [16] 15/320: $8\mem_di_w[31:0] [14] 16/320: $8\mem_di_w[31:0] [12] 17/320: $8\mem_di_w[31:0] [10] 18/320: $8\mem_di_w[31:0] [8] 19/320: $8\mem_di_w[31:0] [6] 20/320: $8\mem_di_w[31:0] [4] 21/320: $8\mem_di_w[31:0] [2] 22/320: $8\mem_di_w[31:0] [0] 23/320: $8\mem_di_w[31:0] [30] 24/320: $8\mem_di_w[31:0] [27] 25/320: $8\mem_di_w[31:0] [23] 26/320: $8\mem_di_w[31:0] [21] 27/320: $8\mem_di_w[31:0] [17] 28/320: $8\mem_di_w[31:0] [13] 29/320: $8\mem_di_w[31:0] [9] 30/320: $8\mem_di_w[31:0] [5] 31/320: $8\mem_di_w[31:0] [1] 32/320: $8\mem_di_w[31:0] [28] 33/320: $8\mem_di_w[31:0] [26] 34/320: $8\mem_di_w[31:0] [15] 35/320: $8\mem_di_w[31:0] [3] 36/320: $8\mem_di_w[31:0] [7] 37/320: $8\mem_di_w[31:0] [25] 38/320: $8\mem_di_w[31:0] [19] 39/320: $8\mem_di_w[31:0] [29] 40/320: $8\mem_di_w[31:0] [11] 41/320: $7\mem_dm_w[7:0] [7] 42/320: $7\mem_dm_w[7:0] [4] 43/320: $7\mem_dm_w[7:0] [2] 44/320: $7\mem_dm_w[7:0] [0] 45/320: $7\mem_dm_w[7:0] [6] 46/320: $7\mem_dm_w[7:0] [1] 47/320: $7\mem_dm_w[7:0] [3] 48/320: $7\mem_dm_w[7:0] [5] 49/320: $7\mem_di_w[31:0] [31] 50/320: $7\mem_di_w[31:0] [24] 51/320: $7\mem_di_w[31:0] [22] 52/320: $7\mem_di_w[31:0] [20] 53/320: $7\mem_di_w[31:0] [18] 54/320: $7\mem_di_w[31:0] [16] 55/320: $7\mem_di_w[31:0] [14] 56/320: $7\mem_di_w[31:0] [12] 57/320: $7\mem_di_w[31:0] [10] 58/320: $7\mem_di_w[31:0] [8] 59/320: $7\mem_di_w[31:0] [6] 60/320: $7\mem_di_w[31:0] [4] 61/320: $7\mem_di_w[31:0] [2] 62/320: $7\mem_di_w[31:0] [0] 63/320: $7\mem_di_w[31:0] [30] 64/320: $7\mem_di_w[31:0] [27] 65/320: $7\mem_di_w[31:0] [23] 66/320: $7\mem_di_w[31:0] [21] 67/320: $7\mem_di_w[31:0] [17] 68/320: $7\mem_di_w[31:0] [13] 69/320: $7\mem_di_w[31:0] [9] 70/320: $7\mem_di_w[31:0] [5] 71/320: $7\mem_di_w[31:0] [1] 72/320: $7\mem_di_w[31:0] [28] 73/320: $7\mem_di_w[31:0] [26] 74/320: $7\mem_di_w[31:0] [15] 75/320: $7\mem_di_w[31:0] [3] 76/320: $7\mem_di_w[31:0] [7] 77/320: $7\mem_di_w[31:0] [25] 78/320: $7\mem_di_w[31:0] [19] 79/320: $7\mem_di_w[31:0] [29] 80/320: $7\mem_di_w[31:0] [11] 81/320: $6\mem_dm_w[7:0] [7] 82/320: $6\mem_dm_w[7:0] [4] 83/320: $6\mem_dm_w[7:0] [2] 84/320: $6\mem_dm_w[7:0] [0] 85/320: $6\mem_dm_w[7:0] [6] 86/320: $6\mem_dm_w[7:0] [1] 87/320: $6\mem_dm_w[7:0] [3] 88/320: $6\mem_dm_w[7:0] [5] 89/320: $6\mem_di_w[31:0] [31] 90/320: $6\mem_di_w[31:0] [24] 91/320: $6\mem_di_w[31:0] [22] 92/320: $6\mem_di_w[31:0] [20] 93/320: $6\mem_di_w[31:0] [18] 94/320: $6\mem_di_w[31:0] [16] 95/320: $6\mem_di_w[31:0] [14] 96/320: $6\mem_di_w[31:0] [12] 97/320: $6\mem_di_w[31:0] [10] 98/320: $6\mem_di_w[31:0] [8] 99/320: $6\mem_di_w[31:0] [6] 100/320: $6\mem_di_w[31:0] [4] 101/320: $6\mem_di_w[31:0] [2] 102/320: $6\mem_di_w[31:0] [0] 103/320: $6\mem_di_w[31:0] [30] 104/320: $6\mem_di_w[31:0] [27] 105/320: $6\mem_di_w[31:0] [23] 106/320: $6\mem_di_w[31:0] [21] 107/320: $6\mem_di_w[31:0] [17] 108/320: $6\mem_di_w[31:0] [13] 109/320: $6\mem_di_w[31:0] [9] 110/320: $6\mem_di_w[31:0] [5] 111/320: $6\mem_di_w[31:0] [1] 112/320: $6\mem_di_w[31:0] [28] 113/320: $6\mem_di_w[31:0] [26] 114/320: $6\mem_di_w[31:0] [15] 115/320: $6\mem_di_w[31:0] [3] 116/320: $6\mem_di_w[31:0] [7] 117/320: $6\mem_di_w[31:0] [25] 118/320: $6\mem_di_w[31:0] [19] 119/320: $6\mem_di_w[31:0] [29] 120/320: $6\mem_di_w[31:0] [11] 121/320: $5\mem_dm_w[7:0] [7] 122/320: $5\mem_dm_w[7:0] [4] 123/320: $5\mem_dm_w[7:0] [2] 124/320: $5\mem_dm_w[7:0] [0] 125/320: $5\mem_dm_w[7:0] [6] 126/320: $5\mem_dm_w[7:0] [1] 127/320: $5\mem_dm_w[7:0] [3] 128/320: $5\mem_dm_w[7:0] [5] 129/320: $5\mem_di_w[31:0] [31] 130/320: $5\mem_di_w[31:0] [24] 131/320: $5\mem_di_w[31:0] [22] 132/320: $5\mem_di_w[31:0] [20] 133/320: $5\mem_di_w[31:0] [18] 134/320: $5\mem_di_w[31:0] [16] 135/320: $5\mem_di_w[31:0] [14] 136/320: $5\mem_di_w[31:0] [12] 137/320: $5\mem_di_w[31:0] [10] 138/320: $5\mem_di_w[31:0] [8] 139/320: $5\mem_di_w[31:0] [6] 140/320: $5\mem_di_w[31:0] [4] 141/320: $5\mem_di_w[31:0] [2] 142/320: $5\mem_di_w[31:0] [0] 143/320: $5\mem_di_w[31:0] [30] 144/320: $5\mem_di_w[31:0] [27] 145/320: $5\mem_di_w[31:0] [23] 146/320: $5\mem_di_w[31:0] [21] 147/320: $5\mem_di_w[31:0] [17] 148/320: $5\mem_di_w[31:0] [13] 149/320: $5\mem_di_w[31:0] [9] 150/320: $5\mem_di_w[31:0] [5] 151/320: $5\mem_di_w[31:0] [1] 152/320: $5\mem_di_w[31:0] [28] 153/320: $5\mem_di_w[31:0] [26] 154/320: $5\mem_di_w[31:0] [15] 155/320: $5\mem_di_w[31:0] [3] 156/320: $5\mem_di_w[31:0] [7] 157/320: $5\mem_di_w[31:0] [25] 158/320: $5\mem_di_w[31:0] [19] 159/320: $5\mem_di_w[31:0] [29] 160/320: $5\mem_di_w[31:0] [11] 161/320: $4\mem_dm_w[7:0] [7] 162/320: $4\mem_dm_w[7:0] [4] 163/320: $4\mem_dm_w[7:0] [2] 164/320: $4\mem_dm_w[7:0] [0] 165/320: $4\mem_dm_w[7:0] [6] 166/320: $4\mem_dm_w[7:0] [1] 167/320: $4\mem_dm_w[7:0] [3] 168/320: $4\mem_dm_w[7:0] [5] 169/320: $4\mem_di_w[31:0] [31] 170/320: $4\mem_di_w[31:0] [24] 171/320: $4\mem_di_w[31:0] [22] 172/320: $4\mem_di_w[31:0] [20] 173/320: $4\mem_di_w[31:0] [18] 174/320: $4\mem_di_w[31:0] [16] 175/320: $4\mem_di_w[31:0] [14] 176/320: $4\mem_di_w[31:0] [12] 177/320: $4\mem_di_w[31:0] [10] 178/320: $4\mem_di_w[31:0] [8] 179/320: $4\mem_di_w[31:0] [6] 180/320: $4\mem_di_w[31:0] [4] 181/320: $4\mem_di_w[31:0] [2] 182/320: $4\mem_di_w[31:0] [0] 183/320: $4\mem_di_w[31:0] [30] 184/320: $4\mem_di_w[31:0] [27] 185/320: $4\mem_di_w[31:0] [23] 186/320: $4\mem_di_w[31:0] [21] 187/320: $4\mem_di_w[31:0] [17] 188/320: $4\mem_di_w[31:0] [13] 189/320: $4\mem_di_w[31:0] [9] 190/320: $4\mem_di_w[31:0] [5] 191/320: $4\mem_di_w[31:0] [1] 192/320: $4\mem_di_w[31:0] [28] 193/320: $4\mem_di_w[31:0] [26] 194/320: $4\mem_di_w[31:0] [15] 195/320: $4\mem_di_w[31:0] [3] 196/320: $4\mem_di_w[31:0] [7] 197/320: $4\mem_di_w[31:0] [25] 198/320: $4\mem_di_w[31:0] [19] 199/320: $4\mem_di_w[31:0] [29] 200/320: $4\mem_di_w[31:0] [11] 201/320: $3\mem_dm_w[7:0] [7] 202/320: $3\mem_dm_w[7:0] [4] 203/320: $3\mem_dm_w[7:0] [2] 204/320: $3\mem_dm_w[7:0] [0] 205/320: $3\mem_dm_w[7:0] [6] 206/320: $3\mem_dm_w[7:0] [1] 207/320: $3\mem_dm_w[7:0] [3] 208/320: $3\mem_dm_w[7:0] [5] 209/320: $3\mem_di_w[31:0] [31] 210/320: $3\mem_di_w[31:0] [24] 211/320: $3\mem_di_w[31:0] [22] 212/320: $3\mem_di_w[31:0] [20] 213/320: $3\mem_di_w[31:0] [18] 214/320: $3\mem_di_w[31:0] [16] 215/320: $3\mem_di_w[31:0] [14] 216/320: $3\mem_di_w[31:0] [12] 217/320: $3\mem_di_w[31:0] [10] 218/320: $3\mem_di_w[31:0] [8] 219/320: $3\mem_di_w[31:0] [6] 220/320: $3\mem_di_w[31:0] [4] 221/320: $3\mem_di_w[31:0] [2] 222/320: $3\mem_di_w[31:0] [0] 223/320: $3\mem_di_w[31:0] [30] 224/320: $3\mem_di_w[31:0] [27] 225/320: $3\mem_di_w[31:0] [23] 226/320: $3\mem_di_w[31:0] [21] 227/320: $3\mem_di_w[31:0] [17] 228/320: $3\mem_di_w[31:0] [13] 229/320: $3\mem_di_w[31:0] [9] 230/320: $3\mem_di_w[31:0] [5] 231/320: $3\mem_di_w[31:0] [1] 232/320: $3\mem_di_w[31:0] [28] 233/320: $3\mem_di_w[31:0] [26] 234/320: $3\mem_di_w[31:0] [15] 235/320: $3\mem_di_w[31:0] [3] 236/320: $3\mem_di_w[31:0] [7] 237/320: $3\mem_di_w[31:0] [25] 238/320: $3\mem_di_w[31:0] [19] 239/320: $3\mem_di_w[31:0] [29] 240/320: $3\mem_di_w[31:0] [11] 241/320: $2\mem_dm_w[7:0] [7] 242/320: $2\mem_dm_w[7:0] [4] 243/320: $2\mem_dm_w[7:0] [2] 244/320: $2\mem_dm_w[7:0] [0] 245/320: $2\mem_dm_w[7:0] [6] 246/320: $2\mem_dm_w[7:0] [1] 247/320: $2\mem_dm_w[7:0] [3] 248/320: $2\mem_dm_w[7:0] [5] 249/320: $2\mem_di_w[31:0] [31] 250/320: $2\mem_di_w[31:0] [24] 251/320: $2\mem_di_w[31:0] [22] 252/320: $2\mem_di_w[31:0] [20] 253/320: $2\mem_di_w[31:0] [18] 254/320: $2\mem_di_w[31:0] [16] 255/320: $2\mem_di_w[31:0] [14] 256/320: $2\mem_di_w[31:0] [12] 257/320: $2\mem_di_w[31:0] [10] 258/320: $2\mem_di_w[31:0] [8] 259/320: $2\mem_di_w[31:0] [6] 260/320: $2\mem_di_w[31:0] [4] 261/320: $2\mem_di_w[31:0] [2] 262/320: $2\mem_di_w[31:0] [0] 263/320: $2\mem_di_w[31:0] [30] 264/320: $2\mem_di_w[31:0] [27] 265/320: $2\mem_di_w[31:0] [23] 266/320: $2\mem_di_w[31:0] [21] 267/320: $2\mem_di_w[31:0] [17] 268/320: $2\mem_di_w[31:0] [13] 269/320: $2\mem_di_w[31:0] [9] 270/320: $2\mem_di_w[31:0] [5] 271/320: $2\mem_di_w[31:0] [1] 272/320: $2\mem_di_w[31:0] [28] 273/320: $2\mem_di_w[31:0] [26] 274/320: $2\mem_di_w[31:0] [15] 275/320: $2\mem_di_w[31:0] [3] 276/320: $2\mem_di_w[31:0] [7] 277/320: $2\mem_di_w[31:0] [25] 278/320: $2\mem_di_w[31:0] [19] 279/320: $2\mem_di_w[31:0] [29] 280/320: $2\mem_di_w[31:0] [11] 281/320: $1\mem_dm_w[7:0] [7] 282/320: $1\mem_dm_w[7:0] [4] 283/320: $1\mem_dm_w[7:0] [2] 284/320: $1\mem_dm_w[7:0] [0] 285/320: $1\mem_dm_w[7:0] [6] 286/320: $1\mem_dm_w[7:0] [1] 287/320: $1\mem_dm_w[7:0] [3] 288/320: $1\mem_dm_w[7:0] [5] 289/320: $1\mem_di_w[31:0] [31] 290/320: $1\mem_di_w[31:0] [24] 291/320: $1\mem_di_w[31:0] [22] 292/320: $1\mem_di_w[31:0] [20] 293/320: $1\mem_di_w[31:0] [18] 294/320: $1\mem_di_w[31:0] [16] 295/320: $1\mem_di_w[31:0] [14] 296/320: $1\mem_di_w[31:0] [12] 297/320: $1\mem_di_w[31:0] [10] 298/320: $1\mem_di_w[31:0] [8] 299/320: $1\mem_di_w[31:0] [6] 300/320: $1\mem_di_w[31:0] [4] 301/320: $1\mem_di_w[31:0] [2] 302/320: $1\mem_di_w[31:0] [0] 303/320: $1\mem_di_w[31:0] [30] 304/320: $1\mem_di_w[31:0] [27] 305/320: $1\mem_di_w[31:0] [23] 306/320: $1\mem_di_w[31:0] [21] 307/320: $1\mem_di_w[31:0] [17] 308/320: $1\mem_di_w[31:0] [13] 309/320: $1\mem_di_w[31:0] [9] 310/320: $1\mem_di_w[31:0] [5] 311/320: $1\mem_di_w[31:0] [1] 312/320: $1\mem_di_w[31:0] [28] 313/320: $1\mem_di_w[31:0] [26] 314/320: $1\mem_di_w[31:0] [15] 315/320: $1\mem_di_w[31:0] [3] 316/320: $1\mem_di_w[31:0] [7] 317/320: $1\mem_di_w[31:0] [25] 318/320: $1\mem_di_w[31:0] [19] 319/320: $1\mem_di_w[31:0] [29] 320/320: $1\mem_di_w[31:0] [11] Creating decoders for process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4655'. 1/1: $0\addr_r[13:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:254$4638'. Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:247$4634'. 1/1: $0\rx_overflow[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:240$4632'. 1/1: $0\rx_rst[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4614'. 1/2: $0\bro_rden[0:0] 2/2: $0\bri_wren[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4613'. 1/2: $0\rx_mode[1:0] 2/2: $0\rx_enabled[0:0] Creating decoders for process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4605'. 1/2: $0\crx_clear[0:0] 2/2: $0\crx_wren[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4599'. 1/1: $0\tx_underflow[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4597'. 1/1: $0\tx_rst[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4574'. 1/2: $0\bto_rden[0:0] 2/2: $0\bti_wren[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4573'. 1/5: $0\tx_loopback[1:0] 2/5: $0\tx_alarm[0:0] 3/5: $0\tx_time_src[0:0] 4/5: $0\tx_mode[1:0] 5/5: $0\tx_enabled[0:0] Creating decoders for process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4565'. 1/2: $0\ctx_clear[0:0] 2/2: $0\ctx_wren[0:0] Creating decoders for process `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1719'. 1/1: $0\rst_48m_i[0:0] Creating decoders for process `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1714'. 1/1: $0\rst_cnt[3:0] Creating decoders for process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4560'. 1/2: $0\pg_lo[4:0] 2/2: $0\pg_hi[4:0] Creating decoders for process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:100$4552'. Creating decoders for process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4550'. 1/1: $0\mf_valid[0:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1654'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1652'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1650'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1648'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1646'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1644'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1642'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1640'. Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:302$1639'. 1/2: $0\boot_now[0:0] 2/2: $0\boot_sel[1:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1638'. 1/4: $0\pdm_e1[1][8:0] 2/4: $0\pdm_e1[0][8:0] 3/4: $0\pdm_clk[1][12:0] 4/4: $0\pdm_clk[0][12:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:183$1637'. 1/1: $0\e1_led[8:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:170$1636'. 1/2: $0\gpio_out[3:0] 2/2: $0\gpio_oe[3:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:130$1635'. 1/1: $0\wb_rdata[31:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1625'. 1/7: $0\bus_we_pdm_e1[1:0] [1] 2/7: $0\bus_we_pdm_e1[1:0] [0] 3/7: $0\bus_we_pdm_clk[1:0] [1] 4/7: $0\bus_we_pdm_clk[1:0] [0] 5/7: $0\bus_we_led[0:0] 6/7: $0\bus_we_gpio[0:0] 7/7: $0\bus_we_boot[0:0] Creating decoders for process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:104$1620'. Creating decoders for process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1607'. 1/1: $0\sr_go[0:0] Creating decoders for process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:77$1598'. Creating decoders for process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:65$1594'. Creating decoders for process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:55$1590'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1582'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1579'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1573'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1569'. 1/1: $0\len[10:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1563'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1556'. 1/2: $0\shift_last_byte[0:0] 2/2: $0\shift_data_crc[0:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1554'. 1/1: $0\shift_data[7:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1550'. 1/1: $0\shift_load[7:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1547'. 1/1: $0\shift_bit[3:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1535'. Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1534'. 1/1: $0\state[3:0] Creating decoders for process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1532'. 1/8: $8\state_nxt[3:0] 2/8: $7\state_nxt[3:0] 3/8: $6\state_nxt[3:0] 4/8: $5\state_nxt[3:0] 5/8: $4\state_nxt[3:0] 6/8: $3\state_nxt[3:0] 7/8: $2\state_nxt[3:0] 8/8: $1\state_nxt[3:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1531'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1529'. 1/1: $0\out_sym[1:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1522'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1517'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1507'. 1/2: $0\bs_now[0:0] 2/2: $0\bs_cnt[2:0] Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1504'. Creating decoders for process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1501'. 1/1: $0\state[2:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1497'. 1/1: $0\pkt_pid[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1489'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1486'. 1/1: $0\bd_length[10:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1480'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1479'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1476'. 1/1: $0\txpkt_pid[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1470'. 1/1: $0\cel_state_i[0:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1468'. Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1455'. 1/7: $0\bd_state[2:0] 2/7: $0\ep_data_toggle[0:0] 3/7: $0\ep_bd_idx_nxt[0:0] 4/7: $0\ep_bd_idx_cur[0:0] 5/7: $0\ep_bd_ctrl[0:0] 6/7: $0\ep_bd_dual[0:0] 7/7: $0\ep_type[2:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1452'. 1/1: $0\epfw_cap_dl[5:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1447'. 1/1: $0\epfw_state[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1443'. 1/4: $0\trans_cel[0:0] 2/4: $0\trans_dir[0:0] 3/4: $0\trans_endp[3:0] 4/4: $0\trans_is_setup[0:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1436'. 1/1: $0\rto_cnt[9:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1431'. 1/1: $0\evt[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1428'. 1/1: $0\mc_a_reg[3:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1419'. 1/1: $0\mc_pc_nxt[7:0] Creating decoders for process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1410'. 1/1: $0\mc_rst_n[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1407'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1398'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1396'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1393'. 1/1: $0\token_data[10:8] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1390'. 1/1: $0\token_data[7:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1373'. 1/5: $0\pid_is_handshake[0:0] 2/5: $0\pid_is_data[0:0] 3/5: $0\pid_is_token[0:0] 4/5: $0\pid_is_sof[0:0] 5/5: $0\pid[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1372'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1351'. 1/1: $0\pid_valid[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1347'. 1/2: $0\crc16_ok[0:0] 2/2: $0\crc5_ok[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1346'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1344'. 1/1: $0\crc_in_first[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1341'. 1/1: $0\bit_eop_ok[0:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1338'. 1/1: $0\bit_cnt[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1337'. 1/1: $0\data[7:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1329'. Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1328'. 1/1: $0\state[3:0] Creating decoders for process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1312'. 1/18: $18\state_nxt[3:0] 2/18: $17\state_nxt[3:0] 3/18: $16\state_nxt[3:0] 4/18: $15\state_nxt[3:0] 5/18: $14\state_nxt[3:0] 6/18: $13\state_nxt[3:0] 7/18: $12\state_nxt[3:0] 8/18: $11\state_nxt[3:0] 9/18: $10\state_nxt[3:0] 10/18: $9\state_nxt[3:0] 11/18: $8\state_nxt[3:0] 12/18: $7\state_nxt[3:0] 13/18: $6\state_nxt[3:0] 14/18: $5\state_nxt[3:0] 15/18: $4\state_nxt[3:0] 16/18: $3\state_nxt[3:0] 17/18: $2\state_nxt[3:0] 18/18: $1\state_nxt[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1311'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1309'. 1/1: $0\dec_bs_skip_1[0:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1307'. 1/1: $0\dec_rep_state_1[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1306'. 1/1: $0\dec_sync_state_1[3:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1305'. 1/1: $0\dec_eop_state_1[2:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1304'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1297'. 1/2: $0\dec_bit_1[0:0] 2/2: $0\dec_sym_1[1:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1290'. Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1289'. 1/1: $0\samp_cnt[2:0] Creating decoders for process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1279'. 1/1: $0\samp_active[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4549'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4540'. 1/1: $0\stage[4].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4538'. 1/1: $0\stage[4].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4529'. 1/1: $0\stage[3].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4527'. 1/1: $0\stage[3].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4518'. 1/1: $0\stage[2].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4516'. 1/1: $0\stage[2].l_data[6:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4507'. 1/1: $0\stage[1].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4505'. 1/1: $0\stage[1].l_data[6:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1275'. 1/1: $0\s_dout_3[15:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1273'. 1/1: $0\p_dout_3[15:0] Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1270'. Creating decoders for process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1262'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4503'. Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4494'. 1/1: $0\stage[4].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4492'. 1/1: $0\stage[4].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4483'. 1/1: $0\stage[3].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4481'. 1/1: $0\stage[3].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4472'. 1/1: $0\stage[2].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4470'. 1/1: $0\stage[2].l_data[8:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4461'. 1/1: $0\stage[1].l_valid[0:0] Creating decoders for process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4459'. 1/1: $0\stage[1].l_data[8:0] Creating decoders for process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:203$4448'. 1/1: $0\bd_crc_e[1:0] Creating decoders for process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:196$4442'. Creating decoders for process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:188$4438'. 1/1: $0\mf_valid[0:0] Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5379'. Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5374'. 1/1: $0\wb_rdata[15:0] Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5369'. Creating decoders for process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:106$5364'. Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4405'. Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4400'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4396'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4392'. 1/1: $0\cnt[1:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4384'. 1/2: $2\cnt_move[1:0] 2/2: $1\cnt_move[1:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1107'. 1/1: $0\out_stb[0:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1106'. 1/1: $0\dst[1:0] Creating decoders for process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1104'. 1/1: $0\src[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5355'. Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:163$5354'. 1/1: $0\tx_data_reg[0][7:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5349'. 1/1: $0\tx_pending[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:143$5348'. 1/1: $0\tx_addr_reg[0][15:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5347'. Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5342'. 1/1: $0\rx_pending[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5341'. 1/2: $0\rx_addr_reg[0][15:0] 2/2: $0\rx_data_reg[0][7:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5331'. 1/3: $1\t_done[3:0] 2/3: $1$bitselwrite$data$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$5290[3:0]$5335 3/3: $1$bitselwrite$mask$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$5289[3:0]$5334 Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. 1/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5284[15:0]$5327 2/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5283[15:0]$5326 3/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5282[15:0]$5324 4/20: $2$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5281[15:0]$5323 5/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5278[15:0]$5321 6/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5277[15:0]$5320 7/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5276[15:0]$5318 8/20: $2$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5275[15:0]$5317 9/20: $1\mux.j[31:0] 10/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5284[15:0]$5315 11/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5283[15:0]$5314 12/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5282[15:0]$5313 13/20: $1$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5281[15:0]$5312 14/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5278[15:0]$5311 15/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5277[15:0]$5310 16/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5276[15:0]$5309 17/20: $1$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5275[15:0]$5308 18/20: $0\wb_wdata_byte[7:0] 19/20: $0\wb_addr_lsb[1:0] 20/20: $0\wb_addr[13:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$5295'. 1/1: $0\t_chan[1:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5293'. 1/1: $0\t_busy[0:0] Creating decoders for process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5291'. 1/4: $4\t_nxt_chan[1:0] 2/4: $3\t_nxt_chan[1:0] 3/4: $2\t_nxt_chan[1:0] 4/4: $1\t_nxt_chan[1:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5264'. Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5263'. 1/1: $0\shift[9:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5260'. 1/1: $0\bit_cnt[4:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5256'. 1/1: $0\div_cnt[12:0] Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5252'. 1/1: $0\active[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4345'. 1/1: $0\rd_valid[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4339'. 1/1: $0\ram_rd_addr[8:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4337'. 1/1: $0\ram_wr_addr[8:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4328'. 1/1: $0\full[0:0] Creating decoders for process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4322'. 1/1: $0\level[9:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4321'. Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4316'. 1/2: $0\fall[0:0] 2/2: $0\rise[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4312'. 1/1: $0\state[0:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4308'. 1/1: $0\cnt[1:0] Creating decoders for process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4300'. 1/2: $2\cnt_move[1:0] 2/2: $1\cnt_move[1:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4299'. 1/1: $0\wb_now[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4290'. 1/3: $0\wb_req[0:0] 2/3: $0\wb_sel[1:0] 3/3: $0\rst_req[0:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4286'. 1/1: $0\timer[25:0] Creating decoders for process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4284'. 1/1: $0\armed[0:0] Creating decoders for process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:67$4280'. Creating decoders for process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4277'. 1/1: $0\acc[12:0] Creating decoders for process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:72$4276'. Creating decoders for process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4273'. 1/1: $0\acc[8:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. 1/82: $0\reg_next_pc[31:0] [31:2] 2/82: $0\reg_next_pc[31:0] [1:0] 3/82: $0\reg_pc[31:0] [1:0] 4/82: $18\next_irq_pending[2:2] 5/82: $17\next_irq_pending[2:2] 6/82: $16\next_irq_pending[2:2] 7/82: $15\next_irq_pending[2:2] 8/82: $14\next_irq_pending[2:2] 9/82: $13\next_irq_pending[2:2] 10/82: $4\next_irq_pending[31:0] [31:2] 11/82: $3\set_mem_do_rdata[0:0] 12/82: $4\next_irq_pending[31:0] [1] 13/82: $3\set_mem_do_wdata[0:0] 14/82: $4\next_irq_pending[31:0] [0] 15/82: $4\set_mem_do_rinst[0:0] 16/82: $3\set_mem_do_rinst[0:0] 17/82: $4\set_mem_do_wdata[0:0] 18/82: $11\next_irq_pending[1:1] 19/82: $10\next_irq_pending[1:1] 20/82: $9\next_irq_pending[1:1] 21/82: $4\set_mem_do_rdata[0:0] 22/82: $7\next_irq_pending[1:1] 23/82: $6\next_irq_pending[1:1] 24/82: $12\next_irq_pending[1:1] 25/82: $5\set_mem_do_rinst[0:0] 26/82: $8\next_irq_pending[1:1] 27/82: $5\next_irq_pending[31:0] 28/82: $3\current_pc[31:0] 29/82: $2\current_pc[31:0] 30/82: $2\set_mem_do_wdata[0:0] 31/82: $2\set_mem_do_rdata[0:0] 32/82: $2\set_mem_do_rinst[0:0] 33/82: $3\next_irq_pending[31:0] 34/82: $1\current_pc[31:0] 35/82: $1\set_mem_do_wdata[0:0] 36/82: $1\set_mem_do_rdata[0:0] 37/82: $1\set_mem_do_rinst[0:0] 38/82: $0\trace_data[35:0] 39/82: $2\next_irq_pending[0:0] 40/82: $1\next_irq_pending[0:0] 41/82: $0\count_instr[63:0] 42/82: $0\count_cycle[63:0] 43/82: $0\trace_valid[0:0] 44/82: $0\do_waitirq[0:0] 45/82: $0\decoder_pseudo_trigger[0:0] 46/82: $0\decoder_trigger[0:0] 47/82: $0\alu_wait_2[0:0] 48/82: $0\alu_wait[0:0] 49/82: $0\reg_out[31:0] 50/82: $0\reg_sh[4:0] 51/82: $0\trap[0:0] 52/82: $0\pcpi_timeout[0:0] 53/82: $0\latched_rd[4:0] 54/82: $0\latched_is_lb[0:0] 55/82: $0\latched_is_lh[0:0] 56/82: $0\latched_is_lu[0:0] 57/82: $0\latched_trace[0:0] 58/82: $0\latched_compr[0:0] 59/82: $0\latched_branch[0:0] 60/82: $0\latched_stalu[0:0] 61/82: $0\latched_store[0:0] 62/82: $0\irq_state[1:0] 63/82: $0\cpu_state[7:0] 64/82: $0\dbg_rs2val_valid[0:0] 65/82: $0\dbg_rs1val_valid[0:0] 66/82: $0\dbg_rs2val[31:0] 67/82: $0\dbg_rs1val[31:0] 68/82: $0\mem_do_wdata[0:0] 69/82: $0\mem_do_rdata[0:0] 70/82: $0\mem_do_rinst[0:0] 71/82: $0\mem_do_prefetch[0:0] 72/82: $0\mem_wordsize[1:0] 73/82: $0\irq_mask[31:0] 74/82: $0\irq_active[0:0] 75/82: $0\irq_delay[0:0] 76/82: $0\reg_op2[31:0] 77/82: $0\reg_op1[31:0] 78/82: $0\reg_pc[31:0] [31:2] 79/82: $19\next_irq_pending[2:2] 80/82: $0\eoi[31:0] 81/82: $0\pcpi_valid[0:0] 82/82: $0\timer[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4083'. Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4069'. 1/4: $2\cpuregs_write[0:0] 2/4: $2\cpuregs_wrdata[31:0] 3/4: $1\cpuregs_wrdata[31:0] 4/4: $1\cpuregs_write[0:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$4064'. 1/2: $2\clear_prefetched_high_word[0:0] 2/2: $1\clear_prefetched_high_word[0:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$4063'. Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4041'. 1/2: $1\alu_out[31:0] 2/2: $1\alu_out_0[0:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$4029'. 1/8: $8\dbg_ascii_state[127:0] 2/8: $7\dbg_ascii_state[127:0] 3/8: $6\dbg_ascii_state[127:0] 4/8: $5\dbg_ascii_state[127:0] 5/8: $4\dbg_ascii_state[127:0] 6/8: $3\dbg_ascii_state[127:0] 7/8: $2\dbg_ascii_state[127:0] 8/8: $1\dbg_ascii_state[127:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. 1/76: $0\decoded_rs1[4:0] [4] 2/76: $0\decoded_imm_uj[31:0] [10] 3/76: $0\decoded_imm_uj[31:0] [7] 4/76: $0\decoded_imm_uj[31:0] [6] 5/76: $0\decoded_imm_uj[31:0] [3:1] 6/76: $0\decoded_imm_uj[31:0] [5] 7/76: $0\decoded_imm_uj[31:0] [9:8] 8/76: $0\decoded_imm_uj[31:0] [31:20] 9/76: $0\decoded_imm_uj[31:0] [4] 10/76: $0\decoded_imm_uj[31:0] [11] 11/76: $0\decoded_imm_uj[31:0] [0] 12/76: $0\decoded_rs1[4:0] [3:0] 13/76: $0\is_lui_auipc_jal_jalr_addi_add_sub[0:0] 14/76: $0\is_alu_reg_reg[0:0] 15/76: $0\is_alu_reg_imm[0:0] 16/76: $0\is_beq_bne_blt_bge_bltu_bgeu[0:0] 17/76: $0\is_sll_srl_sra[0:0] 18/76: $0\is_sb_sh_sw[0:0] 19/76: $0\is_jalr_addi_slti_sltiu_xori_ori_andi[0:0] 20/76: $0\is_slli_srli_srai[0:0] 21/76: $0\is_lb_lh_lw_lbu_lhu[0:0] 22/76: $0\compressed_instr[0:0] 23/76: $0\is_compare[0:0] 24/76: $0\decoded_imm[31:0] 25/76: $0\decoded_rs2[4:0] 26/76: $0\decoded_imm_uj[31:0] [19:12] 27/76: $0\decoded_rd[4:0] 28/76: $0\instr_timer[0:0] 29/76: $0\instr_waitirq[0:0] 30/76: $0\instr_maskirq[0:0] 31/76: $0\instr_retirq[0:0] 32/76: $0\instr_setq[0:0] 33/76: $0\instr_getq[0:0] 34/76: $0\instr_ecall_ebreak[0:0] 35/76: $0\instr_rdinstrh[0:0] 36/76: $0\instr_rdinstr[0:0] 37/76: $0\instr_rdcycleh[0:0] 38/76: $0\instr_rdcycle[0:0] 39/76: $0\instr_and[0:0] 40/76: $0\instr_or[0:0] 41/76: $0\instr_sra[0:0] 42/76: $0\instr_srl[0:0] 43/76: $0\instr_xor[0:0] 44/76: $0\instr_sltu[0:0] 45/76: $0\instr_slt[0:0] 46/76: $0\instr_sll[0:0] 47/76: $0\instr_sub[0:0] 48/76: $0\instr_add[0:0] 49/76: $0\instr_srai[0:0] 50/76: $0\instr_srli[0:0] 51/76: $0\instr_slli[0:0] 52/76: $0\instr_andi[0:0] 53/76: $0\instr_ori[0:0] 54/76: $0\instr_xori[0:0] 55/76: $0\instr_sltiu[0:0] 56/76: $0\instr_slti[0:0] 57/76: $0\instr_addi[0:0] 58/76: $0\instr_sw[0:0] 59/76: $0\instr_sh[0:0] 60/76: $0\instr_sb[0:0] 61/76: $0\instr_lhu[0:0] 62/76: $0\instr_lbu[0:0] 63/76: $0\instr_lw[0:0] 64/76: $0\instr_lh[0:0] 65/76: $0\instr_lb[0:0] 66/76: $0\instr_bgeu[0:0] 67/76: $0\instr_bltu[0:0] 68/76: $0\instr_bge[0:0] 69/76: $0\instr_blt[0:0] 70/76: $0\instr_bne[0:0] 71/76: $0\instr_beq[0:0] 72/76: $0\instr_jalr[0:0] 73/76: $0\instr_jal[0:0] 74/76: $0\instr_auipc[0:0] 75/76: $0\instr_lui[0:0] 76/76: $0\pcpi_insn[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3767'. 1/13: $3\dbg_insn_opcode[31:0] 2/13: $2\dbg_insn_rd[4:0] 3/13: $2\dbg_insn_rs2[4:0] 4/13: $2\dbg_insn_rs1[4:0] 5/13: $2\dbg_insn_opcode[31:0] 6/13: $2\dbg_insn_imm[31:0] 7/13: $2\dbg_ascii_instr[63:0] 8/13: $1\dbg_insn_rd[4:0] 9/13: $1\dbg_insn_rs2[4:0] 10/13: $1\dbg_insn_rs1[4:0] 11/13: $1\dbg_insn_imm[31:0] 12/13: $1\dbg_ascii_instr[63:0] 13/13: $1\dbg_insn_opcode[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. 1/8: $0\cached_insn_rd[4:0] 2/8: $0\cached_insn_rs2[4:0] 3/8: $0\cached_insn_rs1[4:0] 4/8: $0\cached_insn_opcode[31:0] 5/8: $0\cached_insn_imm[31:0] 6/8: $0\cached_ascii_instr[63:0] 7/8: $0\dbg_valid_insn[0:0] 8/8: $0\dbg_insn_addr[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3762'. 1/47: $47\new_ascii_instr[63:0] 2/47: $46\new_ascii_instr[63:0] 3/47: $45\new_ascii_instr[63:0] 4/47: $44\new_ascii_instr[63:0] 5/47: $43\new_ascii_instr[63:0] 6/47: $42\new_ascii_instr[63:0] 7/47: $41\new_ascii_instr[63:0] 8/47: $40\new_ascii_instr[63:0] 9/47: $39\new_ascii_instr[63:0] 10/47: $38\new_ascii_instr[63:0] 11/47: $37\new_ascii_instr[63:0] 12/47: $36\new_ascii_instr[63:0] 13/47: $35\new_ascii_instr[63:0] 14/47: $34\new_ascii_instr[63:0] 15/47: $33\new_ascii_instr[63:0] 16/47: $32\new_ascii_instr[63:0] 17/47: $31\new_ascii_instr[63:0] 18/47: $30\new_ascii_instr[63:0] 19/47: $29\new_ascii_instr[63:0] 20/47: $28\new_ascii_instr[63:0] 21/47: $27\new_ascii_instr[63:0] 22/47: $26\new_ascii_instr[63:0] 23/47: $25\new_ascii_instr[63:0] 24/47: $24\new_ascii_instr[63:0] 25/47: $23\new_ascii_instr[63:0] 26/47: $22\new_ascii_instr[63:0] 27/47: $21\new_ascii_instr[63:0] 28/47: $20\new_ascii_instr[63:0] 29/47: $19\new_ascii_instr[63:0] 30/47: $18\new_ascii_instr[63:0] 31/47: $17\new_ascii_instr[63:0] 32/47: $16\new_ascii_instr[63:0] 33/47: $15\new_ascii_instr[63:0] 34/47: $14\new_ascii_instr[63:0] 35/47: $13\new_ascii_instr[63:0] 36/47: $12\new_ascii_instr[63:0] 37/47: $11\new_ascii_instr[63:0] 38/47: $10\new_ascii_instr[63:0] 39/47: $9\new_ascii_instr[63:0] 40/47: $8\new_ascii_instr[63:0] 41/47: $7\new_ascii_instr[63:0] 42/47: $6\new_ascii_instr[63:0] 43/47: $5\new_ascii_instr[63:0] 44/47: $4\new_ascii_instr[63:0] 45/47: $3\new_ascii_instr[63:0] 46/47: $2\new_ascii_instr[63:0] 47/47: $1\new_ascii_instr[63:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3738'. 1/9: $0\mem_16bit_buffer[15:0] 2/9: $0\prefetched_high_word[0:0] 3/9: $0\mem_la_secondword[0:0] 4/9: $0\mem_state[1:0] 5/9: $0\mem_wstrb[3:0] 6/9: $0\mem_wdata[31:0] 7/9: $0\mem_instr[0:0] 8/9: $0\mem_valid[0:0] 9/9: $0\mem_addr[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4262'. Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3700'. 1/9: $0\mem_rdata_q[31:0] [31] 2/9: $0\mem_rdata_q[31:0] [7] 3/9: $0\mem_rdata_q[31:0] [24:20] 4/9: $0\mem_rdata_q[31:0] [19:15] 5/9: $0\mem_rdata_q[31:0] [6:0] 6/9: $0\mem_rdata_q[31:0] [14:12] 7/9: $0\mem_rdata_q[31:0] [11:8] 8/9: $0\mem_rdata_q[31:0] [30:25] 9/9: $0\next_insn_opcode[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3697'. 1/5: $3\mem_rdata_word[31:0] 2/5: $2\mem_rdata_word[31:0] 3/5: $1\mem_rdata_word[31:0] 4/5: $1\mem_la_wstrb[3:0] 5/5: $1\mem_la_wdata[31:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3692'. 1/2: $0\last_mem_valid[0:0] 2/2: $0\mem_la_firstword_reg[0:0] Creating decoders for process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3618'. 1/2: $1\pcpi_int_rd[31:0] 2/2: $1\pcpi_int_wr[0:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5246'. Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5245'. 1/1: $0\shift[8:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5242'. 1/1: $0\bit_cnt[4:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5238'. 1/1: $0\div_cnt[12:0] Creating decoders for process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5234'. 1/1: $0\active[0:0] Creating decoders for process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. 1/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_EN[31:0]$3511 2/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_DATA[31:0]$3510 3/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_ADDR[7:0]$3509 4/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN[31:0]$3514 5/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_DATA[31:0]$3513 6/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_ADDR[7:0]$3512 7/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN[31:0]$3517 8/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_DATA[31:0]$3516 9/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_ADDR[7:0]$3515 10/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN[31:0]$3520 11/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_DATA[31:0]$3519 12/12: $0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_ADDR[7:0]$3518 Creating decoders for process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3499'. 1/1: $0\led_ctrl[4:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3493'. 1/1: $0\evt_cnt[3:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3488'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3486'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3485'. 1/1: $0\pad_pu[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3481'. 1/1: $0\rst_pending[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3477'. 1/1: $0\timeout_reset[19:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3473'. 1/1: $0\timeout_suspend[19:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3459'. 1/1: $0\eps_bus_ack_wait[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3456'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3446'. 1/3: $0\eps_bus_req[0:0] 2/3: $0\eps_bus_write[0:0] 3/3: $0\eps_bus_read[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3497'. Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3444'. 1/4: $0\cr_addr[6:0] 2/4: $0\cr_addr_chk[0:0] 3/4: $0\cr_cel_ena[0:0] 4/4: $0\cr_pu_ena[0:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3440'. 1/2: $2\csr_bus_dout[15:0] 2/2: $1\csr_bus_dout[15:0] Creating decoders for process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3422'. 1/7: $0\ir_bus_we[0:0] 2/7: $0\evt_rd_ack[0:0] 3/7: $0\sof_clear[0:0] 4/7: $0\rst_clear[0:0] 5/7: $0\cel_rel[0:0] 6/7: $0\cr_bus_we[0:0] 7/7: $0\csr_bus_req[0:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3418'. 1/1: $0\m_cyc_i[0:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3414'. Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3411'. 1/1: $0\s_rdata[15:0] Creating decoders for process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3410'. 1/1: $0\m_rdata_i[15:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5230'. Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5229'. Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5221'. 1/1: $0\sda_oe[0:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5218'. 1/1: $0\scl_oe[0:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5214'. 1/1: $0\data_reg[8:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5210'. 1/1: $0\bit_cnt[3:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5206'. 1/1: $0\cyc_cnt[4:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:121$5205'. 1/1: $0\cmd_cur[1:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5200'. 1/7: $7\state_nxt[2:0] 2/7: $6\state_nxt[2:0] 3/7: $5\state_nxt[2:0] 4/7: $4\state_nxt[2:0] 5/7: $3\state_nxt[2:0] 6/7: $2\state_nxt[2:0] 7/7: $1\state_nxt[2:0] Creating decoders for process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5199'. 1/1: $0\state[2:0] Creating decoders for process `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5198'. 1/1: $0\out[7:0] Creating decoders for process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3327'. Creating decoders for process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3325'. Creating decoders for process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3323'. Creating decoders for process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3322'. 1/1: $0\pb_rst_n[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3308'. 1/1: $0\uart_div[11:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3306'. 1/1: $0\ub_rdata[31:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3296'. 1/1: $0\ub_ack[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3279'. 1/4: $0\ub_wr_div[0:0] 2/4: $0\ub_wr_data[0:0] 3/4: $0\ub_rd_ctrl[0:0] 4/4: $0\ub_rd_data[0:0] Creating decoders for process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3274'. 1/1: $0\urf_overflow[0:0] Creating decoders for process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3269'. 1/1: $0\wb_rdata[31:0] Creating decoders for process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:85$3261'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3259'. 1/4: $0\srio_rclk_oe[0:0] 2/4: $0\srio_rclk_o[0:0] 3/4: $0\srio_dat_o[0:0] 4/4: $0\srio_clk_o[0:0] Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:279$3258'. 1/1: $0\shift_data[7:0] Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:270$3246'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:262$3239'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:243$3233'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:227$3226'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:214$3220'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:206$3219'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:197$3217'. Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3205'. 1/9: $9\state_nxt[2:0] 2/9: $8\state_nxt[2:0] 3/9: $7\state_nxt[2:0] 4/9: $6\state_nxt[2:0] 5/9: $5\state_nxt[2:0] 6/9: $4\state_nxt[2:0] 7/9: $3\state_nxt[2:0] 8/9: $2\state_nxt[2:0] 9/9: $1\state_nxt[2:0] Creating decoders for process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3204'. 1/1: $0\state[2:0] Creating decoders for process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$447'. 1/9: $0\d_neg[3:0] [3] 2/9: $0\d_pos[3:0] [3] 3/9: $0\d_neg[3:0] [2:1] 4/9: $0\d_neg[3:0] [0] 5/9: $0\d_pos[3:0] [0] 6/9: $0\zcnt[1:0] 7/9: $0\d_pos[3:0] [2:1] 8/9: $0\vstate[0:0] 9/9: $0\pstate[0:0] Creating decoders for process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:41$446'. Creating decoders for process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$443'. 1/2: $0\pstate[0:0] 2/2: $0\data[3:0] Creating decoders for process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:37$438'. Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:253$252'. 1/2: $0\out_valid[0:0] 2/2: $0\out_bit[0:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:241$250'. 1/1: $0\crc_smf[3:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:229$249'. Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:209$237'. 1/3: $0\shift_at_crc[0:0] 2/3: $0\shift_at_last[0:0] 3/3: $0\shift_at_first[0:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:199$234'. 1/1: $0\shift_data[7:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:192$230'. 1/1: $0\bit_cnt[3:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:167$227'. 1/1: $0\shift_data_nxt[7:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:148$223'. 1/1: $0\fetch_done[0:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:144$222'. Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$218'. 1/2: $0\in_mf_last[0:0] 2/2: $0\in_mf_first[0:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$215'. 1/3: $0\fetch_ts_is31[0:0] 2/3: $0\fetch_ts_is0[0:0] 3/3: $0\fetch_ts[4:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:113$213'. 1/1: $0\fetch_frame[3:0] Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:103$209'. Creating decoders for process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:97$205'. 1/1: $0\tick_cnt[4:0] Creating decoders for process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$168'. 1/3: $0\out_stb[0:0] 2/3: $0\out_lo[0:0] 3/3: $0\out_hi[0:0] Creating decoders for process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$149'. 1/2: $0\cnt_lo[1:0] 2/2: $0\cnt_hi[1:0] Creating decoders for process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:39$148'. Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$146'. 1/1: $0\aligned[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$140'. 1/7: $0\out_last[0:0] 2/7: $0\out_first[0:0] 3/7: $0\out_ts_is0[0:0] 4/7: $0\out_ts[4:0] 5/7: $0\out_frame[3:0] 6/7: $0\out_data[7:0] 7/7: $0\out_valid[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:357$132'. Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$114'. 1/4: $0\ec_mfa[1:0] 2/4: $0\ec_crc[1:0] 3/4: $0\ec_nfas[1:0] 4/4: $0\ec_fas[1:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$94'. 1/4: $0\ed_mfa[0:0] 2/4: $0\ep_mfa[0:0] 3/4: $0\ed_crc[0:0] 4/4: $0\ep_crc[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$72'. 1/4: $0\ed_nfas[0:0] 2/4: $0\ep_nfas[0:0] 3/4: $0\ed_fas[0:0] 4/4: $0\ep_fas[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$71'. 1/1: $0\crc_smf[3:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$60'. 1/3: $0\ts0_msbs_match_crc[0:0] 2/3: $0\ts0_msbs_match_mf[0:0] 3/3: $0\ts0_msbs[15:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$56'. 1/1: $0\mfa_timeout[6:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$52'. 1/1: $0\fas_pos[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$42'. 1/5: $0\frame_mf_last[0:0] 2/5: $0\frame_mf_first[0:0] 3/5: $0\frame_smf_last[0:0] 4/5: $0\frame_smf_first[0:0] 5/5: $0\frame[3:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$38'. 1/3: $0\ts_is_ts31[0:0] 2/3: $0\ts_is_ts0[0:0] 3/3: $0\ts[4:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$34'. 1/3: $0\bit_last[0:0] 2/3: $0\bit_first[0:0] 3/3: $0\bit[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$26'. 1/1: $0\fsm_state_nxt[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$24'. 1/1: $0\fsm_state[2:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$21'. 1/1: $0\data_match_fas[0:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$20'. 1/1: $0\data[7:0] Creating decoders for process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$19'. 1/1: $0\strobe[0:0] Creating decoders for process `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:39$17'. 1/1: $0\cnt[5:0] Creating decoders for process `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:33$15'. 1/1: $0\enabled[0:0] Creating decoders for process `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$13'. 1/1: $0\state[3:0] 75.3.7. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\cnt_move' from process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5174'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\sel_nxt' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5141'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\prio.i' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5141'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_addr' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5119'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_wdata' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5119'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux_wmsk' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5119'. No latch inferred for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\mux.i' from process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5119'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\sel_nxt' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5089'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\prio.i' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5089'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_addr' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5073'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_wdata' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5073'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux_wmsk' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5073'. No latch inferred for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\mux.i' from process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5073'. No latch inferred for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\state_nxt' from process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$5015'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4994$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5006'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4997$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5006'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:92$4997$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5006'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4993$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5002'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4996$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5002'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:91$4996$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5002'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4992$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4998'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4995$\bitrev16' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4998'. No latch inferred for signal `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$func$\bitrev16$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:81$4995$\sig' from process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4998'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5527$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5569'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5536$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5569'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5536$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5569'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5526$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5565'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5535$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5565'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5535$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5565'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5525$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5561'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5534$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5561'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5534$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5561'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5524$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5557'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5533$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5557'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5533$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5557'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5523$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5553'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5532$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5553'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5532$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5553'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5522$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5549'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5531$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5549'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5531$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5549'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5521$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5545'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5530$\ram_wr_map8' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5545'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:265$5530$\wdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5545'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5520$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5541'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5529$\ram_rd_map2' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5541'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_rd_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:252$5529$\rdata' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5541'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5519$\ram_wr_shuffle_32' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5537'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5528$\ram_wr_shuffle_32' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5537'. No latch inferred for signal `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$func$\ram_wr_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:220$5528$\src' from process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5537'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5472$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5514'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5481$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5514'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5481$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5514'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5471$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5510'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5480$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5510'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5480$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5510'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5470$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5506'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5479$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5506'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5479$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5506'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5469$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5502'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5478$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5502'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5478$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5502'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5468$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5498'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5477$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5498'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5477$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5498'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5467$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5494'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5476$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5494'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5476$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5494'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5466$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5490'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5475$\ram_wr_map2' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5490'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_wr_map2$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:261$5475$\wdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5490'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5465$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5486'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5474$\ram_rd_map8' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5486'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_map8$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:256$5474$\rdata' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5486'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5464$\ram_rd_shuffle_32' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5482'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5473$\ram_rd_shuffle_32' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5482'. No latch inferred for signal `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$func$\ram_rd_shuffle_32$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:211$5473$\src' from process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5482'. No latch inferred for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdata_or' from process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5423'. No latch inferred for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_or.i' from process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5423'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_do_m[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4812'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4812'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di[1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4812'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm[0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4812'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm[1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4812'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\rd_data' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.n' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.x' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656'. No latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\map.o' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656'. Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$16038 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$16153 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [2]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$16316 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [3]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$16527 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [4]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$16738 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [5]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$16949 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [6]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$17160 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [7]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$17371 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [8]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$17582 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [9]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$17793 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [10]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$18004 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [11]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$18215 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [12]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$18426 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [13]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$18637 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [14]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$18848 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [15]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$19059 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [16]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$19270 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [17]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$19481 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [18]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$19692 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [19]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$19903 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [20]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$20114 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [21]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$20325 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [22]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$20536 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [23]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$20747 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [24]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$20958 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [25]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$21169 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [26]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$21380 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [27]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$21591 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [28]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$21802 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [29]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$22013 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [30]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$22224 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_di_w [31]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$22435 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [0]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$22502 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [1]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$22569 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [2]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$22636 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [3]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$22703 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [4]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$22770 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [5]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$22837 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [6]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$22904 Latch inferred for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\mem_dm_w [7]' from process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656': $auto$proc_dlatch.cc:430:proc_dlatch$22971 No latch inferred for signal `\misc.$mem2bits$\pdm_e1$/build/gateware/icE1usb/rtl/misc.v:293$1619' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1654'. No latch inferred for signal `\misc.$mem2bits$\pdm_e1$/build/gateware/icE1usb/rtl/misc.v:293$1618' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1652'. No latch inferred for signal `\misc.$mem2bits$\pdm_e1$/build/gateware/icE1usb/rtl/misc.v:292$1617' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1650'. No latch inferred for signal `\misc.$mem2bits$\pdm_e1$/build/gateware/icE1usb/rtl/misc.v:292$1616' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1648'. No latch inferred for signal `\misc.$mem2bits$\pdm_clk$/build/gateware/icE1usb/rtl/misc.v:281$1615' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1646'. No latch inferred for signal `\misc.$mem2bits$\pdm_clk$/build/gateware/icE1usb/rtl/misc.v:281$1614' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1644'. No latch inferred for signal `\misc.$mem2bits$\pdm_clk$/build/gateware/icE1usb/rtl/misc.v:280$1613' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1642'. No latch inferred for signal `\misc.$mem2bits$\pdm_clk$/build/gateware/icE1usb/rtl/misc.v:280$1612' from process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1640'. No latch inferred for signal `\led_blinker.\led' from process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:77$1598'. No latch inferred for signal `\led_blinker.\led_state_proc.i' from process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:77$1598'. No latch inferred for signal `\usb_tx_pkt.\shift_load' from process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1550'. No latch inferred for signal `\usb_tx_pkt.\state_nxt' from process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1532'. No latch inferred for signal `\usb_rx_pkt.\state_nxt' from process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1312'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[0]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4549'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[1]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4549'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[2]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4549'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[3]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4549'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[4]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4549'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\data[5]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4549'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[0]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4503'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[1]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4503'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[2]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4503'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[3]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4503'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[4]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4503'. No latch inferred for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\data[5]' from process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4503'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\bus_rdata_rx[1]' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5379'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\bus_rdata_tx[1]' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5379'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\bus_rdata' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5369'. No latch inferred for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\rdata_or.j' from process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5369'. No latch inferred for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\cnt_move' from process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4384'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_done' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5331'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$bitselwrite$mask$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$5289' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5331'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$bitselwrite$data$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:268$5290' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5331'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_nxt_busy' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5291'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_nxt_chan' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5291'. No latch inferred for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\next_sel.j' from process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5291'. No latch inferred for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\cnt_move' from process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4300'. No latch inferred for signal `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.\dither' from process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:72$4276'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpuregs_rs1' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4083'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpuregs_rs2' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4083'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_rs' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4083'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpuregs_write' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4069'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpuregs_wrdata' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4069'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\clear_prefetched_high_word' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$4064'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_out' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4041'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_out_0' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4041'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_ascii_state' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$4029'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_opcode' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3767'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_ascii_instr' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3767'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_imm' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3767'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_rs1' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3767'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_rs2' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3767'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_rd' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3767'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\new_ascii_instr' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3762'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_la_wdata' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3697'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_la_wstrb' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3697'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_rdata_word' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3697'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_int_wr' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3618'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_int_rd' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3618'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_int_wait' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3618'. No latch inferred for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_int_ready' from process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3618'. No latch inferred for signal `$paramod\usb\EPDW=32.\irq' from process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3497'. No latch inferred for signal `$paramod\usb\EPDW=32.\csr_bus_dout' from process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3440'. No latch inferred for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\scl_ir' from process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5230'. No latch inferred for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\to_cnt' from process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5229'. No latch inferred for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\to_latch' from process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5229'. No latch inferred for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\state_nxt' from process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5200'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\wb_rdata[3] [31:16]' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3327'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\wb_rdata[5]' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3327'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\wb_rdata[6]' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3327'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\wb_rdata[7] [31:16]' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3327'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$mem2bits$\wb_rdata$/build/gateware/common/rtl/soc_base.v:499$3321' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3325'. No latch inferred for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$mem2bits$\wb_rdata$/build/gateware/common/rtl/soc_base.v:402$3320' from process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3323'. No latch inferred for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\state_nxt' from process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3205'. No latch inferred for signal `\e1_rx_deframer.\fsm_state_nxt' from process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$26'. 75.3.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3064'. created $adff cell `$procdff$22972' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3057'. created $dff cell `$procdff$22973' with negative edge clock. Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3053'. created $adff cell `$procdff$22974' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3046'. created $dff cell `$procdff$22975' with negative edge clock. Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3043'. created $adff cell `$procdff$22976' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3040'. created $dff cell `$procdff$22977' with negative edge clock. Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3037'. created $adff cell `$procdff$22978' with negative edge clock and positive level reset. Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3034'. created $dff cell `$procdff$22979' with negative edge clock. Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$3032'. created $dff cell `$procdff$22980' with negative edge clock. Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$3030'. created $dff cell `$procdff$22981' with negative edge clock. Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3026'. created $adff cell `$procdff$22982' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3019'. created $dff cell `$procdff$22983' with positive edge clock. Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3015'. created $adff cell `$procdff$22984' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3008'. created $dff cell `$procdff$22985' with positive edge clock. Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$3005'. created $adff cell `$procdff$22986' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$3002'. created $dff cell `$procdff$22987' with positive edge clock. Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2999'. created $adff cell `$procdff$22988' with positive edge clock and positive level reset. Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2996'. created $dff cell `$procdff$22989' with positive edge clock. Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2994'. created $dff cell `$procdff$22990' with positive edge clock. Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2992'. created $dff cell `$procdff$22991' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\sync' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$5195'. created $dff cell `$procdff$22992' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\rise' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5190'. created $dff cell `$procdff$22993' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\fall' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5190'. created $dff cell `$procdff$22994' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\state' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5186'. created $dff cell `$procdff$22995' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.\cnt' using process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5182'. created $dff cell `$procdff$22996' with positive edge clock. Creating register for signal `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.\ack_i' using process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5171'. created $adff cell `$procdff$22997' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\sel' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5150'. created $adff cell `$procdff$22998' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\busy' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5150'. created $adff cell `$procdff$22999' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_addr' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5138'. created $adff cell `$procdff$23000' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_wdata' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5138'. created $adff cell `$procdff$23001' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_we' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5138'. created $adff cell `$procdff$23002' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=3\DW=32\AW=14.\m_wmsk' using process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5138'. created $adff cell `$procdff$23003' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_epbuf\AW=9\DW=32.\ack_i' using process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$5107'. created $adff cell `$procdff$23004' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\sel' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5096'. created $adff cell `$procdff$23005' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\busy' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5096'. created $adff cell `$procdff$23006' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_addr' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5086'. created $adff cell `$procdff$23007' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_wdata' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5086'. created $adff cell `$procdff$23008' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_we' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5086'. created $adff cell `$procdff$23009' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_arbiter\N=2\DW=32\AW=9.\m_wmsk' using process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5086'. created $adff cell `$procdff$23010' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_do_write' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5054'. created $adff cell `$procdff$23011' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_do_read' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5054'. created $adff cell `$procdff$23012' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\ctl_ack_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5054'. created $adff cell `$procdff$23013' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\dir' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$5050'. created $dff cell `$procdff$23014' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\len' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$5047'. created $dff cell `$procdff$23015' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\m1_addr_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$5037'. created $dff cell `$procdff$23016' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\m0_addr_i' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$5033'. created $dff cell `$procdff$23017' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\data_reg' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$5031'. created $dff cell `$procdff$23018' with positive edge clock. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\state' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$5014'. created $adff cell `$procdff$23019' with positive edge clock and positive level reset. Creating register for signal `$paramod\wb_dma\A0W=14\A1W=9\DW=32.\go' using process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$5010'. created $adff cell `$procdff$23020' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.\state' using process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4968'. created $dff cell `$procdff$23021' with positive edge clock. Creating register for signal `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.\state' using process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4955'. created $dff cell `$procdff$23022' with positive edge clock. Creating register for signal `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.\dp_state' using process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4931'. created $adff cell `$procdff$23023' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.\dn_state' using process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4931'. created $adff cell `$procdff$23024' with positive edge clock and positive level reset. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.\rd_data' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5458'. created $dff cell `$procdff$23025' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_ADDR' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5458'. created $dff cell `$procdff$23026' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_DATA' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5458'. created $dff cell `$procdff$23027' with positive edge clock. Creating register for signal `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN' using process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5458'. created $dff cell `$procdff$23028' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdata_reg' using process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5452'. created $dff cell `$procdff$23029' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\wb_rdy_reg' using process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5450'. created $dff cell `$procdff$23030' with positive edge clock. Creating register for signal `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.\ram_rdy' using process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5420'. created $dff cell `$procdff$23031' with positive edge clock. Creating register for signal `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.\addr_r' using process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4655'. created $dff cell `$procdff$23032' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\tx_crc_e_auto' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:254$4638'. created $dff cell `$procdff$23033' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\rx_overflow' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:247$4634'. created $adff cell `$procdff$23034' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\rx_rst' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:240$4632'. created $adff cell `$procdff$23035' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\bri_wren' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4614'. created $dff cell `$procdff$23036' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\bro_rden' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4614'. created $dff cell `$procdff$23037' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\rx_enabled' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4613'. created $adff cell `$procdff$23038' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\rx_mode' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4613'. created $adff cell `$procdff$23039' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\crx_wren' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4605'. created $dff cell `$procdff$23040' with positive edge clock. Creating register for signal `$paramod\e1_wb_rx\LIU=0\MFW=7.\crx_clear' using process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4605'. created $dff cell `$procdff$23041' with positive edge clock. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_underflow' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4599'. created $adff cell `$procdff$23042' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_rst' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4597'. created $adff cell `$procdff$23043' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\bti_wren' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4574'. created $dff cell `$procdff$23044' with positive edge clock. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\bto_rden' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4574'. created $dff cell `$procdff$23045' with positive edge clock. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_enabled' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4573'. created $adff cell `$procdff$23046' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_mode' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4573'. created $adff cell `$procdff$23047' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_time_src' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4573'. created $adff cell `$procdff$23048' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_alarm' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4573'. created $adff cell `$procdff$23049' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\tx_loopback' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4573'. created $adff cell `$procdff$23050' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\ctx_wren' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4565'. created $dff cell `$procdff$23051' with positive edge clock. Creating register for signal `$paramod\e1_wb_tx\LIU=0\MFW=7.\ctx_clear' using process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4565'. created $dff cell `$procdff$23052' with positive edge clock. Creating register for signal `\sysmgr.\rst_48m_i' using process `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1719'. created $adff cell `$procdff$23053' with positive edge clock and positive level reset. Creating register for signal `\sysmgr.\rst_cnt' using process `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1714'. created $adff cell `$procdff$23054' with positive edge clock and negative level reset. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\pg_hi' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4560'. created $dff cell `$procdff$23055' with positive edge clock. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\pg_lo' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4560'. created $dff cell `$procdff$23056' with positive edge clock. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\bd_done' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:100$4552'. created $dff cell `$procdff$23057' with positive edge clock. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\bd_miss' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:100$4552'. created $dff cell `$procdff$23058' with positive edge clock. Creating register for signal `$paramod\e1_tx\LIU=0\MFW=7.\mf_valid' using process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4550'. created $adff cell `$procdff$23059' with positive edge clock and positive level reset. Creating register for signal `\misc.\boot_sel' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:302$1639'. created $adff cell `$procdff$23060' with positive edge clock and positive level reset. Creating register for signal `\misc.\boot_now' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:302$1639'. created $adff cell `$procdff$23061' with positive edge clock and positive level reset. Creating register for signal `\misc.\pdm_clk[0]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1638'. created $adff cell `$procdff$23062' with positive edge clock and positive level reset. Creating register for signal `\misc.\pdm_clk[1]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1638'. created $adff cell `$procdff$23063' with positive edge clock and positive level reset. Creating register for signal `\misc.\pdm_e1[0]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1638'. created $adff cell `$procdff$23064' with positive edge clock and positive level reset. Creating register for signal `\misc.\pdm_e1[1]' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1638'. created $adff cell `$procdff$23065' with positive edge clock and positive level reset. Creating register for signal `\misc.\e1_led' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:183$1637'. created $adff cell `$procdff$23066' with positive edge clock and positive level reset. Creating register for signal `\misc.\gpio_oe' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:170$1636'. created $adff cell `$procdff$23067' with positive edge clock and positive level reset. Creating register for signal `\misc.\gpio_out' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:170$1636'. created $adff cell `$procdff$23068' with positive edge clock and positive level reset. Creating register for signal `\misc.\wb_rdata' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:130$1635'. created $dff cell `$procdff$23069' with positive edge clock. Creating register for signal `\misc.\bus_we_boot' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1625'. created $dff cell `$procdff$23070' with positive edge clock. Creating register for signal `\misc.\bus_we_gpio' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1625'. created $dff cell `$procdff$23071' with positive edge clock. Creating register for signal `\misc.\bus_we_led' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1625'. created $dff cell `$procdff$23072' with positive edge clock. Creating register for signal `\misc.\bus_we_pdm_clk' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1625'. created $dff cell `$procdff$23073' with positive edge clock. Creating register for signal `\misc.\bus_we_pdm_e1' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1625'. created $dff cell `$procdff$23074' with positive edge clock. Creating register for signal `\misc.\wb_ack' using process `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:104$1620'. created $dff cell `$procdff$23075' with positive edge clock. Creating register for signal `\led_blinker.\sr_go' using process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1607'. created $adff cell `$procdff$23076' with positive edge clock and positive level reset. Creating register for signal `\led_blinker.\cycle' using process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:65$1594'. created $dff cell `$procdff$23077' with positive edge clock. Creating register for signal `\led_blinker.\tick_cnt' using process `\led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:55$1590'. created $dff cell `$procdff$23078' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pkt_done' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1582'. created $dff cell `$procdff$23079' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pkt_data_ack' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1582'. created $dff cell `$procdff$23080' with positive edge clock. Creating register for signal `\usb_tx_pkt.\ll_start' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1579'. created $dff cell `$procdff$23081' with positive edge clock. Creating register for signal `\usb_tx_pkt.\crc_in_first' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1573'. created $dff cell `$procdff$23082' with positive edge clock. Creating register for signal `\usb_tx_pkt.\len' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1569'. created $dff cell `$procdff$23083' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_new_bit' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1563'. created $dff cell `$procdff$23084' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_data_crc' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1556'. created $dff cell `$procdff$23085' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_last_byte' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1556'. created $dff cell `$procdff$23086' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_data' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1554'. created $dff cell `$procdff$23087' with positive edge clock. Creating register for signal `\usb_tx_pkt.\shift_bit' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1547'. created $dff cell `$procdff$23088' with positive edge clock. Creating register for signal `\usb_tx_pkt.\pid_is_handshake' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1535'. created $dff cell `$procdff$23089' with positive edge clock. Creating register for signal `\usb_tx_pkt.\state' using process `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1534'. created $adff cell `$procdff$23090' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\out_active' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1531'. created $dff cell `$procdff$23091' with positive edge clock. Creating register for signal `\usb_tx_ll.\out_sym' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1529'. created $adff cell `$procdff$23092' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\ll_ack' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1522'. created $dff cell `$procdff$23093' with positive edge clock. Creating register for signal `\usb_tx_ll.\lvl_prev' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1517'. created $dff cell `$procdff$23094' with positive edge clock. Creating register for signal `\usb_tx_ll.\bs_cnt' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1507'. created $adff cell `$procdff$23095' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\bs_now' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1507'. created $adff cell `$procdff$23096' with positive edge clock and positive level reset. Creating register for signal `\usb_tx_ll.\br_cnt' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1504'. created $dff cell `$procdff$23097' with positive edge clock. Creating register for signal `\usb_tx_ll.\state' using process `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1501'. created $adff cell `$procdff$23098' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\pkt_pid' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1497'. created $dff cell `$procdff$23099' with positive edge clock. Creating register for signal `\usb_trans.\xfer_length' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1489'. created $dff cell `$procdff$23100' with positive edge clock. Creating register for signal `\usb_trans.\bd_length' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1486'. created $dff cell `$procdff$23101' with positive edge clock. Creating register for signal `\usb_trans.\addr' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1480'. created $dff cell `$procdff$23102' with positive edge clock. Creating register for signal `\usb_trans.\txpkt_start_i' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1479'. created $dff cell `$procdff$23103' with positive edge clock. Creating register for signal `\usb_trans.\txpkt_pid' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1476'. created $dff cell `$procdff$23104' with positive edge clock. Creating register for signal `\usb_trans.\cel_state_i' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1470'. created $adff cell `$procdff$23105' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\epfw_issue_wb' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1468'. created $dff cell `$procdff$23106' with positive edge clock. Creating register for signal `\usb_trans.\ep_type' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1455'. created $dff cell `$procdff$23107' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_dual' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1455'. created $dff cell `$procdff$23108' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_ctrl' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1455'. created $dff cell `$procdff$23109' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_idx_cur' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1455'. created $dff cell `$procdff$23110' with positive edge clock. Creating register for signal `\usb_trans.\ep_bd_idx_nxt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1455'. created $dff cell `$procdff$23111' with positive edge clock. Creating register for signal `\usb_trans.\ep_data_toggle' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1455'. created $dff cell `$procdff$23112' with positive edge clock. Creating register for signal `\usb_trans.\bd_state' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1455'. created $dff cell `$procdff$23113' with positive edge clock. Creating register for signal `\usb_trans.\epfw_cap_dl' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1452'. created $adff cell `$procdff$23114' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\epfw_state' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1447'. created $adff cell `$procdff$23115' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\trans_is_setup' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1443'. created $dff cell `$procdff$23116' with positive edge clock. Creating register for signal `\usb_trans.\trans_endp' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1443'. created $dff cell `$procdff$23117' with positive edge clock. Creating register for signal `\usb_trans.\trans_dir' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1443'. created $dff cell `$procdff$23118' with positive edge clock. Creating register for signal `\usb_trans.\trans_cel' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1443'. created $dff cell `$procdff$23119' with positive edge clock. Creating register for signal `\usb_trans.\rto_cnt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1436'. created $adff cell `$procdff$23120' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\evt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1431'. created $adff cell `$procdff$23121' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\mc_a_reg' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1428'. created $dff cell `$procdff$23122' with positive edge clock. Creating register for signal `\usb_trans.\mc_pc_nxt' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1419'. created $adff cell `$procdff$23123' with positive edge clock and positive level reset. Creating register for signal `\usb_trans.\mc_rst_n' using process `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1410'. created $adff cell `$procdff$23124' with positive edge clock and positive level reset. Creating register for signal `\usb_rx_pkt.\pkt_data_stb' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1407'. created $dff cell `$procdff$23125' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_done_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1398'. created $dff cell `$procdff$23126' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_done_err' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1398'. created $dff cell `$procdff$23127' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pkt_start' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1396'. created $dff cell `$procdff$23128' with positive edge clock. Creating register for signal `\usb_rx_pkt.\token_data [10:8]' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1393'. created $dff cell `$procdff$23129' with positive edge clock. Creating register for signal `\usb_rx_pkt.\token_data [7:0]' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1390'. created $dff cell `$procdff$23130' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1373'. created $dff cell `$procdff$23131' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_sof' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1373'. created $dff cell `$procdff$23132' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_token' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1373'. created $dff cell `$procdff$23133' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_data' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1373'. created $dff cell `$procdff$23134' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_is_handshake' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1373'. created $dff cell `$procdff$23135' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_cap_r' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1372'. created $dff cell `$procdff$23136' with positive edge clock. Creating register for signal `\usb_rx_pkt.\pid_valid' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1351'. created $dff cell `$procdff$23137' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc5_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1347'. created $dff cell `$procdff$23138' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc16_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1347'. created $dff cell `$procdff$23139' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc_cap' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1346'. created $dff cell `$procdff$23140' with positive edge clock. Creating register for signal `\usb_rx_pkt.\crc_in_first' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1344'. created $dff cell `$procdff$23141' with positive edge clock. Creating register for signal `\usb_rx_pkt.\bit_eop_ok' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1341'. created $dff cell `$procdff$23142' with positive edge clock. Creating register for signal `\usb_rx_pkt.\bit_cnt' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1338'. created $dff cell `$procdff$23143' with positive edge clock. Creating register for signal `\usb_rx_pkt.\data' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1337'. created $dff cell `$procdff$23144' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state_prev_idle' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1329'. created $dff cell `$procdff$23145' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state_prev_error' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1329'. created $dff cell `$procdff$23146' with positive edge clock. Creating register for signal `\usb_rx_pkt.\state' using process `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1328'. created $adff cell `$procdff$23147' with positive edge clock and positive level reset. Creating register for signal `\usb_rx_ll.\dec_bs_skip_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1309'. created $dff cell `$procdff$23148' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_rep_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1307'. created $dff cell `$procdff$23149' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_sync_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1306'. created $dff cell `$procdff$23150' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_eop_state_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1305'. created $dff cell `$procdff$23151' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_valid_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1304'. created $dff cell `$procdff$23152' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_sym_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1297'. created $dff cell `$procdff$23153' with positive edge clock. Creating register for signal `\usb_rx_ll.\dec_bit_1' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1297'. created $dff cell `$procdff$23154' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_valid_0' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1290'. created $dff cell `$procdff$23155' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_cnt' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1289'. created $dff cell `$procdff$23156' with positive edge clock. Creating register for signal `\usb_rx_ll.\samp_active' using process `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1279'. created $adff cell `$procdff$23157' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[4].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4540'. created $adff cell `$procdff$23158' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[4].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4538'. created $adff cell `$procdff$23159' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[3].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4529'. created $adff cell `$procdff$23160' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[3].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4527'. created $adff cell `$procdff$23161' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[2].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4518'. created $adff cell `$procdff$23162' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[2].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4516'. created $adff cell `$procdff$23163' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[1].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4507'. created $adff cell `$procdff$23164' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.\stage[1].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4505'. created $adff cell `$procdff$23165' with positive edge clock and positive level reset. Creating register for signal `\usb_ep_status.\s_dout_3' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1275'. created $dff cell `$procdff$23166' with positive edge clock. Creating register for signal `\usb_ep_status.\p_dout_3' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1273'. created $dff cell `$procdff$23167' with positive edge clock. Creating register for signal `\usb_ep_status.\p_read_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1270'. created $dff cell `$procdff$23168' with positive edge clock. Creating register for signal `\usb_ep_status.\p_zero_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1270'. created $dff cell `$procdff$23169' with positive edge clock. Creating register for signal `\usb_ep_status.\s_read_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1270'. created $dff cell `$procdff$23170' with positive edge clock. Creating register for signal `\usb_ep_status.\s_zero_2' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1270'. created $dff cell `$procdff$23171' with positive edge clock. Creating register for signal `\usb_ep_status.\addr_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1262'. created $dff cell `$procdff$23172' with positive edge clock. Creating register for signal `\usb_ep_status.\din_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1262'. created $dff cell `$procdff$23173' with positive edge clock. Creating register for signal `\usb_ep_status.\we_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1262'. created $dff cell `$procdff$23174' with positive edge clock. Creating register for signal `\usb_ep_status.\p_read_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1262'. created $dff cell `$procdff$23175' with positive edge clock. Creating register for signal `\usb_ep_status.\p_zero_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1262'. created $dff cell `$procdff$23176' with positive edge clock. Creating register for signal `\usb_ep_status.\s_read_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1262'. created $dff cell `$procdff$23177' with positive edge clock. Creating register for signal `\usb_ep_status.\s_zero_1' using process `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1262'. created $dff cell `$procdff$23178' with positive edge clock. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[4].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4494'. created $adff cell `$procdff$23179' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[4].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4492'. created $adff cell `$procdff$23180' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[3].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4483'. created $adff cell `$procdff$23181' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[3].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4481'. created $adff cell `$procdff$23182' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[2].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4472'. created $adff cell `$procdff$23183' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[2].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4470'. created $adff cell `$procdff$23184' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[1].l_valid' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4461'. created $adff cell `$procdff$23185' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.\stage[1].l_data' using process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4459'. created $adff cell `$procdff$23186' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_rx\LIU=0\MFW=7.\bd_crc_e' using process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:203$4448'. created $adff cell `$procdff$23187' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_rx\LIU=0\MFW=7.\bd_done' using process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:196$4442'. created $dff cell `$procdff$23188' with positive edge clock. Creating register for signal `$paramod\e1_rx\LIU=0\MFW=7.\bd_miss' using process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:196$4442'. created $dff cell `$procdff$23189' with positive edge clock. Creating register for signal `$paramod\e1_rx\LIU=0\MFW=7.\mf_valid' using process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:188$4438'. created $adff cell `$procdff$23190' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\wb_rdata' using process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5374'. created $dff cell `$procdff$23191' with positive edge clock. Creating register for signal `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.\wb_ack' using process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:106$5364'. created $dff cell `$procdff$23192' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\sync' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4405'. created $dff cell `$procdff$23193' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\rise' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4400'. created $dff cell `$procdff$23194' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\fall' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4400'. created $dff cell `$procdff$23195' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\state' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4396'. created $dff cell `$procdff$23196' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.\cnt' using process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4392'. created $dff cell `$procdff$23197' with positive edge clock. Creating register for signal `\xclk_strobe.\out_stb' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1107'. created $adff cell `$procdff$23198' with positive edge clock and positive level reset. Creating register for signal `\xclk_strobe.\dst' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1106'. created $adff cell `$procdff$23199' with positive edge clock and positive level reset. Creating register for signal `\xclk_strobe.\src' using process `\xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1104'. created $adff cell `$procdff$23200' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_pending [1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5355'. created $dff cell `$procdff$23201' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_addr_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5355'. created $dff cell `$procdff$23202' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_data_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5355'. created $dff cell `$procdff$23203' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_data_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:163$5354'. created $dff cell `$procdff$23204' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_pending [0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5349'. created $adff cell `$procdff$23205' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\tx_addr_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:143$5348'. created $dff cell `$procdff$23206' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_pending [1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5347'. created $dff cell `$procdff$23207' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_data_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5347'. created $dff cell `$procdff$23208' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_addr_reg[1]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5347'. created $dff cell `$procdff$23209' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_pending [0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5342'. created $adff cell `$procdff$23210' with positive edge clock and positive level reset. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_data_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5341'. created $dff cell `$procdff$23211' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\rx_addr_reg[0]' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5341'. created $dff cell `$procdff$23212' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\wb_addr' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. created $dff cell `$procdff$23213' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\wb_addr_lsb' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. created $dff cell `$procdff$23214' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\wb_wdata_byte' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. created $dff cell `$procdff$23215' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\mux.j' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. created $dff cell `$procdff$23216' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5275' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. created $dff cell `$procdff$23217' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5276' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. created $dff cell `$procdff$23218' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:235$5277' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. created $dff cell `$procdff$23219' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\rx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:236$5278' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. created $dff cell `$procdff$23220' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5281' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. created $dff cell `$procdff$23221' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5282' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. created $dff cell `$procdff$23222' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:242$5283' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. created $dff cell `$procdff$23223' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$mem2bits$\tx_addr_reg$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:243$5284' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. created $dff cell `$procdff$23224' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_chan' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$5295'. created $dff cell `$procdff$23225' with positive edge clock. Creating register for signal `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.\t_busy' using process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5293'. created $adff cell `$procdff$23226' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\ack' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5264'. created $dff cell `$procdff$23227' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\shift' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5263'. created $adff cell `$procdff$23228' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\bit_cnt' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5260'. created $dff cell `$procdff$23229' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\div_cnt' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5256'. created $dff cell `$procdff$23230' with positive edge clock. Creating register for signal `$paramod\uart_tx\DIV_WIDTH=12.\active' using process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5252'. created $adff cell `$procdff$23231' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\rd_valid' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4345'. created $adff cell `$procdff$23232' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\ram_rd_addr' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4339'. created $adff cell `$procdff$23233' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\ram_wr_addr' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4337'. created $adff cell `$procdff$23234' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\full' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4328'. created $adff cell `$procdff$23235' with positive edge clock and positive level reset. Creating register for signal `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.\level' using process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4322'. created $adff cell `$procdff$23236' with positive edge clock and positive level reset. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\sync' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4321'. created $dff cell `$procdff$23237' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\rise' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4316'. created $dff cell `$procdff$23238' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\fall' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4316'. created $dff cell `$procdff$23239' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\state' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4312'. created $dff cell `$procdff$23240' with positive edge clock. Creating register for signal `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.\cnt' using process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4308'. created $dff cell `$procdff$23241' with positive edge clock. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\wb_now' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4299'. created $adff cell `$procdff$23242' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\rst_req' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4290'. created $adff cell `$procdff$23243' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\wb_sel' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4290'. created $adff cell `$procdff$23244' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\wb_req' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4290'. created $adff cell `$procdff$23245' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\timer' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4286'. created $adff cell `$procdff$23246' with positive edge clock and positive level reset. Creating register for signal `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.\armed' using process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4284'. created $adff cell `$procdff$23247' with positive edge clock and positive level reset. Creating register for signal `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.\dither' using process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:67$4280'. created $dff cell `$procdff$23248' with positive edge clock. Creating register for signal `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.\acc' using process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4277'. created $dff cell `$procdff$23249' with positive edge clock. Creating register for signal `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.\acc' using process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4273'. created $dff cell `$procdff$23250' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\timer' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23251' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\trap' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23252' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23253' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\eoi' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23254' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\trace_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23255' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\trace_data' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23256' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\count_cycle' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23257' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\count_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23258' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_pc' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23259' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_next_pc' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23260' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_op1' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23261' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_op2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23262' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_out' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23263' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\reg_sh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23264' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_delay' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23265' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_active' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23266' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_mask' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23267' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_pending' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23268' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_wordsize' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23269' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_do_prefetch' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23270' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_do_rinst' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23271' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_do_rdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23272' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_do_wdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23273' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoder_trigger' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23274' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoder_trigger_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23275' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoder_pseudo_trigger' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23276' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoder_pseudo_trigger_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23277' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_rs1val' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23278' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_rs2val' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23279' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_rs1val_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23280' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_rs2val_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23281' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cpu_state' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23282' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\irq_state' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23283' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\set_mem_do_rinst' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23284' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\set_mem_do_rdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23285' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\set_mem_do_wdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23286' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_store' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23287' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_stalu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23288' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_branch' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23289' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_compr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23290' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_trace' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23291' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_is_lu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23292' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_is_lh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23293' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_is_lb' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23294' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\latched_rd' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23295' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\current_pc' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23296' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_timeout' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23297' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\next_irq_pending' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23298' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\do_waitirq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23299' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_out_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23300' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_out_0_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23301' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_wait' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23302' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_wait_2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. created $dff cell `$procdff$23303' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\clear_prefetched_high_word_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$4063'. created $dff cell `$procdff$23304' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\pcpi_insn' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23305' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lui' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23306' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_auipc' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23307' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_jal' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23308' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_jalr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23309' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_beq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23310' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_bne' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23311' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_blt' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23312' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_bge' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23313' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_bltu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23314' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_bgeu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23315' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lb' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23316' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23317' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lw' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23318' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lbu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23319' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_lhu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23320' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sb' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23321' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23322' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sw' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23323' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_addi' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23324' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_slti' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23325' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sltiu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23326' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_xori' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23327' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_ori' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23328' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_andi' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23329' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_slli' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23330' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_srli' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23331' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_srai' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23332' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_add' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23333' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sub' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23334' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sll' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23335' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_slt' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23336' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sltu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23337' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_xor' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23338' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_srl' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23339' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_sra' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23340' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_or' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23341' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_and' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23342' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_rdcycle' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23343' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_rdcycleh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23344' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_rdinstr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23345' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_rdinstrh' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23346' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_ecall_ebreak' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23347' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_getq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23348' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_setq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23349' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_retirq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23350' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_maskirq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23351' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_waitirq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23352' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\instr_timer' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23353' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_rd' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23354' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_rs1' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23355' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_rs2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23356' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_imm' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23357' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\decoded_imm_uj' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23358' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\compressed_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23359' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_lui_auipc_jal' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23360' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_lb_lh_lw_lbu_lhu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23361' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_slli_srli_srai' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23362' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_jalr_addi_slti_sltiu_xori_ori_andi' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23363' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_sb_sh_sw' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23364' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_sll_srl_sra' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23365' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_lui_auipc_jal_jalr_addi_add_sub' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23366' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_slti_blt_slt' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23367' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_sltiu_bltu_sltu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23368' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_beq_bne_blt_bge_bltu_bgeu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23369' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_lbu_lhu_lw' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23370' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_alu_reg_imm' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23371' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_alu_reg_reg' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23372' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\is_compare' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. created $dff cell `$procdff$23373' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_insn_addr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23374' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_ascii_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23375' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_imm' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23376' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_opcode' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23377' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_rs1' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23378' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_rs2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23379' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\q_insn_rd' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23380' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_next' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23381' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\dbg_valid_insn' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23382' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_ascii_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23383' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_imm' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23384' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_opcode' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23385' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_rs1' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23386' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_rs2' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23387' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\cached_insn_rd' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. created $dff cell `$procdff$23388' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_addr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3738'. created $dff cell `$procdff$23389' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3738'. created $dff cell `$procdff$23390' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_instr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3738'. created $dff cell `$procdff$23391' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_wdata' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3738'. created $dff cell `$procdff$23392' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_wstrb' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3738'. created $dff cell `$procdff$23393' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_state' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3738'. created $dff cell `$procdff$23394' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_la_secondword' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3738'. created $dff cell `$procdff$23395' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\prefetched_high_word' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3738'. created $dff cell `$procdff$23396' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_16bit_buffer' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3738'. created $dff cell `$procdff$23397' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_add_sub' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4262'. created $dff cell `$procdff$23398' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_shl' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4262'. created $dff cell `$procdff$23399' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_shr' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4262'. created $dff cell `$procdff$23400' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_eq' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4262'. created $dff cell `$procdff$23401' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_ltu' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4262'. created $dff cell `$procdff$23402' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\alu_lts' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4262'. created $dff cell `$procdff$23403' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\next_insn_opcode' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3700'. created $dff cell `$procdff$23404' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_rdata_q' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3700'. created $dff cell `$procdff$23405' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\mem_la_firstword_reg' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3692'. created $dff cell `$procdff$23406' with positive edge clock. Creating register for signal `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.\last_mem_valid' using process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3692'. created $dff cell `$procdff$23407' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\stb' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5246'. created $dff cell `$procdff$23408' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\shift' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5245'. created $dff cell `$procdff$23409' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\bit_cnt' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5242'. created $dff cell `$procdff$23410' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\div_cnt' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5238'. created $dff cell `$procdff$23411' with positive edge clock. Creating register for signal `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.\active' using process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5234'. created $adff cell `$procdff$23412' with positive edge clock and positive level reset. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.\rdata' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. created $dff cell `$procdff$23413' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. created $dff cell `$procdff$23414' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. created $dff cell `$procdff$23415' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. created $dff cell `$procdff$23416' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. created $dff cell `$procdff$23417' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. created $dff cell `$procdff$23418' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. created $dff cell `$procdff$23419' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. created $dff cell `$procdff$23420' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. created $dff cell `$procdff$23421' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. created $dff cell `$procdff$23422' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_ADDR' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. created $dff cell `$procdff$23423' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_DATA' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. created $dff cell `$procdff$23424' with positive edge clock. Creating register for signal `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN' using process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. created $dff cell `$procdff$23425' with positive edge clock. Creating register for signal `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.\led_ctrl' using process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3499'. created $adff cell `$procdff$23426' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\evt_cnt' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3493'. created $adff cell `$procdff$23427' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\sof_pending' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3488'. created $dff cell `$procdff$23428' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\sof_ind' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3486'. created $dff cell `$procdff$23429' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\pad_pu' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3485'. created $dff cell `$procdff$23430' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\rst_pending' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3481'. created $adff cell `$procdff$23431' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\timeout_reset' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3477'. created $dff cell `$procdff$23432' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\timeout_suspend' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3473'. created $dff cell `$procdff$23433' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_ack_wait' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3459'. created $adff cell `$procdff$23434' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_req_ok_dly' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3456'. created $dff cell `$procdff$23435' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_read' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3446'. created $dff cell `$procdff$23436' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_write' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3446'. created $dff cell `$procdff$23437' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\eps_bus_req' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3446'. created $dff cell `$procdff$23438' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\cr_pu_ena' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3444'. created $adff cell `$procdff$23439' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_cel_ena' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3444'. created $adff cell `$procdff$23440' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_addr_chk' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3444'. created $adff cell `$procdff$23441' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cr_addr' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3444'. created $adff cell `$procdff$23442' with positive edge clock and positive level reset. Creating register for signal `$paramod\usb\EPDW=32.\cel_rel' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3422'. created $dff cell `$procdff$23443' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\csr_bus_req' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3422'. created $dff cell `$procdff$23444' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\cr_bus_we' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3422'. created $dff cell `$procdff$23445' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\ir_bus_we' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3422'. created $dff cell `$procdff$23446' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\evt_rd_ack' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3422'. created $dff cell `$procdff$23447' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\rst_clear' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3422'. created $dff cell `$procdff$23448' with positive edge clock. Creating register for signal `$paramod\usb\EPDW=32.\sof_clear' using process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3422'. created $dff cell `$procdff$23449' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\m_cyc_i' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3418'. created $adff cell `$procdff$23450' with positive edge clock and positive level reset. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_cyc_d' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3414'. created $dff cell `$procdff$23451' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_ack_d' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3414'. created $dff cell `$procdff$23452' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\s_rdata' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3411'. created $dff cell `$procdff$23453' with positive edge clock. Creating register for signal `$paramod\xclk_wb\DW=16\AW=12.\m_rdata_i' using process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3410'. created $dff cell `$procdff$23454' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\sda_oe' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5221'. created $dff cell `$procdff$23455' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\scl_oe' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5218'. created $dff cell `$procdff$23456' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\data_reg' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5214'. created $dff cell `$procdff$23457' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\bit_cnt' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5210'. created $dff cell `$procdff$23458' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\cyc_cnt' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5206'. created $dff cell `$procdff$23459' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\cmd_cur' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:121$5205'. created $dff cell `$procdff$23460' with positive edge clock. Creating register for signal `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.\state' using process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5199'. created $dff cell `$procdff$23461' with positive edge clock. Creating register for signal `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.\out' using process `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5198'. created $dff cell `$procdff$23462' with positive edge clock. Creating register for signal `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.\pb_rst_n' using process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3322'. created $adff cell `$procdff$23463' with positive edge clock and positive level reset. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\uart_div' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3308'. created $dff cell `$procdff$23464' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rdata' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3306'. created $dff cell `$procdff$23465' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_ack' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3296'. created $dff cell `$procdff$23466' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rd_data' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3279'. created $dff cell `$procdff$23467' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_rd_ctrl' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3279'. created $dff cell `$procdff$23468' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_wr_data' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3279'. created $dff cell `$procdff$23469' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\ub_wr_div' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3279'. created $dff cell `$procdff$23470' with positive edge clock. Creating register for signal `$paramod\uart_wb\DIV_WIDTH=12\DW=32.\urf_overflow' using process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3274'. created $adff cell `$procdff$23471' with positive edge clock and positive level reset. Creating register for signal `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.\wb_rdata' using process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3269'. created $dff cell `$procdff$23472' with positive edge clock. Creating register for signal `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.\wb_ack' using process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:85$3261'. created $dff cell `$procdff$23473' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\srio_clk_o' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3259'. created $dff cell `$procdff$23474' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\srio_dat_o' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3259'. created $dff cell `$procdff$23475' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\srio_rclk_o' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3259'. created $dff cell `$procdff$23476' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\srio_rclk_oe' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3259'. created $dff cell `$procdff$23477' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\shift_data' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:279$3258'. created $dff cell `$procdff$23478' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\btn_stb' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:270$3246'. created $dff cell `$procdff$23479' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\btn_val' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:262$3239'. created $dff cell `$procdff$23480' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\sense_cnt_in' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:243$3233'. created $dff cell `$procdff$23481' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\sense_cnt' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:243$3233'. created $dff cell `$procdff$23482' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\bit_cnt' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:227$3226'. created $dff cell `$procdff$23483' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\tick_cnt' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:214$3220'. created $dff cell `$procdff$23484' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\btn_sync' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:206$3219'. created $dff cell `$procdff$23485' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\sio_sel' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:197$3217'. created $dff cell `$procdff$23486' with positive edge clock. Creating register for signal `$paramod\sr_btn_if\TICK_LOG2_DIV=3.\state' using process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3204'. created $dff cell `$procdff$23487' with positive edge clock. Creating register for signal `\hdb3_enc.\pstate' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$447'. created $dff cell `$procdff$23488' with positive edge clock. Creating register for signal `\hdb3_enc.\d_pos' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$447'. created $dff cell `$procdff$23489' with positive edge clock. Creating register for signal `\hdb3_enc.\d_neg' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$447'. created $dff cell `$procdff$23490' with positive edge clock. Creating register for signal `\hdb3_enc.\zcnt' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$447'. created $dff cell `$procdff$23491' with positive edge clock. Creating register for signal `\hdb3_enc.\vstate' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$447'. created $dff cell `$procdff$23492' with positive edge clock. Creating register for signal `\hdb3_enc.\out_valid' using process `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:41$446'. created $dff cell `$procdff$23493' with positive edge clock. Creating register for signal `\hdb3_dec.\data' using process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$443'. created $dff cell `$procdff$23494' with positive edge clock. Creating register for signal `\hdb3_dec.\pstate' using process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$443'. created $dff cell `$procdff$23495' with positive edge clock. Creating register for signal `\hdb3_dec.\out_valid' using process `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:37$438'. created $dff cell `$procdff$23496' with positive edge clock. Creating register for signal `\e1_tx_framer.\out_valid' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:253$252'. created $adff cell `$procdff$23497' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\out_bit' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:253$252'. created $adff cell `$procdff$23498' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\crc_smf' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:241$250'. created $adff cell `$procdff$23499' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\crc_capture' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:229$249'. created $dff cell `$procdff$23500' with positive edge clock. Creating register for signal `\e1_tx_framer.\shift_at_first' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:209$237'. created $adff cell `$procdff$23501' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\shift_at_last' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:209$237'. created $adff cell `$procdff$23502' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\shift_at_crc' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:209$237'. created $adff cell `$procdff$23503' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\shift_data' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:199$234'. created $adff cell `$procdff$23504' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\bit_cnt' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:192$230'. created $adff cell `$procdff$23505' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\shift_data_nxt' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:167$227'. created $dff cell `$procdff$23506' with positive edge clock. Creating register for signal `\e1_tx_framer.\fetch_done' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:148$223'. created $adff cell `$procdff$23507' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\in_req' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:144$222'. created $dff cell `$procdff$23508' with positive edge clock. Creating register for signal `\e1_tx_framer.\in_mf_first' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$218'. created $adff cell `$procdff$23509' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\in_mf_last' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$218'. created $adff cell `$procdff$23510' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\fetch_ts' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$215'. created $adff cell `$procdff$23511' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\fetch_ts_is0' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$215'. created $adff cell `$procdff$23512' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\fetch_ts_is31' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$215'. created $adff cell `$procdff$23513' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\fetch_frame' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:113$213'. created $adff cell `$procdff$23514' with positive edge clock and positive level reset. Creating register for signal `\e1_tx_framer.\strobe' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:103$209'. created $dff cell `$procdff$23515' with positive edge clock. Creating register for signal `\e1_tx_framer.\tick_cnt' using process `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:97$205'. created $adff cell `$procdff$23516' with positive edge clock and positive level reset. Creating register for signal `\e1_rx_filter.\out_hi' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$168'. created $dff cell `$procdff$23517' with positive edge clock. Creating register for signal `\e1_rx_filter.\out_lo' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$168'. created $dff cell `$procdff$23518' with positive edge clock. Creating register for signal `\e1_rx_filter.\out_stb' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$168'. created $dff cell `$procdff$23519' with positive edge clock. Creating register for signal `\e1_rx_filter.\cnt_hi' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$149'. created $dff cell `$procdff$23520' with positive edge clock. Creating register for signal `\e1_rx_filter.\cnt_lo' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$149'. created $dff cell `$procdff$23521' with positive edge clock. Creating register for signal `\e1_rx_filter.\in_hi_r' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:39$148'. created $dff cell `$procdff$23522' with positive edge clock. Creating register for signal `\e1_rx_filter.\in_lo_r' using process `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:39$148'. created $dff cell `$procdff$23523' with positive edge clock. Creating register for signal `\e1_rx_deframer.\aligned' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$146'. created $dff cell `$procdff$23524' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_data' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$140'. created $dff cell `$procdff$23525' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_frame' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$140'. created $dff cell `$procdff$23526' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_ts' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$140'. created $dff cell `$procdff$23527' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_ts_is0' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$140'. created $dff cell `$procdff$23528' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$140'. created $dff cell `$procdff$23529' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$140'. created $dff cell `$procdff$23530' with positive edge clock. Creating register for signal `\e1_rx_deframer.\out_valid' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$140'. created $dff cell `$procdff$23531' with positive edge clock. Creating register for signal `\e1_rx_deframer.\error' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:357$132'. created $dff cell `$procdff$23532' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$114'. created $dff cell `$procdff$23533' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$114'. created $dff cell `$procdff$23534' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$114'. created $dff cell `$procdff$23535' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ec_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$114'. created $dff cell `$procdff$23536' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$94'. created $dff cell `$procdff$23537' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$94'. created $dff cell `$procdff$23538' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$94'. created $dff cell `$procdff$23539' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_mfa' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$94'. created $dff cell `$procdff$23540' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$72'. created $dff cell `$procdff$23541' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$72'. created $dff cell `$procdff$23542' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ed_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$72'. created $dff cell `$procdff$23543' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ep_nfas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$72'. created $dff cell `$procdff$23544' with positive edge clock. Creating register for signal `\e1_rx_deframer.\crc_smf' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$71'. created $dff cell `$procdff$23545' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$60'. created $dff cell `$procdff$23546' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs_match_mf' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$60'. created $dff cell `$procdff$23547' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts0_msbs_match_crc' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$60'. created $dff cell `$procdff$23548' with positive edge clock. Creating register for signal `\e1_rx_deframer.\mfa_timeout' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$56'. created $dff cell `$procdff$23549' with positive edge clock. Creating register for signal `\e1_rx_deframer.\fas_pos' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$52'. created $dff cell `$procdff$23550' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$42'. created $dff cell `$procdff$23551' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_smf_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$42'. created $dff cell `$procdff$23552' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_smf_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$42'. created $dff cell `$procdff$23553' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_mf_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$42'. created $dff cell `$procdff$23554' with positive edge clock. Creating register for signal `\e1_rx_deframer.\frame_mf_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$42'. created $dff cell `$procdff$23555' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$38'. created $dff cell `$procdff$23556' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts_is_ts0' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$38'. created $dff cell `$procdff$23557' with positive edge clock. Creating register for signal `\e1_rx_deframer.\ts_is_ts31' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$38'. created $dff cell `$procdff$23558' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$34'. created $dff cell `$procdff$23559' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit_first' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$34'. created $dff cell `$procdff$23560' with positive edge clock. Creating register for signal `\e1_rx_deframer.\bit_last' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$34'. created $dff cell `$procdff$23561' with positive edge clock. Creating register for signal `\e1_rx_deframer.\fsm_state' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$24'. created $dff cell `$procdff$23562' with positive edge clock. Creating register for signal `\e1_rx_deframer.\data_match_fas' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$21'. created $dff cell `$procdff$23563' with positive edge clock. Creating register for signal `\e1_rx_deframer.\data' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$20'. created $dff cell `$procdff$23564' with positive edge clock. Creating register for signal `\e1_rx_deframer.\strobe' using process `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$19'. created $dff cell `$procdff$23565' with positive edge clock. Creating register for signal `\e1_rx_clock_recovery.\cnt' using process `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:39$17'. created $dff cell `$procdff$23566' with positive edge clock. Creating register for signal `\e1_rx_clock_recovery.\enabled' using process `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:33$15'. created $dff cell `$procdff$23567' with positive edge clock. Creating register for signal `\e1_crc4.\state' using process `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$13'. created $dff cell `$procdff$23568' with positive edge clock. 75.3.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3067'. Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3064'. Removing empty process `SB_DFFNES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1330$3064'. Removing empty process `SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3063'. Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3057'. Removing empty process `SB_DFFNESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1274$3057'. Removing empty process `SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3056'. Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3053'. Removing empty process `SB_DFFNER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1199$3053'. Removing empty process `SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3052'. Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3046'. Removing empty process `SB_DFFNESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1143$3046'. Removing empty process `SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3045'. Removing empty process `SB_DFFNS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1074$3043'. Removing empty process `SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3042'. Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3040'. Removing empty process `SB_DFFNSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:1026$3040'. Removing empty process `SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3039'. Removing empty process `SB_DFFNR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:957$3037'. Removing empty process `SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3036'. Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3034'. Removing empty process `SB_DFFNSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:909$3034'. Removing empty process `SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3033'. Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$3032'. Removing empty process `SB_DFFNE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:866$3032'. Removing empty process `SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3031'. Removing empty process `SB_DFFN.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:830$3030'. Removing empty process `SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3029'. Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3026'. Removing empty process `SB_DFFES.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:753$3026'. Removing empty process `SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3025'. Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3019'. Removing empty process `SB_DFFESS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:697$3019'. Removing empty process `SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3018'. Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3015'. Removing empty process `SB_DFFER.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:622$3015'. Removing empty process `SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3014'. Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3008'. Removing empty process `SB_DFFESR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:566$3008'. Removing empty process `SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3007'. Removing empty process `SB_DFFS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:497$3005'. Removing empty process `SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3004'. Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$3002'. Removing empty process `SB_DFFSS.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:449$3002'. Removing empty process `SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$3001'. Removing empty process `SB_DFFR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:380$2999'. Removing empty process `SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2998'. Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2996'. Removing empty process `SB_DFFSR.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:332$2996'. Removing empty process `SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2995'. Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2994'. Removing empty process `SB_DFFE.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:289$2994'. Removing empty process `SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:0$2993'. Removing empty process `SB_DFF.$proc$/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_sim.v:253$2992'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$5195'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5190'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$5190'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5186'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$5186'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5182'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$5182'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5174'. Removing empty process `$paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$5174'. Removing empty process `$paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_wb.v:50$5171'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5150'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5150'. Found and cleaned up 3 empty switches in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5141'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5141'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5138'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5138'. Removing empty process `$paramod\wb_arbiter\N=3\DW=32\AW=14.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5119'. Removing empty process `$paramod\wb_epbuf\AW=9\DW=32.$proc$/build/gateware/common/rtl/wb_epbuf.v:51$5107'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5096'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:116$5096'. Found and cleaned up 2 empty switches in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5089'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:100$5089'. Found and cleaned up 1 empty switch in `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5086'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:80$5086'. Removing empty process `$paramod\wb_arbiter\N=2\DW=32\AW=9.$proc$/build/gateware/common/rtl/wb_arbiter.v:65$5073'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:190$5054'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$5050'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:178$5050'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$5047'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:174$5047'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$5037'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:157$5037'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$5033'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:153$5033'. Found and cleaned up 1 empty switch in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$5031'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:142$5031'. Found and cleaned up 4 empty switches in `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$5015'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:98$5015'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:92$5014'. Removing empty process `$paramod\wb_dma\A0W=14\A1W=9\DW=32.$proc$/build/gateware/common/rtl/wb_dma.v:86$5010'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5006'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$5002'. Removing empty process `$paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr.$proc$/build/gateware/cores/no2ice40//rtl/ice40_ebr.v:0$4998'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5569'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5565'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5561'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5557'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5553'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5549'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5545'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5541'. Removing empty process `$paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5537'. Found and cleaned up 1 empty switch in `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4968'. Removing empty process `$paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4968'. Found and cleaned up 1 empty switch in `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4955'. Removing empty process `$paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101.$proc$/build/gateware/cores/no2usb//rtl/usb_crc.v:40$4955'. Found and cleaned up 2 empty switches in `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4931'. Removing empty process `$paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000.$proc$/build/gateware/cores/no2usb//rtl/usb_phy.v:81$4931'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5514'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5510'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5506'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5502'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5498'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5494'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5490'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5486'. Removing empty process `$paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_buf.v:0$5482'. Found and cleaned up 2 empty switches in `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5458'. Removing empty process `$paramod\ram_sdp\AWIDTH=9\DWIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/ram_sdp.v:39$5458'. Found and cleaned up 1 empty switch in `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5452'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:163$5452'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:160$5450'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:147$5423'. Removing empty process `$paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4.$proc$/build/gateware/common/rtl/soc_picorv32_bridge.v:91$5420'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:0$4812'. Found and cleaned up 16 empty switches in `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:81$4656'. Found and cleaned up 1 empty switch in `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4655'. Removing empty process `$paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32.$proc$/build/gateware/cores/no2ice40//rtl/ice40_spram_gen.v:73$4655'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:254$4638'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:247$4634'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:240$4632'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4614'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:143$4614'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4613'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:118$4613'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4605'. Removing empty process `$paramod\e1_wb_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:108$4605'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:265$4599'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:258$4597'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4574'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:152$4574'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4573'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:122$4573'. Found and cleaned up 1 empty switch in `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4565'. Removing empty process `$paramod\e1_wb_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:112$4565'. Removing empty process `sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:84$1719'. Found and cleaned up 1 empty switch in `\sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1714'. Removing empty process `sysmgr.$proc$/build/gateware/icE1usb/rtl/sysmgr.v:76$1714'. Found and cleaned up 2 empty switches in `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4560'. Removing empty process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:160$4560'. Removing empty process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:100$4552'. Found and cleaned up 1 empty switch in `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4550'. Removing empty process `$paramod\e1_tx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_tx.v:93$4550'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1654'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1652'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1650'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1648'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1646'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1644'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1642'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:0$1640'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:302$1639'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:302$1639'. Found and cleaned up 4 empty switches in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1638'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:260$1638'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:183$1637'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:183$1637'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:170$1636'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:170$1636'. Found and cleaned up 2 empty switches in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:130$1635'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:130$1635'. Found and cleaned up 1 empty switch in `\misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1625'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:110$1625'. Removing empty process `misc.$proc$/build/gateware/icE1usb/rtl/misc.v:104$1620'. Removing empty process `led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:89$1607'. Removing empty process `led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:77$1598'. Removing empty process `led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:65$1594'. Removing empty process `led_blinker.$proc$/build/gateware/icE1usb/rtl/led_blinker.v:55$1590'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:241$1582'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:229$1579'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:202$1573'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1569'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:191$1569'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:182$1563'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1556'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:175$1556'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1554'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:170$1554'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1550'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:159$1550'. Found and cleaned up 1 empty switch in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1547'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:152$1547'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:136$1535'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:126$1534'. Found and cleaned up 8 empty switches in `\usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1532'. Removing empty process `usb_tx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:86$1532'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:134$1531'. Found and cleaned up 2 empty switches in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1529'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:117$1529'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:110$1522'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:102$1517'. Found and cleaned up 1 empty switch in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1507'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:89$1507'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:79$1504'. Found and cleaned up 4 empty switches in `\usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1501'. Removing empty process `usb_tx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:58$1501'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1497'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:236$1497'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:428$1489'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1486'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:421$1486'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:414$1480'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:403$1479'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1476'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:399$1476'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:387$1470'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:380$1468'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1455'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:356$1455'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:345$1452'. Found and cleaned up 4 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1447'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:293$1447'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1443'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:282$1443'. Found and cleaned up 1 empty switch in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1436'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:249$1436'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:225$1431'. Found and cleaned up 2 empty switches in `\usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1428'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:210$1428'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:175$1419'. Removing empty process `usb_trans.$proc$/build/gateware/cores/no2usb//rtl/usb_trans.v:162$1410'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:374$1407'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:353$1398'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:349$1396'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1393'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:340$1393'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1390'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:336$1390'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1373'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:322$1373'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:318$1372'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1351'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:304$1351'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1347'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:287$1347'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:284$1346'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1344'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:244$1344'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1341'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:230$1341'. Found and cleaned up 2 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1338'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:220$1338'. Found and cleaned up 1 empty switch in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1337'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:215$1337'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:198$1329'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:188$1328'. Found and cleaned up 18 empty switches in `\usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1312'. Removing empty process `usb_rx_pkt.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:117$1312'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:49$1311'. Found and cleaned up 1 empty switch in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1309'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:181$1309'. Found and cleaned up 3 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1307'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:160$1307'. Found and cleaned up 3 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1306'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:137$1306'. Found and cleaned up 2 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1305'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:124$1305'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:120$1304'. Found and cleaned up 1 empty switch in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1297'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:111$1297'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:97$1290'. Found and cleaned up 2 empty switches in `\usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1289'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:77$1289'. Removing empty process `usb_rx_ll.$proc$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:67$1279'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4549'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4540'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4540'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4538'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4538'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4529'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4529'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4527'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4527'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4518'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4518'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4516'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4516'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4507'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4507'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4505'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=7.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4505'. Found and cleaned up 1 empty switch in `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1275'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:80$1275'. Found and cleaned up 1 empty switch in `\usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1273'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:76$1273'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:67$1270'. Removing empty process `usb_ep_status.$proc$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:55$1262'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:0$4503'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4494'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4494'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4492'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4492'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4483'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4483'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4481'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4481'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4472'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4472'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4470'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4470'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4461'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:64$4461'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4459'. Removing empty process `$paramod\fifo_sync_shift\DEPTH=4\WIDTH=9.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:57$4459'. Removing empty process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:203$4448'. Removing empty process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:196$4442'. Removing empty process `$paramod\e1_rx\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_rx.v:188$4438'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:0$5379'. Found and cleaned up 1 empty switch in `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5374'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:125$5374'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:117$5369'. Removing empty process `$paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7.$proc$/build/gateware/cores/no2e1//rtl/e1_wb.v:106$5364'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4405'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4400'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4400'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4396'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4396'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4392'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4392'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4384'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4384'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:40$1107'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:34$1106'. Removing empty process `xclk_strobe.$proc$/build/gateware/cores/no2misc//rtl/xclk_strobe.v:28$1104'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:172$5355'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:163$5354'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:163$5354'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:153$5349'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:143$5348'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:143$5348'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:123$5347'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:111$5342'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5341'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:100$5341'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5331'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:261$5331'. Found and cleaned up 5 empty switches in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:221$5298'. Found and cleaned up 1 empty switch in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$5295'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:212$5295'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:206$5293'. Found and cleaned up 4 empty switches in `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5291'. Removing empty process `$paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32.$proc$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:190$5291'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:67$5264'. Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5263'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:58$5263'. Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5260'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:51$5260'. Found and cleaned up 1 empty switch in `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5256'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:42$5256'. Removing empty process `$paramod\uart_tx\DIV_WIDTH=12.$proc$/build/gateware/cores/no2misc//rtl/uart_tx.v:35$5252'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4345'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:116$4345'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4339'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:108$4339'. Found and cleaned up 1 empty switch in `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4337'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:95$4337'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:83$4328'. Removing empty process `$paramod\fifo_sync_ram\DEPTH=512\WIDTH=8.$proc$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:67$4322'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:53$4321'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4316'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:95$4316'. Found and cleaned up 3 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4312'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:80$4312'. Found and cleaned up 1 empty switch in `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4308'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:70$4308'. Found and cleaned up 2 empty switches in `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4300'. Removing empty process `$paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1.$proc$/build/gateware/cores/no2misc//rtl/glitch_filter.v:60$4300'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:149$4299'. Found and cleaned up 2 empty switches in `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4290'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:120$4290'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:109$4286'. Removing empty process `$paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0.$proc$/build/gateware/common/rtl/dfu_helper.v:103$4284'. Removing empty process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:67$4280'. Found and cleaned up 1 empty switch in `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4277'. Removing empty process `$paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4277'. Removing empty process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:72$4276'. Found and cleaned up 1 empty switch in `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4273'. Removing empty process `$paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:42$4273'. Found and cleaned up 55 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1375$4097'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1360$4083'. Found and cleaned up 2 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4069'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1288$4069'. Found and cleaned up 2 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$4064'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1274$4064'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1272$4063'. Found and cleaned up 2 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4041'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1228$4041'. Found and cleaned up 8 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$4029'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1165$4029'. Found and cleaned up 22 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:840$3769'. Found and cleaned up 3 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3767'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:791$3767'. Found and cleaned up 5 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:760$3763'. Found and cleaned up 47 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3762'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:684$3762'. Found and cleaned up 16 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3738'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:549$3738'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:1209$4262'. Found and cleaned up 19 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3700'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:414$3700'. Found and cleaned up 3 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3697'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:385$3697'. Found and cleaned up 2 empty switches in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3692'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:374$3692'. Found and cleaned up 1 empty switch in `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3618'. Removing empty process `$paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32.$proc$/build/gateware/common/rtl/picorv32.v:309$3618'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:102$5246'. Found and cleaned up 1 empty switch in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5245'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:95$5245'. Found and cleaned up 2 empty switches in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5242'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:88$5242'. Found and cleaned up 2 empty switches in `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5238'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:77$5238'. Removing empty process `$paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2.$proc$/build/gateware/cores/no2misc//rtl/uart_rx.v:70$5234'. Found and cleaned up 4 empty switches in `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. Removing empty process `$paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram.$proc$/build/gateware/common/rtl/soc_bram.v:31$3508'. Found and cleaned up 1 empty switch in `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3499'. Removing empty process `$paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb.$proc$/build/gateware/cores/no2ice40//rtl/ice40_rgb_wb.v:94$3499'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:536$3493'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:656$3488'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:653$3486'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3485'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:643$3485'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:636$3481'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3477'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:628$3477'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3473'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:619$3473'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:514$3459'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:510$3456'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3446'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:491$3446'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:697$3497'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3444'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:458$3444'. Found and cleaned up 2 empty switches in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3440'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:442$3440'. Found and cleaned up 1 empty switch in `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3422'. Removing empty process `$paramod\usb\EPDW=32.$proc$/build/gateware/cores/no2usb//rtl/usb.v:399$3422'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:99$3418'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:83$3414'. Found and cleaned up 1 empty switch in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3411'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:73$3411'. Found and cleaned up 1 empty switch in `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3410'. Removing empty process `$paramod\xclk_wb\DW=16\AW=12.$proc$/build/gateware/cores/no2misc//rtl/xclk_wb.v:68$3410'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5230'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:0$5229'. Found and cleaned up 6 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5221'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:214$5221'. Found and cleaned up 4 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5218'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:204$5218'. Found and cleaned up 2 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5214'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:159$5214'. Found and cleaned up 3 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5210'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:141$5210'. Found and cleaned up 1 empty switch in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5206'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:129$5206'. Found and cleaned up 1 empty switch in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:121$5205'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:121$5205'. Found and cleaned up 7 empty switches in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5200'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:87$5200'. Found and cleaned up 1 empty switch in `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5199'. Removing empty process `$paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master.v:81$5199'. Found and cleaned up 1 empty switch in `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5198'. Removing empty process `$paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001.$proc$/build/gateware/cores/no2misc//rtl/pdm.v:133$5198'. Removing empty process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3327'. Removing empty process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3325'. Removing empty process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:0$3323'. Removing empty process `$paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base.$proc$/build/gateware/common/rtl/soc_base.v:185$3322'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3308'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:193$3308'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3306'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:185$3306'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3296'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:177$3296'. Found and cleaned up 1 empty switch in `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3279'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:164$3279'. Removing empty process `$paramod\uart_wb\DIV_WIDTH=12\DW=32.$proc$/build/gateware/cores/no2misc//rtl/uart_wb.v:154$3274'. Found and cleaned up 1 empty switch in `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3269'. Removing empty process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:91$3269'. Removing empty process `$paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0.$proc$/build/gateware/cores/no2misc//rtl/i2c_master_wb.v:85$3261'. Found and cleaned up 1 empty switch in `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3259'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:291$3259'. Found and cleaned up 1 empty switch in `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:279$3258'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:279$3258'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:270$3246'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:262$3239'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:243$3233'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:227$3226'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:214$3220'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:206$3219'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:197$3217'. Found and cleaned up 9 empty switches in `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3205'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:121$3205'. Found and cleaned up 1 empty switch in `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3204'. Removing empty process `$paramod\sr_btn_if\TICK_LOG2_DIV=3.$proc$/build/gateware/icE1usb/rtl/sr_btn_if.v:114$3204'. Found and cleaned up 5 empty switches in `\hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$447'. Removing empty process `hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:45$447'. Removing empty process `hdb3_enc.$proc$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:41$446'. Found and cleaned up 4 empty switches in `\hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$443'. Removing empty process `hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:43$443'. Removing empty process `hdb3_dec.$proc$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:37$438'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:253$252'. Found and cleaned up 2 empty switches in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:241$250'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:241$250'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:229$249'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:209$237'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:209$237'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:199$234'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:199$234'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:192$230'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:192$230'. Found and cleaned up 2 empty switches in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:167$227'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:167$227'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:148$223'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:148$223'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:144$222'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$218'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:135$218'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$215'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:120$215'. Found and cleaned up 1 empty switch in `\e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:113$213'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:113$213'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:103$209'. Removing empty process `e1_tx_framer.$proc$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:97$205'. Found and cleaned up 4 empty switches in `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$168'. Removing empty process `e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:71$168'. Found and cleaned up 5 empty switches in `\e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$149'. Removing empty process `e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:46$149'. Removing empty process `e1_rx_filter.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:39$148'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$146'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:406$146'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$140'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:365$140'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:357$132'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$114'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:344$114'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$94'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:329$94'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$72'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:315$72'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$71'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:306$71'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$60'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:274$60'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$56'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:266$56'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$52'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:258$52'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$42'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:231$42'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$38'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:219$38'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$34'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:207$34'. Found and cleaned up 10 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$26'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:149$26'. Found and cleaned up 2 empty switches in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$24'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:142$24'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$21'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:133$21'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$20'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:128$20'. Found and cleaned up 1 empty switch in `\e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$19'. Removing empty process `e1_rx_deframer.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:121$19'. Found and cleaned up 4 empty switches in `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:39$17'. Removing empty process `e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:39$17'. Found and cleaned up 1 empty switch in `\e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:33$15'. Removing empty process `e1_rx_clock_recovery.$proc$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:33$15'. Found and cleaned up 1 empty switch in `\e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$13'. Removing empty process `e1_crc4.$proc$/build/gateware/cores/no2e1//rtl/e1_crc4.v:38$13'. Cleaned up 540 empty switches. 75.4. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod\glitch_filter\L=4\RST_VAL=1'0\WITH_SYNCHRONIZER=1\WITH_SAMP_COND=1'0. Deleting now unused module $paramod\ice40_spram_wb\AW=14\DW=32\ZERO_RDATA=0. Deleting now unused module $paramod\wb_arbiter\N=3\DW=32\AW=14. Deleting now unused module $paramod\wb_epbuf\AW=9\DW=32. Deleting now unused module $paramod\wb_arbiter\N=2\DW=32\AW=9. Deleting now unused module soc_iobuf. Deleting now unused module $paramod\wb_dma\A0W=14\A1W=9\DW=32. Deleting now unused module $paramod$378870cfb06e08a90373493fb48767f352080cd3\ice40_ebr. Deleting now unused module picorv32_ice40_regs. Deleting now unused module $paramod$eb8ac1f548f32e0d53e54d71ace4509f90139868\usb_ep_buf. Deleting now unused module $paramod\usb_crc\WIDTH=5\POLY=5'00101\MATCH=5'01100. Deleting now unused module $paramod\usb_crc\WIDTH=16\POLY=16'1000000000000101\MATCH=16'1000000000001101. Deleting now unused module $paramod\usb_phy\TARGET=40'0100100101000011010001010011010000110000. Deleting now unused module $paramod$05771025eb2b8cb2c5b473bd870cc61d0f9215fc\usb_ep_buf. Deleting now unused module $paramod\ram_sdp\AWIDTH=9\DWIDTH=8. Deleting now unused module $paramod\soc_picorv32_bridge\WB_N=11\WB_DW=32\WB_AW=16\WB_AI=2\WB_REG=4. Deleting now unused module $paramod\ice40_spram_gen\ADDR_WIDTH=14\DATA_WIDTH=32. Deleting now unused module $paramod\e1_wb_rx\LIU=0\MFW=7. Deleting now unused module capcnt32_sb_mac16. Deleting now unused module capcnt16_sb_mac16. Deleting now unused module $paramod\e1_wb_tx\LIU=0\MFW=7. Deleting now unused module sysmgr. Deleting now unused module $paramod\e1_tx\LIU=0\MFW=7. Deleting now unused module misc. Deleting now unused module led_blinker. Deleting now unused module usb_tx_pkt. Deleting now unused module usb_tx_ll. Deleting now unused module usb_trans. Deleting now unused module usb_rx_pkt. Deleting now unused module usb_rx_ll. Deleting now unused module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=7. Deleting now unused module usb_ep_status. Deleting now unused module $paramod\fifo_sync_shift\DEPTH=4\WIDTH=9. Deleting now unused module $paramod\e1_rx\LIU=0\MFW=7. Deleting now unused module $paramod\e1_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\LIU=0\MFW=7. Deleting now unused module $paramod\glitch_filter\L=2\RST_VAL=1'1\WITH_SYNCHRONIZER=1. Deleting now unused module xclk_strobe. Deleting now unused module $paramod\e1_buf_if_wb\N=2\UNIT_HAS_RX=2'01\UNIT_HAS_TX=2'01\MFW=7\DW=32. Deleting now unused module $paramod\uart_tx\DIV_WIDTH=12. Deleting now unused module $paramod\fifo_sync_ram\DEPTH=512\WIDTH=8. Deleting now unused module $paramod\glitch_filter\L=2\RST_VAL=1'0\WITH_SYNCHRONIZER=1. Deleting now unused module $paramod\capcnt\W=32. Deleting now unused module $paramod\dfu_helper\TIMER_WIDTH=26\BTN_MODE=0\DFU_MODE=0. Deleting now unused module $paramod\capcnt\W=16. Deleting now unused module $paramod$a352de46d45b5f63adff3e11b85c468bb766efd0\pdm. Deleting now unused module $paramod$2f402e8506da57ea423e4c48b88211562a82053d\pdm. Deleting now unused module $paramod$a5267d9727cc292e2ca448914bb9f8cdbf595c62\picorv32. Deleting now unused module $paramod\uart_rx\DIV_WIDTH=12\GLITCH_FILTER=2. Deleting now unused module $paramod$0c9777f9a67fd17a34d59e5870cc10e6c5b1347c\soc_bram. Deleting now unused module $paramod\soc_spram\AW=14. Deleting now unused module $paramod\ice40_spi_wb\N_CS=1\WITH_IOB=0\UNIT=0. Deleting now unused module $paramod$9e50ca266fbd3700c8696e9d5d7bb3ff642c62df\ice40_rgb_wb. Deleting now unused module $paramod\usb\EPDW=32. Deleting now unused module $paramod\xclk_wb\DW=16\AW=12. Deleting now unused module $paramod\i2c_master\DW=4\TW=0\CLOCK_STRETCH=0. Deleting now unused module $paramod\pdm_lfsr\WIDTH=8\POLY=8'01110001. Deleting now unused module $paramod$f3481a50459fa1619913391c543e7a57a7d365e3\soc_base. Deleting now unused module $paramod\uart_wb\DIV_WIDTH=12\DW=32. Deleting now unused module $paramod\i2c_master_wb\DW=4\FIFO_DEPTH=0. Deleting now unused module $paramod\sr_btn_if\TICK_LOG2_DIV=3. Deleting now unused module hdb3_enc. Deleting now unused module hdb3_dec. Deleting now unused module e1_tx_phy. Deleting now unused module e1_tx_framer. Deleting now unused module e1_rx_phy. Deleting now unused module e1_rx_filter. Deleting now unused module e1_rx_deframer. Deleting now unused module e1_rx_clock_recovery. Deleting now unused module e1_crc4. <suppressed ~86 debug messages> 75.5. Executing TRIBUF pass. 75.6. Executing DEMINOUT pass (demote inout ports to input or output). Demoting inout port top.flash_cs_n to output. 75.7. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~10796 debug messages> 75.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 965 unused cells and 14470 unused wires. <suppressed ~1090 debug messages> 75.9. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 75.10. Executing OPT pass (performing simple optimizations). 75.10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~1551 debug messages> Removed a total of 517 cells. 75.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procmux$15956: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.cnt -> { 1'0 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.cnt [4:0] } Replacing known input bits on port B of cell $flatten\misc_I.\dfu_I.$procmux$12493: \misc_I.dfu_I.wb_req -> 1'1 Replacing known input bits on port B of cell $flatten\sys_mgr_I.$procmux$11673: \sys_mgr_I.rst_cnt -> { 1'1 \sys_mgr_I.rst_cnt [2:0] } Analyzing evaluation results. dead port 1/2 on $mux $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12295. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12623. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12629. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12632. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12644. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12651. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12654. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12667. dead port 1/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12677. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12679. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12682. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12691. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12694. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12702. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12704. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12707. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12768. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12770. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12773. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12855. dead port 1/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12858. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12860. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12863. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12902. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12905. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$12916. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12948. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12961. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$12974. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$13013. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13108. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13122. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13122. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13122. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13122. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13122. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13122. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13122. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13151. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13164. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13164. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13164. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13164. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13164. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13164. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13164. dead port 1/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13210. dead port 2/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13210. dead port 3/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13210. dead port 4/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13210. dead port 5/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13210. dead port 6/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13210. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13216. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13216. dead port 3/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13216. dead port 4/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13216. dead port 5/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$13216. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13249. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13249. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13249. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13249. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13249. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13249. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13249. dead port 1/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13454. dead port 2/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13454. dead port 3/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13454. dead port 4/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13454. dead port 5/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13454. dead port 6/7 on $pmux $flatten\soc_I.\cpu_I.$procmux$13454. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13518. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13537. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13537. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13537. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13537. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13537. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13537. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13537. dead port 3/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13719. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13735. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13735. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13735. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13735. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13735. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13735. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13735. dead port 4/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13897. dead port 5/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13897. dead port 6/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13897. dead port 7/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13897. dead port 8/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13897. dead port 10/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13897. dead port 11/12 on $pmux $flatten\soc_I.\cpu_I.$procmux$13897. dead port 1/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13948. dead port 2/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13948. dead port 3/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13948. dead port 4/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13948. dead port 5/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13948. dead port 7/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13948. dead port 8/9 on $pmux $flatten\soc_I.\cpu_I.$procmux$13948. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$14045. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$14045. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$14050. dead port 1/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$14054. dead port 2/5 on $pmux $flatten\soc_I.\cpu_I.$procmux$14054. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$14059. dead port 1/8 on $pmux $flatten\soc_I.\cpu_I.$procmux$14074. dead port 2/8 on $pmux $flatten\soc_I.\cpu_I.$procmux$14074. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$15205. dead port 2/2 on $mux $flatten\soc_I.\cpu_I.$procmux$15212. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15397. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15404. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15413. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15415. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15423. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15432. dead port 2/2 on $mux $flatten\i2c_I.\core_I.$procmux$15442. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12440. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10010. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10010. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10010. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10010. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10010. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10032. dead port 2/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10032. dead port 3/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10032. dead port 4/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10032. dead port 5/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10032. dead port 1/5 on $pmux $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$procmux$10066. dead port 2/5 on $pmux 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port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10066. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10096. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10096. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10096. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10096. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10108. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10108. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10108. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10108. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10108. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10126. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10126. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10126. dead port 4/5 on $pmux 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on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10218. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10218. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10231. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10231. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10231. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10231. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10231. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10246. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10246. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10246. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10246. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10246. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10263. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10263. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10263. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10263. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10263. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10282. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10282. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10282. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10282. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10303. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10303. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10303. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10303. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10326. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10326. dead port 3/5 on $pmux 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on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10407. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10407. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10407. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10407. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10438. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10438. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10438. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10438. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10438. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10471. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10471. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10471. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10471. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10471. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10506. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10506. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10506. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10546. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10546. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10546. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10546. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10546. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10556. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10556. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10556. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10556. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10556. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10570. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10570. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10570. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10570. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10570. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10586. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10586. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10586. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10586. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10586. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10606. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10606. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10606. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10606. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10630. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10630. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10630. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10630. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10630. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10658. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10658. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10658. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10658. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10658. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10690. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10690. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10690. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10690. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10690. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10726. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10726. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10733. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10733. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10733. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10733. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10733. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10744. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10744. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10744. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10744. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10744. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10766. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10766. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10766. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10766. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10766. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10800. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10800. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10800. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10800. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10830. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10830. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10830. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10830. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10830. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10842. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10842. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10842. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10842. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10842. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10860. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10860. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10860. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10860. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10868. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10868. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10868. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10868. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10868. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10894. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10894. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10894. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10894. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10894. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10952. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10952. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10952. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10952. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10952. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10965. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10965. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10965. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10965. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10965. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10980. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10980. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10980. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10980. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10980. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10997. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10997. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10997. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10997. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$10997. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11016. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11016. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11016. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11016. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11016. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11037. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11037. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11037. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11037. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11037. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11060. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11060. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11060. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11060. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11060. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11085. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11085. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11085. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11085. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11085. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11112. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11112. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11112. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11112. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11112. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11141. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11141. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11141. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11141. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11141. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11172. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11172. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11172. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11172. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11172. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11205. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11205. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11205. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11205. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11205. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11240. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11240. dead port 4/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11240. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11280. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11280. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11280. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11280. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11280. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11290. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11290. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11290. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11290. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11290. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11304. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11304. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11304. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11304. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11304. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11320. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11320. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11320. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11320. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11320. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11340. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11340. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11340. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11340. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11340. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11364. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11364. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11364. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11364. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11364. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11392. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11392. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11392. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11392. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11392. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11424. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11424. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11424. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11424. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11424. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11460. dead port 3/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11460. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11467. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11467. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11467. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11467. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11467. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11478. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11478. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11478. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11478. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11478. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11500. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11500. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11500. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11500. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11500. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11534. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11534. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11534. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11534. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11564. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11564. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11564. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11564. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11564. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11576. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11576. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11576. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11576. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11576. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11594. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11594. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11594. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11594. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11594. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11602. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11602. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11602. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11602. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11602. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11628. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11628. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11628. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11628. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$11628. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5814. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5814. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5814. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5814. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5827. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5827. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5827. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5827. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5842. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5842. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5842. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5842. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5859. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5859. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5859. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5859. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5878. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5878. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5878. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5878. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5899. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5899. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5899. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5899. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5922. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5922. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5922. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5922. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5947. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5947. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5947. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5947. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5974. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5974. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5974. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$5974. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6003. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6003. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6003. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6003. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6034. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6034. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6034. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6034. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6067. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6067. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6067. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6067. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6102. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6102. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6102. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6142. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6142. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6142. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6142. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6152. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6152. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6152. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6152. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6166. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6166. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6166. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6166. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6182. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6182. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6182. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6182. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6202. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6202. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6202. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6202. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6226. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6226. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6226. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6226. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6254. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6254. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6254. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6254. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6286. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6286. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6286. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6286. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6322. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6322. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6329. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6329. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6329. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6329. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6340. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6340. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6340. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6340. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6362. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6362. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6362. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6362. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6396. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6396. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6396. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6396. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6426. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6426. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6426. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6426. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6438. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6438. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6438. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6438. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6456. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6456. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6456. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6456. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6464. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6464. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6464. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6464. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6490. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6490. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6490. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6490. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6548. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6548. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6548. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6548. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6548. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6561. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6561. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6561. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6561. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6576. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6576. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6576. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6576. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6593. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6593. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6593. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6593. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6612. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6612. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6612. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6612. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6633. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6633. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6633. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6633. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6656. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6656. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6656. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6656. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6681. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6681. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6681. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6681. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6708. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6708. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6708. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6708. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6737. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6737. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6737. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6737. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6768. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6768. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6768. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6768. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6801. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6801. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6801. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6801. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6836. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6836. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6836. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6876. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6876. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6876. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6876. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6876. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6886. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6886. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6886. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6886. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6900. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6900. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6900. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6900. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6916. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6916. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6916. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6916. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6936. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6936. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6936. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6936. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6960. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6960. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6960. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6960. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6988. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6988. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6988. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$6988. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7020. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7020. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7020. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7020. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7056. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7056. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7063. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7063. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7063. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7063. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7063. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7074. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7074. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7074. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7074. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7096. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7096. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7096. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7096. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7130. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7130. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7130. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7130. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7160. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7160. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7160. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7160. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7172. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7172. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7172. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7172. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7190. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7190. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7190. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7190. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7198. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7198. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7198. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7198. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7198. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7224. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7224. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7224. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7224. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7282. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7282. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7282. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7282. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7282. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7295. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7295. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7295. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7295. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7310. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7310. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7310. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7310. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7327. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7327. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7327. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7327. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7346. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7346. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7346. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7346. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7367. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7367. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7367. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7367. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7390. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7390. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7390. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7390. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7390. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7415. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7415. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7415. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7415. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7415. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7442. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7442. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7442. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7442. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7471. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7471. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7471. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7471. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7502. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7502. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7502. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7502. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7535. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7535. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7535. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7535. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7570. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7570. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7570. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7610. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7610. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7610. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7610. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7610. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7620. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7620. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7620. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7620. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7634. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7634. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7634. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7634. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7650. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7650. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7650. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7650. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7670. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7670. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7670. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7670. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7694. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7694. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7694. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7694. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7694. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7722. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7722. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7722. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7722. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7754. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7754. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7754. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7754. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7790. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7790. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7797. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7797. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7797. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7797. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7797. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7808. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7808. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7808. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7808. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7830. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7830. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7830. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7830. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7830. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7864. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7864. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7864. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7864. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7894. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7894. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7894. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7894. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7906. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7906. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7906. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7906. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7924. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7924. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7924. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7924. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7932. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7932. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7932. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7932. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7932. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7958. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7958. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7958. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$7958. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8016. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8016. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8016. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8016. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8016. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8029. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8029. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8029. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8029. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8029. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8044. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8044. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8044. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8044. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8061. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8061. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8061. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8061. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8080. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8080. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8080. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8080. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8101. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8101. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8101. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8101. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8124. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8124. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8124. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8124. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8124. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8149. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8149. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8149. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8149. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8149. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8176. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8176. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8176. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8176. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8205. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8205. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8205. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8205. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8236. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8236. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8236. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8236. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8269. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8269. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8269. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8269. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8304. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8304. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8304. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8344. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8344. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8344. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8344. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8344. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8354. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8354. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8354. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8354. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8354. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8368. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8368. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8368. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8368. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8384. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8384. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8384. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8384. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8404. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8404. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8404. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8404. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8428. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8428. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8428. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8428. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8428. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8456. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8456. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8456. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8456. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8488. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8488. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8488. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8488. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8524. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8524. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8531. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8531. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8531. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8531. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8531. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8542. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8542. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8542. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8542. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8542. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8564. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8564. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8564. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8564. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8564. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8598. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8598. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8598. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8598. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8628. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8628. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8628. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8628. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8640. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8640. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8640. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8640. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8640. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8658. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8658. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8658. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8658. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8666. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8666. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8666. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8666. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8666. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8692. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8692. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8692. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8692. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8750. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8750. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8750. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8750. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8750. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8763. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8763. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8763. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8763. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8763. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8778. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8778. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8778. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8778. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8795. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8795. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8795. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8795. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8814. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8814. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8814. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8814. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8835. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8835. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8835. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8835. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8858. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8858. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8858. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8858. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8858. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8883. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8883. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8883. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8883. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8883. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8910. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8910. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8910. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8910. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8910. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8939. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8939. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8939. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8939. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8939. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8970. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8970. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8970. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$8970. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9003. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9003. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9003. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9003. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9038. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9038. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9038. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9078. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9078. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9078. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9078. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9078. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9088. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9088. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9088. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9088. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9088. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9102. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9102. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9102. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9102. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9118. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9118. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9118. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9118. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9138. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9138. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9138. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9138. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9162. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9162. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9162. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9162. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9162. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9190. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9190. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9190. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9190. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9190. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9222. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9222. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9222. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9222. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9258. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9258. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9265. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9265. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9265. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9265. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9265. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9276. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9276. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9276. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9276. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9276. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9298. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9298. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9298. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9298. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9298. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9332. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9332. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9332. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9332. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9362. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9362. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9362. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9362. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9374. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9374. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9374. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9374. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9374. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9392. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9392. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9392. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9392. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9400. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9400. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9400. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9400. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9400. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9426. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9426. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9426. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9426. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9426. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9484. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9484. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9484. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9484. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9484. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9497. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9497. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9497. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9497. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9497. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9512. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9512. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9512. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9512. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9512. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9529. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9529. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9529. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9529. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9529. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9548. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9548. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9548. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9548. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9569. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9569. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9569. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9569. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9592. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9592. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9592. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9592. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9592. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9617. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9617. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9617. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9617. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9617. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9644. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9644. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9644. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9644. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9644. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9673. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9673. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9673. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9673. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9673. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9704. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9704. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9704. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9704. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9737. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9737. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9737. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9737. dead port 1/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9772. dead port 2/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9772. dead port 3/4 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9772. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9812. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9812. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9812. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9812. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9812. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9822. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9822. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9822. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9822. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9822. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9836. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9836. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9836. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9836. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9836. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9852. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9852. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9852. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9852. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9852. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9872. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9872. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9872. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9872. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9896. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9896. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9896. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9896. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9896. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9924. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9924. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9924. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9924. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9924. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9956. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9956. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9956. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9956. dead port 1/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9992. dead port 2/3 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9992. dead port 1/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9999. dead port 2/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9999. dead port 3/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9999. dead port 4/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9999. dead port 5/5 on $pmux $flatten\soc_I.\spram_I.\spram_I.$procmux$9999. dead port 1/2 on $mux $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12295. dead port 2/2 on $mux $flatten\soc_I.\usb_I.$procmux$15317. dead port 1/2 on $mux $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5640. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11969. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11971. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11973. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11980. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11982. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11988. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11996. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11998. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12005. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12014. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12016. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12024. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12034. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12036. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12045. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12055. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12068. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12071. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12074. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12076. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12078. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12091. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12094. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12096. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12098. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12111. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12113. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12115. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12127. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12129. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12140. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12152. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12165. dead port 1/2 on $mux $flatten\misc_I.\pps_flt_I.$procmux$12485. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11760. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11767. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11775. dead port 1/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11786. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11788. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11790. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11800. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11802. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11811. dead port 2/2 on $mux $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11822. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15504. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15511. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15519. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15528. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15538. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15549. dead port 1/2 on $mux $flatten\spi_mux_I.$procmux$15562. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15564. dead port 2/2 on $mux $flatten\spi_mux_I.$procmux$15576. Removed 2334 multiplexer ports. <suppressed ~613 debug messages> 75.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $flatten\soc_I.\e1_buf_I.$reduce_or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:195$5292: { \soc_I.cpu_I.do_waitirq \soc_I.e1_buf_I.tx_pending [0] \soc_I.e1_buf_I.rx_pending [0] } Consolidated identical input bits for $mux cell $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5750: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 New ports: A=1'0, B=1'1, Y=$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] New connections: $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [7:1] = { $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13537: { \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$23570 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13719: \soc_I.cpu_I.is_sb_sh_sw New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13731: \soc_I.cpu_I.is_sb_sh_sw New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13735: { \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu $auto$opt_reduce.cc:134:opt_mux$23572 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13897: { $auto$opt_reduce.cc:134:opt_mux$23576 $auto$opt_reduce.cc:134:opt_mux$23574 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14045: $auto$opt_reduce.cc:134:opt_mux$23578 New ctrl vector for $pmux cell $flatten\i2c_I.\core_I.$procmux$15378: { $auto$opt_reduce.cc:134:opt_mux$23582 $auto$opt_reduce.cc:134:opt_mux$23580 } New ctrl vector for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15667: { } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$15277: Old ports: A=0, B=32'11111111000000000000000000000000, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN[31:0]$3520 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN[31:0]$3520 [24] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN[31:0]$3520 [31:25] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN[31:0]$3520 [23:0] } = { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN[31:0]$3520 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN[31:0]$3520 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN[31:0]$3520 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN[31:0]$3520 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN[31:0]$3520 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN[31:0]$3520 [24] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN[31:0]$3520 [24] 24'000000000000000000000000 } New ctrl vector for $mux cell $flatten\soc_I.\cpu_I.$procmux$12620: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12639: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12657: $auto$opt_reduce.cc:134:opt_mux$23584 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12938: { $flatten\soc_I.\cpu_I.$procmux$12652_CMP $auto$opt_reduce.cc:134:opt_mux$23586 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12951: { $auto$opt_reduce.cc:134:opt_mux$23588 $flatten\soc_I.\cpu_I.$procmux$12630_CMP } Consolidated identical input bits for $mux cell $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5750: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 New ports: A=1'0, B=1'1, Y=$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] New connections: $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [7:1] = { $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$12964: { $flatten\soc_I.\cpu_I.$procmux$12661_CMP $auto$opt_reduce.cc:134:opt_mux$23590 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13108: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13112: $flatten\soc_I.\cpu_I.$procmux$12641_CMP New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13118: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13122: { } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13151: $auto$opt_reduce.cc:134:opt_mux$23592 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13160: $auto$opt_reduce.cc:134:opt_mux$23594 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13164: { $auto$opt_reduce.cc:134:opt_mux$23598 $auto$opt_reduce.cc:134:opt_mux$23596 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13190: { $flatten\soc_I.\cpu_I.$procmux$12661_CMP $flatten\soc_I.\cpu_I.$procmux$12660_CMP $flatten\soc_I.\cpu_I.$procmux$12630_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13249: { \soc_I.cpu_I.is_slli_srli_srai $auto$opt_reduce.cc:134:opt_mux$23600 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13291: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4070_Y $flatten\soc_I.\cpu_I.$procmux$12661_CMP } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5750: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] New connections: $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [7:1] = { $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5750: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] New connections: $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [7:1] = { $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN[7:0]$5461 [0] } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.$procmux$15313: { $flatten\gps_uart_I.$eq$/build/gateware/cores/no2misc//rtl/uart_wb.v:171$3282_Y $flatten\soc_I.\iobuf_I.\dma_I.$eq$/build/gateware/common/rtl/wb_dma.v:164$5043_Y } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\phy_I.$procmux$5716: { $auto$opt_reduce.cc:134:opt_mux$23608 $auto$opt_reduce.cc:134:opt_mux$23606 $flatten\soc_I.\usb_I.\phy_I.$procmux$5725_CMP $flatten\soc_I.\usb_I.\phy_I.$procmux$5724_CMP $auto$opt_reduce.cc:134:opt_mux$23604 $auto$opt_reduce.cc:134:opt_mux$23602 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\phy_I.$procmux$5733: { $auto$opt_reduce.cc:134:opt_mux$23616 $auto$opt_reduce.cc:134:opt_mux$23614 $flatten\soc_I.\usb_I.\phy_I.$procmux$5742_CMP $flatten\soc_I.\usb_I.\phy_I.$procmux$5741_CMP $auto$opt_reduce.cc:134:opt_mux$23612 $auto$opt_reduce.cc:134:opt_mux$23610 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12179: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12187_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12186_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12185_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12184_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12183_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12182_CMP $auto$opt_reduce.cc:134:opt_mux$23618 } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12211: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12215_CMP $auto$opt_reduce.cc:134:opt_mux$23620 $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12212_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12222: { $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12229_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12228_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12227_CMP $auto$opt_reduce.cc:134:opt_mux$23622 $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12225_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12224_CMP $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12223_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13388: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4070_Y $flatten\soc_I.\cpu_I.$procmux$12661_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13431: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4070_Y $flatten\soc_I.\cpu_I.$procmux$12661_CMP $auto$opt_reduce.cc:134:opt_mux$23624 } New ctrl vector for $pmux cell $flatten\spi_mux_I.$procmux$15480: $auto$opt_reduce.cc:134:opt_mux$23626 New ctrl vector for $pmux cell $flatten\spi_mux_I.$procmux$15484: $auto$opt_reduce.cc:134:opt_mux$23628 New ctrl vector for $pmux cell $flatten\spi_mux_I.$procmux$15490: $auto$opt_reduce.cc:134:opt_mux$23630 Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$15259: Old ports: A=0, B=255, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_EN[31:0]$3511 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_EN[31:0]$3511 [0] New connections: $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_EN[31:0]$3511 [31:1] = { 24'000000000000000000000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_EN[31:0]$3511 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_EN[31:0]$3511 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_EN[31:0]$3511 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_EN[31:0]$3511 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_EN[31:0]$3511 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_EN[31:0]$3511 [0] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_EN[31:0]$3511 [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$15265: Old ports: A=0, B=65280, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN[31:0]$3514 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN[31:0]$3514 [8] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN[31:0]$3514 [31:9] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN[31:0]$3514 [7:0] } = { 16'0000000000000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN[31:0]$3514 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN[31:0]$3514 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN[31:0]$3514 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN[31:0]$3514 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN[31:0]$3514 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN[31:0]$3514 [8] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN[31:0]$3514 [8] 8'00000000 } Consolidated identical input bits for $mux cell $flatten\soc_I.\bram_I.$procmux$15271: Old ports: A=0, B=16711680, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN[31:0]$3517 New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN[31:0]$3517 [16] New connections: { $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN[31:0]$3517 [31:17] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN[31:0]$3517 [15:0] } = { 8'00000000 $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN[31:0]$3517 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN[31:0]$3517 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN[31:0]$3517 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN[31:0]$3517 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN[31:0]$3517 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN[31:0]$3517 [16] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN[31:0]$3517 [16] 16'0000000000000000 } New ctrl vector for $mux cell $flatten\soc_I.\cpu_I.$procmux$13112: { } New ctrl vector for $mux cell $flatten\soc_I.\cpu_I.$procmux$13136: { } Optimizing cells in module \top. Performed a total of 46 changes. 75.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~54 debug messages> Removed a total of 18 cells. 75.10.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23176 ($dff) from module top. Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22703 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22636 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22569 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22502 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22435 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22224 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22013 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21802 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21591 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21380 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21169 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20958 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20747 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20536 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20325 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20114 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19903 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19692 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19481 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19270 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19059 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18848 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18637 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18426 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18215 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18004 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17793 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17582 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17371 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17160 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16949 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16738 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16527 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16316 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16153 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16038 ($dlatch) from module top (changing to combinatorial circuit). Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$23299 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$23260 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$23260 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$23259 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$23259 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 16 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 17 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 18 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 19 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 20 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 21 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 22 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 23 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 24 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 25 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 26 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 27 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 28 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 29 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 30 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 31 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 32 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 33 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 34 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 35 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 36 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 37 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 38 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 39 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 40 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 41 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 42 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 43 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 44 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 45 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 46 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 47 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 48 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 49 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 50 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 51 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 52 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 53 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 54 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 55 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 56 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 57 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 58 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 59 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 60 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 61 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 62 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Setting constant 1-bit at position 63 on $flatten\soc_I.\cpu_I.$procdff$23257 ($dff) from module top. Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22770 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22703 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22636 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22569 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22502 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22435 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22224 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$22013 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21802 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21591 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21380 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$21169 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20958 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20747 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20536 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20325 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$20114 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19903 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19692 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19481 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19270 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$19059 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18848 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18637 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18426 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18215 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$18004 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17793 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17582 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17371 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$17160 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16949 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16738 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16527 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16316 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16153 ($dlatch) from module top (changing to combinatorial circuit). Handling always-active EN on $flatten\soc_I.\iobuf_I.\spram_I.\spram_I.$auto$proc_dlatch.cc:430:proc_dlatch$16038 ($dlatch) from module top (changing to combinatorial circuit). Setting constant 0-bit at position 0 on $flatten\soc_I.\e1_buf_I.$procdff$23208 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\e1_buf_I.$procdff$23208 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\e1_buf_I.$procdff$23208 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\e1_buf_I.$procdff$23208 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\e1_buf_I.$procdff$23208 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\e1_buf_I.$procdff$23208 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\e1_buf_I.$procdff$23208 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\e1_buf_I.$procdff$23208 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\e1_buf_I.$procdff$23202 ($dff) from module top. 75.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 31 unused cells and 687 unused wires. <suppressed ~59 debug messages> 75.10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~7 debug messages> 75.10.9. Rerunning OPT passes. (Maybe there is more to do..) 75.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~543 debug messages> 75.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $flatten\soc_I.\e1_buf_I.$reduce_or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:195$5292: { \soc_I.e1_buf_I.tx_pending [0] \soc_I.e1_buf_I.rx_pending [0] } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13061: $auto$opt_reduce.cc:134:opt_mux$23632 New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13078: { $flatten\soc_I.\cpu_I.$procmux$12661_CMP $auto$opt_reduce.cc:134:opt_mux$23634 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13145: { $flatten\soc_I.\cpu_I.$procmux$12641_CMP $flatten\soc_I.\cpu_I.$procmux$12640_CMP } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13496: { $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4070_Y $flatten\soc_I.\cpu_I.$procmux$12641_CMP $flatten\soc_I.\cpu_I.$procmux$12640_CMP $flatten\soc_I.\cpu_I.$procmux$12661_CMP $flatten\soc_I.\cpu_I.$procmux$12660_CMP $auto$opt_reduce.cc:134:opt_mux$23636 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14959: { $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:364$3667_Y $auto$opt_reduce.cc:134:opt_mux$23638 } Optimizing cells in module \top. Performed a total of 6 changes. 75.10.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 75.10.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23169 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$23425 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$23422 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$23419 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 24 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 25 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 26 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 27 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 28 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 29 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 30 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. Setting constant 0-bit at position 31 on $flatten\soc_I.\bram_I.$procdff$23416 ($dff) from module top. 75.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 9 unused wires. <suppressed ~1 debug messages> 75.10.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1 debug messages> 75.10.16. Rerunning OPT passes. (Maybe there is more to do..) 75.10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~543 debug messages> 75.10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.10.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.10.20. Executing OPT_DFF pass (perform DFF optimizations). 75.10.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 1 unused wires. <suppressed ~1 debug messages> 75.10.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.10.23. Rerunning OPT passes. (Maybe there is more to do..) 75.10.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~543 debug messages> 75.10.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.10.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.10.27. Executing OPT_DFF pass (perform DFF optimizations). 75.10.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.10.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.10.30. Finished OPT passes. (There is nothing left to do.) 75.11. Executing FSM pass (extract and optimize FSM). 75.11.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top.$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.fsm_state. Not marking top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:47$5457_EN as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.i2c_I.core_I.state. Found FSM state register top.soc_I.cpu_I.cpu_state. Not marking top.soc_I.cpu_I.mem_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.cpu_I.mem_wordsize. Not marking top.soc_I.e1_buf_I.t_chan as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.iobuf_I.dma_I.state as FSM state register: Users of register don't seem to benefit from recoding. Circuit seems to be self-resetting. Not marking top.soc_I.iobuf_I.epbam_arb_I.sel as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.iobuf_I.spram_arb_I.sel as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.phy_I.dn_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.phy_I.dp_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_eop_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_rep_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.dec_sync_state_1 as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.rx_ll_I.samp_cnt as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.usb_I.rx_pkt_I.state. Not marking top.soc_I.usb_I.trans_I.epfw_state as FSM state register: Users of register don't seem to benefit from recoding. Circuit seems to be self-resetting. Not marking top.soc_I.usb_I.tx_ll_I.out_sym as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.soc_I.usb_I.tx_ll_I.state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register top.soc_I.usb_I.tx_pkt_I.state. Not marking top.spi_mux_I.state as FSM state register: Users of register don't seem to benefit from recoding. 75.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.fsm_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23562 root of input selection tree: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$25_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.crc_I.in_valid found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15926_CMP found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$50_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$49_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.align_frame found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$27_Y found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$33_Y found state code: 3'100 found state code: 3'000 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf found state code: 3'011 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.fas_pos found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.data [6] found state code: 3'001 found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.data_match_fas found ctrl input: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.ctrl_mode_mf found state code: 3'010 found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15926_CMP found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$142_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$74_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$73_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$50_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$49_Y found ctrl output: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.align_frame ctrl inputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.data [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.data_match_fas $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.fas_pos $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$25_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$27_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$33_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.crc_I.in_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.ctrl_mode_mf } ctrl outputs: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.align_frame $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$49_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$50_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$73_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$74_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$142_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15926_CMP } transition: 3'000 10'-----0--0- -> 3'000 10'1000001100 transition: 3'000 10'-0---0--1- -> 3'000 10'1000001100 transition: 3'000 10'-1---0--1- -> 3'001 10'1001001100 transition: 3'000 10'-----1---- -> 3'000 10'1000001100 transition: 3'100 10'-----0--0- -> 3'100 10'0100001010 transition: 3'100 10'-----0--1- -> 3'100 10'0100001010 transition: 3'100 10'-----1---- -> 3'000 10'0000001010 transition: 3'010 10'-----0--0- -> 3'010 10'0010010100 transition: 3'010 10'-----00-1- -> 3'010 10'0010010100 transition: 3'010 10'---0001-1- -> 3'010 10'0010010100 transition: 3'010 10'---0101-1- -> 3'011 10'0011010100 transition: 3'010 10'---1-01-1- -> 3'000 10'0000010100 transition: 3'010 10'-----1---- -> 3'000 10'0000010100 transition: 3'001 10'-----0--0- -> 3'001 10'0001101100 transition: 3'001 10'-----00-1- -> 3'001 10'0001101100 transition: 3'001 10'0-0--01-1- -> 3'000 10'0000101100 transition: 3'001 10'1-0--01-1- -> 3'001 10'0001101100 transition: 3'001 10'-01--01-1- -> 3'000 10'0000101100 transition: 3'001 10'-11--01-10 -> 3'100 10'0100101100 transition: 3'001 10'-11--01-11 -> 3'010 10'0010101100 transition: 3'001 10'-----1---- -> 3'000 10'0000101100 transition: 3'011 10'-----0--0- -> 3'011 10'0011001101 transition: 3'011 10'-----00-1- -> 3'011 10'0011001101 transition: 3'011 10'---0-0101- -> 3'011 10'0011001101 transition: 3'011 10'---0-0111- -> 3'100 10'0100001101 transition: 3'011 10'---1-01-1- -> 3'000 10'0000001101 transition: 3'011 10'-----1---- -> 3'000 10'0000001101 Extracting FSM `\i2c_I.core_I.state' from module `\top'. found $dff cell for state register: $flatten\i2c_I.\core_I.$procdff$23461 root of input selection tree: $flatten\i2c_I.\core_I.$0\state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \blinker_I.rst found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:142$5211_Y found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:160$5215_Y found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:210$5220_Y found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:219$5223_Y found ctrl input: \i2c_I.ready found ctrl input: \i2c_I.core_I.cyc_cnt [4] found ctrl input: \i2c_I.core_I.bit_cnt [3] found state code: 3'010 found state code: 3'000 found ctrl input: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:109$5202_Y found state code: 3'001 found state code: 3'100 found state code: 3'011 found ctrl input: \i2c_I.core_I.stb found ctrl output: \i2c_I.ready found ctrl output: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:142$5211_Y found ctrl output: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:160$5215_Y found ctrl output: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:210$5220_Y found ctrl output: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:219$5223_Y ctrl inputs: { \blinker_I.rst $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:109$5202_Y \i2c_I.core_I.bit_cnt [3] \i2c_I.core_I.cyc_cnt [4] \i2c_I.core_I.stb } ctrl outputs: { \i2c_I.ready $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:219$5223_Y $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:210$5220_Y $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:160$5215_Y $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:142$5211_Y $flatten\i2c_I.\core_I.$0\state[2:0] } transition: 3'000 5'0---0 -> 3'000 8'10000000 transition: 3'000 5'0---1 -> 3'010 8'10000010 transition: 3'000 5'1---- -> 3'000 8'10000000 transition: 3'100 5'0--0- -> 3'100 8'00010100 transition: 3'100 5'00-1- -> 3'001 8'00010001 transition: 3'100 5'01-1- -> 3'000 8'00010000 transition: 3'100 5'1---- -> 3'000 8'00010000 transition: 3'010 5'0--0- -> 3'010 8'01000010 transition: 3'010 5'0--1- -> 3'011 8'01000011 transition: 3'010 5'1---- -> 3'000 8'01000000 transition: 3'001 5'0--0- -> 3'001 8'00001001 transition: 3'001 5'0-01- -> 3'010 8'00001010 transition: 3'001 5'0-11- -> 3'000 8'00001000 transition: 3'001 5'1---- -> 3'000 8'00001000 transition: 3'011 5'0--0- -> 3'011 8'00100011 transition: 3'011 5'0--1- -> 3'100 8'00100100 transition: 3'011 5'1---- -> 3'000 8'00100000 Extracting FSM `\soc_I.cpu_I.cpu_state' from module `\top'. found $dff cell for state register: $flatten\soc_I.\cpu_I.$procdff$23282 root of input selection tree: $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] found reset state: 8'10000000 (guessed from mux tree) found ctrl input: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4258_Y found ctrl input: \soc_I.pb_rst_n found state code: 8'01000000 found ctrl input: $auto$opt_reduce.cc:134:opt_mux$23632 found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12660_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12661_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12640_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12641_CMP found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4070_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4217_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4221_Y found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4199_Y found ctrl input: \soc_I.cpu_I.alu_wait found ctrl input: \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu found ctrl input: \soc_I.cpu_I.mem_done found ctrl input: \soc_I.cpu_I.is_sll_srl_sra found ctrl input: \soc_I.cpu_I.is_sb_sh_sw found state code: 8'00001000 found state code: 8'00000100 found state code: 8'00000010 found ctrl input: $auto$opt_reduce.cc:134:opt_mux$23570 found ctrl input: \soc_I.cpu_I.is_slli_srli_srai found ctrl input: \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu found state code: 8'00000001 found ctrl input: \soc_I.cpu_I.decoder_trigger found ctrl input: \soc_I.cpu_I.instr_jal found state code: 8'00100000 found state code: 8'10000000 found ctrl output: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4070_Y found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12630_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12640_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12641_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12652_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12660_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12661_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$12665_CMP ctrl inputs: { $auto$opt_reduce.cc:134:opt_mux$23570 $auto$opt_reduce.cc:134:opt_mux$23632 \soc_I.pb_rst_n $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4258_Y $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4221_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4217_Y $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4199_Y \soc_I.cpu_I.alu_wait \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu \soc_I.cpu_I.is_sll_srl_sra \soc_I.cpu_I.is_sb_sh_sw \soc_I.cpu_I.is_slli_srli_srai \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu \soc_I.cpu_I.decoder_trigger \soc_I.cpu_I.instr_jal \soc_I.cpu_I.mem_done } ctrl outputs: { $flatten\soc_I.\cpu_I.$procmux$12665_CMP $flatten\soc_I.\cpu_I.$procmux$12661_CMP $flatten\soc_I.\cpu_I.$procmux$12660_CMP $flatten\soc_I.\cpu_I.$procmux$12652_CMP $flatten\soc_I.\cpu_I.$procmux$12641_CMP $flatten\soc_I.\cpu_I.$procmux$12640_CMP $flatten\soc_I.\cpu_I.$procmux$12630_CMP $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4070_Y } transition: 8'10000000 16'--00------------ -> 8'01000000 16'1000000010000000 transition: 8'10000000 16'--10------------ -> 8'10000000 16'1000000100000000 transition: 8'10000000 16'---1------------ -> 8'10000000 16'1000000100000000 transition: 8'01000000 16'--00------------ -> 8'01000000 16'0000000010000001 transition: 8'01000000 16'--10---------0-- -> 8'01000000 16'0000000010000001 transition: 8'01000000 16'--10---------10- -> 8'00100000 16'0000000001000001 transition: 8'01000000 16'--10---------11- -> 8'01000000 16'0000000010000001 transition: 8'01000000 16'---1------------ -> 8'10000000 16'0000000100000001 transition: 8'00100000 16'--00------------ -> 8'01000000 16'0000100010000000 transition: 8'00100000 16'0-10-----0000--- -> 8'00001000 16'0000100000010000 transition: 8'00100000 16'0-10------100--- -> 8'00000010 16'0000100000000100 transition: 8'00100000 16'0-10-----1-00--- -> 8'00000100 16'0000100000001000 transition: 8'00100000 16'--10--------1--- -> 8'00000001 16'0000100000000010 transition: 8'00100000 16'--10-------1---- -> 8'00000100 16'0000100000001000 transition: 8'00100000 16'1-10------------ -> 8'00001000 16'0000100000010000 transition: 8'00100000 16'---1------------ -> 8'10000000 16'0000100100000000 transition: 8'00001000 16'--00------------ -> 8'01000000 16'0100000010000000 transition: 8'00001000 16'--10---00------- -> 8'01000000 16'0100000010000000 transition: 8'00001000 16'--10---01------0 -> 8'00001000 16'0100000000010000 transition: 8'00001000 16'--10---01------1 -> 8'01000000 16'0100000010000000 transition: 8'00001000 16'--10---1-------- -> 8'00001000 16'0100000000010000 transition: 8'00001000 16'---1------------ -> 8'10000000 16'0100000100000000 transition: 8'00000100 16'--00------------ -> 8'01000000 16'0010000010000000 transition: 8'00000100 16'--10--0--------- -> 8'00000100 16'0010000000001000 transition: 8'00000100 16'--10--1--------- -> 8'01000000 16'0010000010000000 transition: 8'00000100 16'---1------------ -> 8'10000000 16'0010000100000000 transition: 8'00000010 16'--00------------ -> 8'01000000 16'0001000010000000 transition: 8'00000010 16'--10-0---------- -> 8'00000010 16'0001000000000100 transition: 8'00000010 16'--1001---------- -> 8'00000010 16'0001000000000100 transition: 8'00000010 16'--1011---------- -> 8'01000000 16'0001000010000000 transition: 8'00000010 16'---1------------ -> 8'10000000 16'0001000100000000 transition: 8'00000001 16'--00------------ -> 8'01000000 16'0000001010000000 transition: 8'00000001 16'--10-0---------- -> 8'00000001 16'0000001000000010 transition: 8'00000001 16'--1001---------- -> 8'00000001 16'0000001000000010 transition: 8'00000001 16'--1011---------- -> 8'01000000 16'0000001010000000 transition: 8'00000001 16'---1------------ -> 8'10000000 16'0000001100000000 Extracting FSM `\soc_I.cpu_I.mem_wordsize' from module `\top'. found $dff cell for state register: $flatten\soc_I.\cpu_I.$procdff$23269 root of input selection tree: $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] found ctrl input: \soc_I.pb_rst_n found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12630_CMP found ctrl input: $flatten\soc_I.\cpu_I.$procmux$12652_CMP found ctrl input: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4070_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4217_Y found ctrl input: \soc_I.cpu_I.mem_do_rdata found ctrl input: \soc_I.cpu_I.instr_lw found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4226_Y found ctrl input: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4225_Y found state code: 2'00 found state code: 2'01 found state code: 2'10 found ctrl input: \soc_I.cpu_I.mem_do_wdata found ctrl input: \soc_I.cpu_I.instr_sw found ctrl input: \soc_I.cpu_I.instr_sh found ctrl input: \soc_I.cpu_I.instr_sb found ctrl output: $flatten\soc_I.\cpu_I.$procmux$15206_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$15213_CMP found ctrl output: $flatten\soc_I.\cpu_I.$procmux$15218_CMP ctrl inputs: { \soc_I.pb_rst_n $flatten\soc_I.\cpu_I.$procmux$12652_CMP $flatten\soc_I.\cpu_I.$procmux$12630_CMP $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4226_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4225_Y $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4217_Y $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4070_Y \soc_I.cpu_I.instr_sw \soc_I.cpu_I.instr_sh \soc_I.cpu_I.instr_sb \soc_I.cpu_I.instr_lw \soc_I.cpu_I.mem_do_wdata \soc_I.cpu_I.mem_do_rdata } ctrl outputs: { $flatten\soc_I.\cpu_I.$procmux$15218_CMP $flatten\soc_I.\cpu_I.$procmux$15213_CMP $flatten\soc_I.\cpu_I.$procmux$15206_CMP $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] } transition: 2'00 13'0------------ -> 2'00 5'10000 transition: 2'00 13'100---0------ -> 2'00 5'10000 transition: 2'00 13'1-----1------ -> 2'00 5'10000 transition: 2'00 13'11---0------- -> 2'00 5'10000 transition: 2'00 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!> transition: 2'00 13'11---1---1-0- -> 2'10 5'10010 transition: 2'00 13'11---1--1--0- -> 2'01 5'10001 transition: 2'00 13'11---1-1---0- -> 2'00 5'10000 transition: 2'00 13'11---1-----1- -> 2'00 5'10000 transition: 2'00 13'1-1--0------- -> 2'00 5'10000 transition: 2'00 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'100xx <ignored invalid transition!> transition: 2'00 13'1-1-11------0 -> 2'10 5'10010 transition: 2'00 13'1-11-1------0 -> 2'01 5'10001 transition: 2'00 13'1-1--1----1-0 -> 2'00 5'10000 transition: 2'00 13'1-1--1------1 -> 2'00 5'10000 transition: 2'10 13'0------------ -> 2'10 5'00110 transition: 2'10 13'100---0------ -> 2'10 5'00110 transition: 2'10 13'1-----1------ -> 2'00 5'00100 transition: 2'10 13'11---0------- -> 2'10 5'00110 transition: 2'10 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!> transition: 2'10 13'11---1---1-0- -> 2'10 5'00110 transition: 2'10 13'11---1--1--0- -> 2'01 5'00101 transition: 2'10 13'11---1-1---0- -> 2'00 5'00100 transition: 2'10 13'11---1-----1- -> 2'10 5'00110 transition: 2'10 13'1-1--0------- -> 2'10 5'00110 transition: 2'10 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'001xx <ignored invalid transition!> transition: 2'10 13'1-1-11------0 -> 2'10 5'00110 transition: 2'10 13'1-11-1------0 -> 2'01 5'00101 transition: 2'10 13'1-1--1----1-0 -> 2'00 5'00100 transition: 2'10 13'1-1--1------1 -> 2'10 5'00110 transition: 2'01 13'0------------ -> 2'01 5'01001 transition: 2'01 13'100---0------ -> 2'01 5'01001 transition: 2'01 13'1-----1------ -> 2'00 5'01000 transition: 2'01 13'11---0------- -> 2'01 5'01001 transition: 2'01 13'11---1-000-0- -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!> transition: 2'01 13'11---1---1-0- -> 2'10 5'01010 transition: 2'01 13'11---1--1--0- -> 2'01 5'01001 transition: 2'01 13'11---1-1---0- -> 2'00 5'01000 transition: 2'01 13'11---1-----1- -> 2'01 5'01001 transition: 2'01 13'1-1--0------- -> 2'01 5'01001 transition: 2'01 13'1-1001----0-0 -> INVALID_STATE(2'xx) 5'010xx <ignored invalid transition!> transition: 2'01 13'1-1-11------0 -> 2'10 5'01010 transition: 2'01 13'1-11-1------0 -> 2'01 5'01001 transition: 2'01 13'1-1--1----1-0 -> 2'00 5'01000 transition: 2'01 13'1-1--1------1 -> 2'01 5'01001 Extracting FSM `\soc_I.usb_I.rx_pkt_I.state' from module `\top'. found $adff cell for state register: $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23147 root of input selection tree: \soc_I.usb_I.rx_pkt_I.state_nxt found reset state: 4'0000 (from async reset) found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1408_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11999_CMP found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1394_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1391_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12079_CMP found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1345_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] found ctrl input: \soc_I.usb_I.rx_ll_I.dec_valid_1 found ctrl input: \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] found ctrl input: \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] found state code: 4'0011 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1326_Y found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1320_Y found ctrl input: \soc_I.usb_I.rx_pkt_I.llu_byte_stb found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1324_Y found state code: 4'0110 found state code: 4'0101 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1319_Y found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_valid found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_sof found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_token found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_data found ctrl input: \soc_I.usb_I.rx_pkt_I.pid_is_handshake found state code: 4'0111 found state code: 4'0100 found state code: 4'0010 found ctrl input: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1315_Y found state code: 4'0001 found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12079_CMP found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11999_CMP found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1408_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1394_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1391_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1345_Y found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] found ctrl output: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] ctrl inputs: { \soc_I.usb_I.rx_pkt_I.llu_byte_stb \soc_I.usb_I.rx_pkt_I.pid_valid \soc_I.usb_I.rx_pkt_I.pid_is_sof \soc_I.usb_I.rx_pkt_I.pid_is_token \soc_I.usb_I.rx_pkt_I.pid_is_data \soc_I.usb_I.rx_pkt_I.pid_is_handshake $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1315_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1319_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1320_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1324_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1326_Y \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] \soc_I.usb_I.rx_ll_I.dec_valid_1 } ctrl outputs: { \soc_I.usb_I.rx_pkt_I.state_nxt $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1345_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1391_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1394_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1408_Y $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11999_CMP $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12079_CMP } transition: 4'0000 14'------0------- -> 4'0000 12'000010000000 transition: 4'0000 14'------1------- -> 4'0001 12'000110000000 transition: 4'0100 14'0-------0----- -> 4'0100 12'010000010000 transition: 4'0100 14'1-------0----- -> 4'0101 12'010100010000 transition: 4'0100 14'--------1----- -> 4'0011 12'001100010000 transition: 4'0010 14'-0------------ -> 4'0011 12'001100000001 transition: 4'0010 14'-10000-------- -> 4'0011 12'001100000001 transition: 4'0010 14'-10001-------- -> 4'0110 12'011000000001 transition: 4'0010 14'-1001--------- -> 4'0111 12'011100000001 transition: 4'0010 14'-101---------- -> 4'0100 12'010000000001 transition: 4'0010 14'-11----------- -> 4'0100 12'010000000001 transition: 4'0110 14'0-------0----- -> 4'0110 12'011000000010 transition: 4'0110 14'1-------0----- -> 4'0011 12'001100000010 transition: 4'0110 14'--------10---- -> 4'0011 12'001100000010 transition: 4'0110 14'--------11---- -> 4'0000 12'000000000010 transition: 4'0001 14'0------------- -> 4'0001 12'000100100000 transition: 4'0001 14'1------------- -> 4'0010 12'001000100000 transition: 4'0101 14'0-------0----- -> 4'0101 12'010100001000 transition: 4'0101 14'1-------0----- -> 4'0110 12'011000001000 transition: 4'0101 14'--------1----- -> 4'0011 12'001100001000 transition: 4'0011 14'-------0------ -> 4'0011 12'001101000000 transition: 4'0011 14'-------1------ -> 4'0000 12'000001000000 transition: 4'0111 14'-------------0 -> 4'0111 12'011100000100 transition: 4'0111 14'-----------001 -> 4'0111 12'011100000100 transition: 4'0111 14'-----------011 -> 4'0011 12'001100000100 transition: 4'0111 14'----------01-1 -> 4'0011 12'001100000100 transition: 4'0111 14'----------11-1 -> 4'0000 12'000000000100 Extracting FSM `\soc_I.usb_I.tx_pkt_I.state' from module `\top'. found $adff cell for state register: $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23090 root of input selection tree: \soc_I.usb_I.tx_pkt_I.state_nxt found reset state: 4'0000 (from async reset) found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1559_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11750_CMP found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1558_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1560_Y found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1576_Y found ctrl input: \soc_I.usb_I.tx_pkt_I.next found state code: 4'0101 found ctrl input: $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1533_Y found state code: 4'0100 found ctrl input: \soc_I.usb_I.tx_pkt_I.pid_is_handshake found ctrl input: \soc_I.usb_I.tx_pkt_I.len [10] found state code: 4'0011 found state code: 4'0010 found ctrl input: \soc_I.usb_I.trans_I.txpkt_start_i found state code: 4'0001 found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11750_CMP found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1576_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1560_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1559_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1558_Y found ctrl output: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] ctrl inputs: { \soc_I.usb_I.trans_I.txpkt_start_i \soc_I.usb_I.tx_pkt_I.pid_is_handshake \soc_I.usb_I.tx_pkt_I.next \soc_I.usb_I.tx_pkt_I.len [10] $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1533_Y } ctrl outputs: { \soc_I.usb_I.tx_pkt_I.state_nxt $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1558_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1559_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1560_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1576_Y $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11750_CMP } transition: 4'0000 5'0---- -> 4'0000 10'0000000100 transition: 4'0000 5'1---- -> 4'0001 10'0001000100 transition: 4'0100 5'--0-- -> 4'0100 10'0100000001 transition: 4'0100 5'--1-- -> 4'0101 10'0101000001 transition: 4'0010 5'--0-- -> 4'0010 10'0010001000 transition: 4'0010 5'-010- -> 4'0011 10'0011001000 transition: 4'0010 5'-011- -> 4'0100 10'0100001000 transition: 4'0010 5'-11-- -> 4'0000 10'0000001000 transition: 4'0001 5'----- -> 4'0010 10'0010000010 transition: 4'0101 5'--0-- -> 4'0101 10'0101010000 transition: 4'0101 5'--1-- -> 4'0000 10'0000010000 transition: 4'0011 5'----0 -> 4'0011 10'0011100000 transition: 4'0011 5'----1 -> 4'0100 10'0100100000 75.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23680' from module `\top'. Optimizing FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23670' from module `\top'. Optimizing FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23665' from module `\top'. Optimizing FSM `$fsm$\soc_I.cpu_I.cpu_state$23655' from module `\top'. Removing unused input signal $auto$opt_reduce.cc:134:opt_mux$23632. Optimizing FSM `$fsm$\i2c_I.core_I.state$23648' from module `\top'. Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.fsm_state$23639' from module `\top'. Merging pattern 10'-----0--0- and 10'-----0--1- from group (1 1 10'0100001010). Merging pattern 10'-----0--1- and 10'-----0--0- from group (1 1 10'0100001010). 75.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 116 unused cells and 116 unused wires. <suppressed ~118 debug messages> 75.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.fsm_state$23639' from module `\top'. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15926_CMP. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\i2c_I.core_I.state$23648' from module `\top'. Removing unused output signal $flatten\i2c_I.\core_I.$0\state[2:0] [0]. Removing unused output signal $flatten\i2c_I.\core_I.$0\state[2:0] [1]. Removing unused output signal $flatten\i2c_I.\core_I.$0\state[2:0] [2]. Optimizing FSM `$fsm$\soc_I.cpu_I.cpu_state$23655' from module `\top'. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [0]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [1]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [2]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [3]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [4]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [5]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [6]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\cpu_state[7:0] [7]. Optimizing FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23665' from module `\top'. Removing unused output signal $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] [0]. Removing unused output signal $flatten\soc_I.\cpu_I.$0\mem_wordsize[1:0] [1]. Optimizing FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23670' from module `\top'. Removing unused output signal $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$12079_CMP. Removing unused output signal $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11999_CMP. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [0]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [1]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [2]. Removing unused output signal \soc_I.usb_I.rx_pkt_I.state_nxt [3]. Optimizing FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23680' from module `\top'. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [0]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [1]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [2]. Removing unused output signal \soc_I.usb_I.tx_pkt_I.state_nxt [3]. 75.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.fsm_state$23639' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 011 -> 1---- Recoding FSM `$fsm$\i2c_I.core_I.state$23648' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ----1 100 -> ---1- 010 -> --1-- 001 -> -1--- 011 -> 1---- Recoding FSM `$fsm$\soc_I.cpu_I.cpu_state$23655' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 10000000 -> ------1 01000000 -> -----1- 00100000 -> ----1-- 00001000 -> ---1--- 00000100 -> --1---- 00000010 -> -1----- 00000001 -> 1------ Recoding FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23665' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> --1 10 -> -1- 01 -> 1-- Recoding FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23670' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -------1 0100 -> ------1- 0010 -> -----1-- 0110 -> ----1--- 0001 -> ---1---- 0101 -> --1----- 0011 -> -1------ 0111 -> 1------- Recoding FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23680' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 0000 -> -----1 0100 -> ----1- 0010 -> ---1-- 0001 -> --1--- 0101 -> -1---- 0011 -> 1----- 75.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.fsm_state$23639' from module `top': ------------------------------------- Information on FSM $fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.fsm_state$23639 ($flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.fsm_state): Number of input signals: 10 Number of output signals: 6 Number of state bits: 5 Input signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.ctrl_mode_mf 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.crc_I.in_valid 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:191$33_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:166$27_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:143$25_Y 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf 6: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.mfa_timeout [6] 7: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.fas_pos 8: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.data_match_fas 9: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.data [6] Output signals: 0: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$142_Y 1: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$74_Y 2: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$ne$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:317$73_Y 3: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$50_Y 4: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:248$49_Y 5: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.align_frame State encoding: 0: 5'----1 <RESET STATE> 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 10'-----0--0- -> 0 6'100110 1: 0 10'-0---0--1- -> 0 6'100110 2: 0 10'-----1---- -> 0 6'100110 3: 0 10'-1---0--1- -> 3 6'100110 4: 1 10'-----1---- -> 0 6'000101 5: 1 10'-----0---- -> 1 6'000101 6: 2 10'---1-01-1- -> 0 6'001010 7: 2 10'-----1---- -> 0 6'001010 8: 2 10'-----0--0- -> 2 6'001010 9: 2 10'-----00-1- -> 2 6'001010 10: 2 10'---0001-1- -> 2 6'001010 11: 2 10'---0101-1- -> 4 6'001010 12: 3 10'0-0--01-1- -> 0 6'010110 13: 3 10'-01--01-1- -> 0 6'010110 14: 3 10'-----1---- -> 0 6'010110 15: 3 10'-11--01-10 -> 1 6'010110 16: 3 10'-11--01-11 -> 2 6'010110 17: 3 10'-----0--0- -> 3 6'010110 18: 3 10'-----00-1- -> 3 6'010110 19: 3 10'1-0--01-1- -> 3 6'010110 20: 4 10'---1-01-1- -> 0 6'000110 21: 4 10'-----1---- -> 0 6'000110 22: 4 10'---0-0111- -> 1 6'000110 23: 4 10'-----0--0- -> 4 6'000110 24: 4 10'---0-0101- -> 4 6'000110 25: 4 10'-----00-1- -> 4 6'000110 ------------------------------------- FSM `$fsm$\i2c_I.core_I.state$23648' from module `top': ------------------------------------- Information on FSM $fsm$\i2c_I.core_I.state$23648 (\i2c_I.core_I.state): Number of input signals: 5 Number of output signals: 5 Number of state bits: 5 Input signals: 0: \i2c_I.core_I.stb 1: \i2c_I.core_I.cyc_cnt [4] 2: \i2c_I.core_I.bit_cnt [3] 3: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:109$5202_Y 4: \blinker_I.rst Output signals: 0: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:142$5211_Y 1: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:160$5215_Y 2: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:210$5220_Y 3: $flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:219$5223_Y 4: \i2c_I.ready State encoding: 0: 5'----1 <RESET STATE> 1: 5'---1- 2: 5'--1-- 3: 5'-1--- 4: 5'1---- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 5'0---0 -> 0 5'10000 1: 0 5'1---- -> 0 5'10000 2: 0 5'0---1 -> 2 5'10000 3: 1 5'01-1- -> 0 5'00010 4: 1 5'1---- -> 0 5'00010 5: 1 5'0--0- -> 1 5'00010 6: 1 5'00-1- -> 3 5'00010 7: 2 5'1---- -> 0 5'01000 8: 2 5'0--0- -> 2 5'01000 9: 2 5'0--1- -> 4 5'01000 10: 3 5'0-11- -> 0 5'00001 11: 3 5'1---- -> 0 5'00001 12: 3 5'0-01- -> 2 5'00001 13: 3 5'0--0- -> 3 5'00001 14: 4 5'1---- -> 0 5'00100 15: 4 5'0--1- -> 1 5'00100 16: 4 5'0--0- -> 4 5'00100 ------------------------------------- FSM `$fsm$\soc_I.cpu_I.cpu_state$23655' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.cpu_I.cpu_state$23655 (\soc_I.cpu_I.cpu_state): Number of input signals: 15 Number of output signals: 8 Number of state bits: 7 Input signals: 0: \soc_I.cpu_I.mem_done 1: \soc_I.cpu_I.instr_jal 2: \soc_I.cpu_I.decoder_trigger 3: \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu 4: \soc_I.cpu_I.is_slli_srli_srai 5: \soc_I.cpu_I.is_sb_sh_sw 6: \soc_I.cpu_I.is_sll_srl_sra 7: \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu 8: \soc_I.cpu_I.alu_wait 9: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1810$4199_Y 10: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4217_Y 11: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1851$4221_Y 12: $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1917$4258_Y 13: \soc_I.pb_rst_n 14: $auto$opt_reduce.cc:134:opt_mux$23570 Output signals: 0: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4070_Y 1: $flatten\soc_I.\cpu_I.$procmux$12630_CMP 2: $flatten\soc_I.\cpu_I.$procmux$12640_CMP 3: $flatten\soc_I.\cpu_I.$procmux$12641_CMP 4: $flatten\soc_I.\cpu_I.$procmux$12652_CMP 5: $flatten\soc_I.\cpu_I.$procmux$12660_CMP 6: $flatten\soc_I.\cpu_I.$procmux$12661_CMP 7: $flatten\soc_I.\cpu_I.$procmux$12665_CMP State encoding: 0: 7'------1 <RESET STATE> 1: 7'-----1- 2: 7'----1-- 3: 7'---1--- 4: 7'--1---- 5: 7'-1----- 6: 7'1------ Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 15'-10------------ -> 0 8'10000000 1: 0 15'--1------------ -> 0 8'10000000 2: 0 15'-00------------ -> 1 8'10000000 3: 1 15'--1------------ -> 0 8'00000001 4: 1 15'-10---------11- -> 1 8'00000001 5: 1 15'-10---------0-- -> 1 8'00000001 6: 1 15'-00------------ -> 1 8'00000001 7: 1 15'-10---------10- -> 2 8'00000001 8: 2 15'--1------------ -> 0 8'00001000 9: 2 15'-00------------ -> 1 8'00001000 10: 2 15'010-----0000--- -> 3 8'00001000 11: 2 15'110------------ -> 3 8'00001000 12: 2 15'010-----1-00--- -> 4 8'00001000 13: 2 15'-10-------1---- -> 4 8'00001000 14: 2 15'010------100--- -> 5 8'00001000 15: 2 15'-10--------1--- -> 6 8'00001000 16: 3 15'--1------------ -> 0 8'01000000 17: 3 15'-10---01------1 -> 1 8'01000000 18: 3 15'-10---00------- -> 1 8'01000000 19: 3 15'-00------------ -> 1 8'01000000 20: 3 15'-10---01------0 -> 3 8'01000000 21: 3 15'-10---1-------- -> 3 8'01000000 22: 4 15'--1------------ -> 0 8'00100000 23: 4 15'-10--1--------- -> 1 8'00100000 24: 4 15'-00------------ -> 1 8'00100000 25: 4 15'-10--0--------- -> 4 8'00100000 26: 5 15'--1------------ -> 0 8'00010000 27: 5 15'-1011---------- -> 1 8'00010000 28: 5 15'-00------------ -> 1 8'00010000 29: 5 15'-10-0---------- -> 5 8'00010000 30: 5 15'-1001---------- -> 5 8'00010000 31: 6 15'--1------------ -> 0 8'00000010 32: 6 15'-1011---------- -> 1 8'00000010 33: 6 15'-00------------ -> 1 8'00000010 34: 6 15'-10-0---------- -> 6 8'00000010 35: 6 15'-1001---------- -> 6 8'00000010 ------------------------------------- FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23665' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.cpu_I.mem_wordsize$23665 (\soc_I.cpu_I.mem_wordsize): Number of input signals: 13 Number of output signals: 3 Number of state bits: 3 Input signals: 0: \soc_I.cpu_I.mem_do_rdata 1: \soc_I.cpu_I.mem_do_wdata 2: \soc_I.cpu_I.instr_lw 3: \soc_I.cpu_I.instr_sb 4: \soc_I.cpu_I.instr_sh 5: \soc_I.cpu_I.instr_sw 6: $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1292$4070_Y 7: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1836$4217_Y 8: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1865$4225_Y 9: $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1866$4226_Y 10: $flatten\soc_I.\cpu_I.$procmux$12630_CMP 11: $flatten\soc_I.\cpu_I.$procmux$12652_CMP 12: \soc_I.pb_rst_n Output signals: 0: $flatten\soc_I.\cpu_I.$procmux$15206_CMP 1: $flatten\soc_I.\cpu_I.$procmux$15213_CMP 2: $flatten\soc_I.\cpu_I.$procmux$15218_CMP State encoding: 0: 3'--1 1: 3'-1- 2: 3'1-- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 13'1-1--1----1-0 -> 0 3'100 1: 0 13'1-1--1------1 -> 0 3'100 2: 0 13'11---1-1---0- -> 0 3'100 3: 0 13'11---1-----1- -> 0 3'100 4: 0 13'100---0------ -> 0 3'100 5: 0 13'1-----1------ -> 0 3'100 6: 0 13'1-1--0------- -> 0 3'100 7: 0 13'11---0------- -> 0 3'100 8: 0 13'0------------ -> 0 3'100 9: 0 13'1-1-11------0 -> 1 3'100 10: 0 13'11---1---1-0- -> 1 3'100 11: 0 13'1-11-1------0 -> 2 3'100 12: 0 13'11---1--1--0- -> 2 3'100 13: 1 13'1-1--1----1-0 -> 0 3'001 14: 1 13'11---1-1---0- -> 0 3'001 15: 1 13'1-----1------ -> 0 3'001 16: 1 13'1-1-11------0 -> 1 3'001 17: 1 13'1-1--1------1 -> 1 3'001 18: 1 13'11---1---1-0- -> 1 3'001 19: 1 13'11---1-----1- -> 1 3'001 20: 1 13'100---0------ -> 1 3'001 21: 1 13'1-1--0------- -> 1 3'001 22: 1 13'11---0------- -> 1 3'001 23: 1 13'0------------ -> 1 3'001 24: 1 13'1-11-1------0 -> 2 3'001 25: 1 13'11---1--1--0- -> 2 3'001 26: 2 13'1-1--1----1-0 -> 0 3'010 27: 2 13'11---1-1---0- -> 0 3'010 28: 2 13'1-----1------ -> 0 3'010 29: 2 13'1-1-11------0 -> 1 3'010 30: 2 13'11---1---1-0- -> 1 3'010 31: 2 13'1-11-1------0 -> 2 3'010 32: 2 13'1-1--1------1 -> 2 3'010 33: 2 13'11---1--1--0- -> 2 3'010 34: 2 13'11---1-----1- -> 2 3'010 35: 2 13'100---0------ -> 2 3'010 36: 2 13'1-1--0------- -> 2 3'010 37: 2 13'11---0------- -> 2 3'010 38: 2 13'0------------ -> 2 3'010 ------------------------------------- FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23670' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.usb_I.rx_pkt_I.state$23670 (\soc_I.usb_I.rx_pkt_I.state): Number of input signals: 14 Number of output signals: 6 Number of state bits: 8 Input signals: 0: \soc_I.usb_I.rx_ll_I.dec_valid_1 1: \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3] 2: \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2] 3: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:180$1326_Y 4: $flatten\soc_I.\usb_I.\rx_pkt_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:173$1324_Y 5: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:158$1320_Y 6: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:153$1319_Y 7: $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:126$1315_Y 8: \soc_I.usb_I.rx_pkt_I.pid_is_handshake 9: \soc_I.usb_I.rx_pkt_I.pid_is_data 10: \soc_I.usb_I.rx_pkt_I.pid_is_token 11: \soc_I.usb_I.rx_pkt_I.pid_is_sof 12: \soc_I.usb_I.rx_pkt_I.pid_valid 13: \soc_I.usb_I.rx_pkt_I.llu_byte_stb Output signals: 0: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:375$1408_Y 1: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:341$1394_Y 2: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:337$1391_Y 3: $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:245$1345_Y 4: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_error[0:0] 5: $flatten\soc_I.\usb_I.\rx_pkt_I.$0\state_prev_idle[0:0] State encoding: 0: 8'-------1 <RESET STATE> 1: 8'------1- 2: 8'-----1-- 3: 8'----1--- 4: 8'---1---- 5: 8'--1----- 6: 8'-1------ 7: 8'1------- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 14'------0------- -> 0 6'100000 1: 0 14'------1------- -> 4 6'100000 2: 1 14'0-------0----- -> 1 6'000100 3: 1 14'1-------0----- -> 5 6'000100 4: 1 14'--------1----- -> 6 6'000100 5: 2 14'-101---------- -> 1 6'000000 6: 2 14'-11----------- -> 1 6'000000 7: 2 14'-10001-------- -> 3 6'000000 8: 2 14'-10000-------- -> 6 6'000000 9: 2 14'-0------------ -> 6 6'000000 10: 2 14'-1001--------- -> 7 6'000000 11: 3 14'--------11---- -> 0 6'000000 12: 3 14'0-------0----- -> 3 6'000000 13: 3 14'--------10---- -> 6 6'000000 14: 3 14'1-------0----- -> 6 6'000000 15: 4 14'1------------- -> 2 6'001000 16: 4 14'0------------- -> 4 6'001000 17: 5 14'1-------0----- -> 3 6'000010 18: 5 14'0-------0----- -> 5 6'000010 19: 5 14'--------1----- -> 6 6'000010 20: 6 14'-------1------ -> 0 6'010000 21: 6 14'-------0------ -> 6 6'010000 22: 7 14'----------11-1 -> 0 6'000001 23: 7 14'-----------011 -> 6 6'000001 24: 7 14'----------01-1 -> 6 6'000001 25: 7 14'-------------0 -> 7 6'000001 26: 7 14'-----------001 -> 7 6'000001 ------------------------------------- FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23680' from module `top': ------------------------------------- Information on FSM $fsm$\soc_I.usb_I.tx_pkt_I.state$23680 (\soc_I.usb_I.tx_pkt_I.state): Number of input signals: 5 Number of output signals: 6 Number of state bits: 6 Input signals: 0: $flatten\soc_I.\usb_I.\tx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:112$1533_Y 1: \soc_I.usb_I.tx_pkt_I.len [10] 2: \soc_I.usb_I.tx_pkt_I.next 3: \soc_I.usb_I.tx_pkt_I.pid_is_handshake 4: \soc_I.usb_I.trans_I.txpkt_start_i Output signals: 0: $flatten\soc_I.\usb_I.\tx_pkt_I.$procmux$11750_CMP 1: $flatten\soc_I.\usb_I.\tx_pkt_I.$0\ll_start[0:0] 2: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:203$1576_Y 3: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1560_Y 4: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1559_Y 5: $flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:177$1558_Y State encoding: 0: 6'-----1 <RESET STATE> 1: 6'----1- 2: 6'---1-- 3: 6'--1--- 4: 6'-1---- 5: 6'1----- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 5'0---- -> 0 6'000100 1: 0 5'1---- -> 3 6'000100 2: 1 5'--0-- -> 1 6'000001 3: 1 5'--1-- -> 4 6'000001 4: 2 5'-11-- -> 0 6'001000 5: 2 5'-011- -> 1 6'001000 6: 2 5'--0-- -> 2 6'001000 7: 2 5'-010- -> 5 6'001000 8: 3 5'----- -> 2 6'000010 9: 4 5'--1-- -> 0 6'010000 10: 4 5'--0-- -> 4 6'010000 11: 5 5'----1 -> 1 6'100000 12: 5 5'----0 -> 5 6'100000 ------------------------------------- 75.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.fsm_state$23639' from module `\top'. Mapping FSM `$fsm$\i2c_I.core_I.state$23648' from module `\top'. Mapping FSM `$fsm$\soc_I.cpu_I.cpu_state$23655' from module `\top'. Mapping FSM `$fsm$\soc_I.cpu_I.mem_wordsize$23665' from module `\top'. Mapping FSM `$fsm$\soc_I.usb_I.rx_pkt_I.state$23670' from module `\top'. Mapping FSM `$fsm$\soc_I.usb_I.tx_pkt_I.state$23680' from module `\top'. 75.12. Executing OPT pass (performing simple optimizations). 75.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~38 debug messages> 75.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~93 debug messages> Removed a total of 31 cells. 75.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$13145. dead port 2/4 on $pmux $flatten\soc_I.\cpu_I.$procmux$13245. dead port 3/6 on $pmux $flatten\soc_I.\cpu_I.$procmux$13709. dead port 1/3 on $pmux $flatten\soc_I.\cpu_I.$procmux$13894. Removed 4 multiplexer ports. <suppressed ~536 debug messages> 75.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$23589: { \soc_I.cpu_I.cpu_state [6:4] \soc_I.cpu_I.cpu_state [2:0] } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$23587: \soc_I.cpu_I.cpu_state [5:0] New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_mux$23585: { \soc_I.cpu_I.cpu_state [6] \soc_I.cpu_I.cpu_state [4:0] } Optimizing cells in module \top. Performed a total of 3 changes. 75.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.12.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\sys_mgr_I.$procdff$23054 ($adff) from module top (D = $flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1717_Y [2:0], Q = \sys_mgr_I.rst_cnt [2:0]). Adding SRST signal on $flatten\spi_mux_I.$procdff$23487 ($dff) from module top (D = \spi_mux_I.state_nxt, Q = \spi_mux_I.state, rval = 3'000). Adding EN signal on $flatten\spi_mux_I.$procdff$23478 ($dff) from module top (D = \spi_mux_I.shift_data_nxt, Q = \spi_mux_I.shift_data). Adding SRST signal on $flatten\spi_mux_I.$procdff$23475 ($dff) from module top (D = \spi_mux_I.shift_data [7], Q = \spi_mux_I.srio_dat_o, rval = 1'0). Adding EN signal on $flatten\soc_I.\wb_48m_xclk_I.$procdff$23454 ($dff) from module top (D = \soc_I.wb_48m_xclk_I.m_rdata, Q = \soc_I.wb_48m_xclk_I.m_rdata_i). Adding SRST signal on $flatten\soc_I.\wb_48m_xclk_I.$procdff$23453 ($dff) from module top (D = \soc_I.wb_48m_xclk_I.m_rdata_i, Q = \soc_I.wb_48m_xclk_I.s_rdata, rval = 16'0000000000000000). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$procdff$23022 ($dff) from module top (D = \soc_I.usb_I.tx_pkt_I.crc_16_I.state_nxt, Q = \soc_I.usb_I.tx_pkt_I.crc_16_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23088 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1549_Y [3:0], Q = \soc_I.usb_I.tx_pkt_I.shift_bit). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23087 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1555_Y, Q = \soc_I.usb_I.tx_pkt_I.shift_data). Adding SRST signal on $auto$opt_dff.cc:764:run$24217 ($dffe) from module top (D = \soc_I.usb_I.tx_pkt_I.shift_load [7], Q = \soc_I.usb_I.tx_pkt_I.shift_data [7], rval = 1'0). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23086 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$or$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:178$1562_Y, Q = \soc_I.usb_I.tx_pkt_I.shift_last_byte). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23085 ($dff) from module top (D = \soc_I.usb_I.tx_pkt_I.state [5], Q = \soc_I.usb_I.tx_pkt_I.shift_data_crc). Adding EN signal on $flatten\soc_I.\usb_I.\tx_pkt_I.$procdff$23083 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1572_Y [10:0], Q = \soc_I.usb_I.tx_pkt_I.len). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23098 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$0\state[2:0], Q = \soc_I.usb_I.tx_ll_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23096 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$and$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:95$1514_Y, Q = \soc_I.usb_I.tx_ll_I.bs_now). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23095 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1512_Y [2:0], Q = \soc_I.usb_I.tx_ll_I.bs_cnt). Adding SRST signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23094 ($dff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$xor$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:103$1520_Y, Q = \soc_I.usb_I.tx_ll_I.lvl_prev, rval = 1'1). Adding EN signal on $flatten\soc_I.\usb_I.\tx_ll_I.$procdff$23092 ($adff) from module top (D = $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11832_Y, Q = \soc_I.usb_I.tx_ll_I.out_sym). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23122 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$procmux$11913_Y, Q = \soc_I.usb_I.trans_I.mc_a_reg). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23119 ($dff) from module top (D = \soc_I.usb_I.trans_I.cel_state_i, Q = \soc_I.usb_I.trans_I.trans_cel). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23118 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:286$1446_Y, Q = \soc_I.usb_I.trans_I.trans_dir). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23117 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.token_data [10:7], Q = \soc_I.usb_I.trans_I.trans_endp). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23116 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:284$1445_Y, Q = \soc_I.usb_I.trans_I.trans_is_setup). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23113 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$0\bd_state[2:0], Q = \soc_I.usb_I.trans_I.bd_state). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23110 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:363$1457_Y, Q = \soc_I.usb_I.trans_I.ep_bd_idx_cur). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23109 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [5], Q = \soc_I.usb_I.trans_I.ep_bd_ctrl). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23108 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [4], Q = \soc_I.usb_I.trans_I.ep_bd_dual). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23107 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.p_dout_3 [2:0], Q = \soc_I.usb_I.trans_I.ep_type). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23104 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$xor$/build/gateware/cores/no2usb//rtl/usb_trans.v:401$1478_Y, Q = \soc_I.usb_I.trans_I.txpkt_pid). Adding SRST signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23101 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1488_Y, Q = \soc_I.usb_I.trans_I.bd_length, rval = 11'00000000000). Adding SRST signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23100 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1490_Y, Q = \soc_I.usb_I.trans_I.xfer_length, rval = 10'0000000000). Adding EN signal on $flatten\soc_I.\usb_I.\trans_I.$procdff$23099 ($dff) from module top (D = $flatten\soc_I.\usb_I.\trans_I.$procmux$11857_Y, Q = \soc_I.usb_I.trans_I.pkt_pid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$procdff$23021 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc_5_I.state_nxt, Q = \soc_I.usb_I.rx_pkt_I.crc_5_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$procdff$23022 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc_16_I.state_nxt, Q = \soc_I.usb_I.rx_pkt_I.crc_16_I.state). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23144 ($dff) from module top (D = { \soc_I.usb_I.rx_ll_I.dec_bit_1 \soc_I.usb_I.rx_pkt_I.data [7:1] }, Q = \soc_I.usb_I.rx_pkt_I.data). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23143 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11956_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_cnt, rval = 4'0110). Adding EN signal on $auto$opt_dff.cc:702:run$24252 ($sdff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1340_Y [3:0], Q = \soc_I.usb_I.rx_pkt_I.bit_cnt). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23142 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11951_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_eop_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24254 ($sdff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:234$1343_Y, Q = \soc_I.usb_I.rx_pkt_I.bit_eop_ok). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23141 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11946_Y, Q = \soc_I.usb_I.rx_pkt_I.crc_in_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24256 ($sdff) from module top (D = 1'0, Q = \soc_I.usb_I.rx_pkt_I.crc_in_first). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23139 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11936_Y, Q = \soc_I.usb_I.rx_pkt_I.crc16_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24258 ($sdff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc16_match, Q = \soc_I.usb_I.rx_pkt_I.crc16_ok). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23138 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$procmux$11941_Y, Q = \soc_I.usb_I.rx_pkt_I.crc5_ok, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24260 ($sdff) from module top (D = \soc_I.usb_I.rx_pkt_I.crc5_match, Q = \soc_I.usb_I.rx_pkt_I.crc5_ok). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23137 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_and$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:306$1371_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_valid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23135 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:329$1389_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_handshake). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23134 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:328$1384_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_data). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23133 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$logic_or$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:327$1381_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_token). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23132 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:307$1354_Y, Q = \soc_I.usb_I.rx_pkt_I.pid_is_sof). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23131 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.data [4:1], Q = \soc_I.usb_I.rx_pkt_I.pid). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23130 ($dff) from module top (D = { \soc_I.usb_I.rx_ll_I.dec_bit_1 \soc_I.usb_I.rx_pkt_I.data [7:1] }, Q = \soc_I.usb_I.rx_pkt_I.token_data [7:0]). Adding EN signal on $flatten\soc_I.\usb_I.\rx_pkt_I.$procdff$23129 ($dff) from module top (D = \soc_I.usb_I.rx_pkt_I.data [3:1], Q = \soc_I.usb_I.rx_pkt_I.token_data [10:8]). Adding SRST signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23156 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12222_Y, Q = \soc_I.usb_I.rx_ll_I.samp_cnt, rval = 3'101). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23154 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$and$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:115$1303_Y, Q = \soc_I.usb_I.rx_ll_I.dec_bit_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23153 ($dff) from module top (D = { \soc_I.usb_I.phy_I.dp_state [1] \soc_I.usb_I.phy_I.dn_state [1] }, Q = \soc_I.usb_I.rx_ll_I.dec_sym_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23151 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12211_Y, Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23150 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12206_Y, Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1). Adding SRST signal on $auto$opt_dff.cc:764:run$24274 ($dffe) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12196_Y, Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1, rval = 4'0000). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23149 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12189_Y, Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1). Adding SRST signal on $auto$opt_dff.cc:764:run$24276 ($dffe) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12179_Y, Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1, rval = 4'0000). Adding EN signal on $flatten\soc_I.\usb_I.\rx_ll_I.$procdff$23148 ($dff) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:183$1310_Y, Q = \soc_I.usb_I.rx_ll_I.dec_bs_skip_1). Adding EN signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23167 ($dff) from module top (D = \soc_I.usb_I.ep_status_I.dout_2, Q = \soc_I.usb_I.ep_status_I.p_dout_3). Adding EN signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23166 ($dff) from module top (D = $flatten\soc_I.\usb_I.\ep_status_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_ep_status.v:82$1276_Y, Q = \soc_I.usb_I.ep_status_I.s_dout_3). Adding SRST signal on $auto$opt_dff.cc:764:run$24280 ($dffe) from module top (D = \soc_I.usb_I.ep_status_I.dout_2, Q = \soc_I.usb_I.ep_status_I.s_dout_3, rval = 16'0000000000000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23449 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:413$3433_Y, Q = \soc_I.usb_I.sof_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23448 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:412$3430_Y, Q = \soc_I.usb_I.rst_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23447 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:414$3436_Y, Q = \soc_I.usb_I.evt_rd_ack, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23445 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:410$3424_Y, Q = \soc_I.usb_I.cr_bus_we, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23443 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:411$3427_Y, Q = \soc_I.usb_I.cel_rel, rval = 1'0). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$23442 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = \soc_I.usb_I.cr_addr). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$23441 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [7], Q = \soc_I.usb_I.cr_addr_chk). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$23440 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [12], Q = \soc_I.usb_I.cr_cel_ena). Adding EN signal on $flatten\soc_I.\usb_I.$procdff$23439 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [15], Q = \soc_I.usb_I.cr_pu_ena). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23438 ($dff) from module top (D = \soc_I.cpu_I.mem_addr [13], Q = \soc_I.usb_I.eps_bus_req, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23437 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:498$3449_Y, Q = \soc_I.usb_I.eps_bus_write, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23436 ($dff) from module top (D = $flatten\soc_I.\usb_I.$and$/build/gateware/cores/no2usb//rtl/usb.v:497$3448_Y, Q = \soc_I.usb_I.eps_bus_read, rval = 1'0). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23433 ($dff) from module top (D = $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3475_Y, Q = \soc_I.usb_I.timeout_suspend, rval = 20'11011100110110000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23432 ($dff) from module top (D = $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3479_Y, Q = \soc_I.usb_I.timeout_reset, rval = 20'10001010110100000000). Adding SRST signal on $flatten\soc_I.\usb_I.$procdff$23430 ($dff) from module top (D = \soc_I.usb_I.cr_pu_ena, Q = \soc_I.usb_I.pad_pu, rval = 1'0). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procdff$23025 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5462_DATA, Q = \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$23234 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338_Y [8:0], Q = \soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$23233 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340_Y [8:0], Q = \soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$procdff$23232 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4343_Y, Q = \soc_I.uart_I.uart_tx_fifo_I.rd_valid). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$23230 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259_Y [12], Q = \soc_I.uart_I.uart_tx_I.div_cnt [12], rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$23229 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12449_Y, Q = \soc_I.uart_I.uart_tx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$24302 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262_Y [4:0], Q = \soc_I.uart_I.uart_tx_I.bit_cnt). Adding EN signal on $flatten\soc_I.\uart_I.\uart_tx_I.$procdff$23228 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0], Q = \soc_I.uart_I.uart_tx_I.shift). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procdff$23025 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5462_DATA, Q = \soc_I.uart_I.uart_rx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$23234 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338_Y [8:0], Q = \soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$23233 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340_Y [8:0], Q = \soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$procdff$23232 ($adff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4343_Y, Q = \soc_I.uart_I.uart_rx_fifo_I.rd_valid). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$23197 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4393_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.cnt, rval = 2'11). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procdff$23196 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12283_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.state, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24312 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12283_Y, Q = \soc_I.uart_I.uart_rx_I.gf_I.state). Adding SRST signal on $flatten\soc_I.\uart_I.\uart_rx_I.$procdff$23410 ($dff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.$procmux$15248_Y, Q = \soc_I.uart_I.uart_rx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$24316 ($sdff) from module top (D = $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244_Y [4:0], Q = \soc_I.uart_I.uart_rx_I.bit_cnt). Adding EN signal on $flatten\soc_I.\uart_I.\uart_rx_I.$procdff$23409 ($dff) from module top (D = { \soc_I.uart_I.uart_rx_I.gf_I.state \soc_I.uart_I.uart_rx_I.shift [8:1] }, Q = \soc_I.uart_I.uart_rx_I.shift). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23470 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:174$3295_Y, Q = \soc_I.uart_I.ub_wr_div, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23469 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:173$3292_Y, Q = \soc_I.uart_I.ub_wr_data, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23468 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3287_Y, Q = \soc_I.uart_I.ub_rd_ctrl, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23467 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:171$3283_Y, Q = \soc_I.uart_I.ub_rd_data, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23466 ($dff) from module top (D = $flatten\soc_I.\uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:181$3302_Y, Q = \soc_I.uart_I.ub_ack, rval = 1'0). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23465 ($dff) from module top (D = { $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3307_Y [31] $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3307_Y [27:12] $flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3307_Y [7:0] }, Q = { \soc_I.uart_I.ub_rdata [31] \soc_I.uart_I.ub_rdata [27:12] \soc_I.uart_I.ub_rdata [7:0] }, rval = 25'0000000000000000000000000). Adding SRST signal on $flatten\soc_I.\uart_I.$procdff$23465 ($dff) from module top (D = { \soc_I.uart_I.urf_overflow \soc_I.uart_I.uart_tx_fifo_I.rd_empty \soc_I.uart_I.uart_tx_fifo_I.full \soc_I.uart_I.uart_div [11:8] }, Q = { \soc_I.uart_I.ub_rdata [30:28] \soc_I.uart_I.ub_rdata [11:8] }, rval = 7'0000000). Adding EN signal on $flatten\soc_I.\uart_I.$procdff$23464 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:0], Q = \soc_I.uart_I.uart_div). Adding EN signal on $flatten\soc_I.\rgb_I.$procdff$23426 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [4:0], Q = \soc_I.rgb_I.led_ctrl). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$23003 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_wmsk, Q = \soc_I.iobuf_I.spram_arb_I.m_wmsk). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$23002 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\spram_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:91$5140_Y, Q = \soc_I.iobuf_I.spram_arb_I.m_we). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$23001 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_wdata, Q = \soc_I.iobuf_I.spram_arb_I.m_wdata). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$23000 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.mux_addr, Q = \soc_I.iobuf_I.spram_arb_I.m_addr). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22999 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\spram_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:121$5153_Y, Q = \soc_I.iobuf_I.spram_arb_I.busy). Adding EN signal on $flatten\soc_I.\iobuf_I.\spram_arb_I.$procdff$22998 ($adff) from module top (D = \soc_I.iobuf_I.spram_arb_I.sel_nxt, Q = \soc_I.iobuf_I.spram_arb_I.sel). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23009 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\epbam_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:91$5088_Y, Q = \soc_I.iobuf_I.epbam_arb_I.m_we). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23008 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.mux_wdata, Q = \soc_I.iobuf_I.epbam_arb_I.m_wdata). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23007 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.mux_addr, Q = \soc_I.iobuf_I.epbam_arb_I.m_addr). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23006 ($adff) from module top (D = $flatten\soc_I.\iobuf_I.\epbam_arb_I.$reduce_or$/build/gateware/common/rtl/wb_arbiter.v:121$5099_Y, Q = \soc_I.iobuf_I.epbam_arb_I.busy). Adding EN signal on $flatten\soc_I.\iobuf_I.\epbam_arb_I.$procdff$23005 ($adff) from module top (D = \soc_I.iobuf_I.epbam_arb_I.sel_nxt, Q = \soc_I.iobuf_I.epbam_arb_I.sel). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23019 ($adff) from module top (D = \soc_I.iobuf_I.dma_I.state_nxt, Q = \soc_I.iobuf_I.dma_I.state). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23018 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:144$5032_Y, Q = \soc_I.iobuf_I.dma_I.data_reg). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23017 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$5036_Y [13:0], Q = \soc_I.iobuf_I.dma_I.m0_addr_i). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23016 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$5040_Y [8:0], Q = \soc_I.iobuf_I.dma_I.m1_addr_i). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23015 ($dff) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$5049_Y [12:0], Q = \soc_I.iobuf_I.dma_I.len). Adding SRST signal on $auto$opt_dff.cc:764:run$24355 ($dffe) from module top (D = $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5048_Y [12], Q = \soc_I.iobuf_I.dma_I.len [12], rval = 1'0). Adding EN signal on $flatten\soc_I.\iobuf_I.\dma_I.$procdff$23014 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [14], Q = \soc_I.iobuf_I.dma_I.dir). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23225 ($dff) from module top (D = \soc_I.e1_buf_I.t_nxt_chan, Q = \soc_I.e1_buf_I.t_chan). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23215 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12397_Y, Q = \soc_I.e1_buf_I.wb_wdata_byte). Adding SRST signal on $auto$opt_dff.cc:764:run$24359 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12394_Y, Q = \soc_I.e1_buf_I.wb_wdata_byte, rval = 8'00000000). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23214 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12412_Y, Q = \soc_I.e1_buf_I.wb_addr_lsb). Adding SRST signal on $auto$opt_dff.cc:764:run$24361 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12409_Y, Q = \soc_I.e1_buf_I.wb_addr_lsb, rval = 2'00). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23213 ($dff) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12427_Y, Q = \soc_I.e1_buf_I.wb_addr). Adding SRST signal on $auto$opt_dff.cc:764:run$24363 ($dffe) from module top (D = $flatten\soc_I.\e1_buf_I.$procmux$12424_Y, Q = \soc_I.e1_buf_I.wb_addr, rval = 14'00000000000000). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23212 ($dff) from module top (D = { \soc_I.e1_buf_I.buf_rx_mf [6:0] \soc_I.e1_buf_I.buf_rx_frame [3:0] \soc_I.e1_buf_I.buf_rx_ts [4:0] }, Q = \soc_I.e1_buf_I.rx_addr_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23211 ($dff) from module top (D = \soc_I.e1_buf_I.buf_rx_data [7:0], Q = \soc_I.e1_buf_I.rx_data_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23206 ($dff) from module top (D = { \soc_I.e1_buf_I.buf_tx_mf [6:0] \soc_I.e1_buf_I.buf_tx_frame [3:0] \soc_I.e1_buf_I.buf_tx_ts [4:0] }, Q = \soc_I.e1_buf_I.tx_addr_reg[0]). Adding EN signal on $flatten\soc_I.\e1_buf_I.$procdff$23204 ($dff) from module top (D = \soc_I.e1_buf_I.wb_rdata_mux, Q = \soc_I.e1_buf_I.tx_data_reg[0]). Adding SRST signal on $flatten\soc_I.\e1_I.$procdff$23191 ($dff) from module top (D = \soc_I.e1_I.bus_rdata, Q = \soc_I.e1_I.wb_rdata, rval = 16'0000000000000000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procdff$23492 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15671_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.hdb3_I.vstate, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24370 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15667_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.hdb3_I.vstate). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procdff$23491 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15651_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.hdb3_I.zcnt, rval = 2'00). Adding EN signal on $auto$opt_dff.cc:702:run$24374 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15649_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.hdb3_I.zcnt). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procdff$23490 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15596_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15616_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15627_Y }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.hdb3_I.d_neg, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$24376 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15594_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.hdb3_I.d_neg [1:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15625_Y }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.hdb3_I.d_neg). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procdff$23489 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15607_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15660_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15638_Y }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.hdb3_I.d_pos, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$24378 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15605_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.hdb3_I.d_pos [1:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15636_Y }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.hdb3_I.d_pos). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procdff$23488 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15682_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.hdb3_I.pstate, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24380 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15680_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.hdb3_I.pstate). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.\crc_I.$procdff$23568 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$14_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.crc_I.out_crc4). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procdff$23514 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:117$214_Y, Q = \soc_I.e1_buf_I.buf_tx_frame [3:0]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procdff$23513 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:128$217_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.fetch_ts_is31). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procdff$23512 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.fetch_ts_is31, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.fetch_ts_is0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procdff$23511 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$216_Y [4:0], Q = \soc_I.e1_buf_I.buf_tx_ts [4:0]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procdff$23510 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$logic_and$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:141$221_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.f_mf_last). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procdff$23509 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.f_mf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.f_mf_first). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procdff$23507 ($adff) from module top (D = 1'1, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.fetch_done). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procdff$23505 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:196$233_Y [3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.bit_cnt). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procdff$23504 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:203$235_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.shift_data). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procdff$23503 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$and$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:217$247_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.shift_at_crc). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procdff$23502 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$and$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:216$244_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.shift_at_last). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procdff$23501 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$and$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:215$240_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.crc_I.in_first). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procdff$23499 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$0\crc_smf[3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.crc_smf). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$procdff$23059 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.stage[1].l_valid, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.mf_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$procdff$23056 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$procmux$11676_Y, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.ll_raw_lo $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.pg_lo [3:0] }, rval = 5'00000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$procdff$23055 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$procmux$11682_Y, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.ll_raw_hi $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.pg_hi [3:0] }, rval = 5'00000). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$procdff$23165 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4506_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.data[1]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$procdff$23164 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4511_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$procdff$23163 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4517_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$procdff$23162 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4522_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$procdff$23161 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4528_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$procdff$23160 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4533_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$procdff$23159 ($adff) from module top (D = \soc_I.e1_buf_I.buf_tx_mf [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$procdff$23158 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4544_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.stage[4].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$procdff$23186 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4460_Y, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.data[1] [8:7] \soc_I.e1_buf_I.buf_tx_mf [6:0] }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$procdff$23185 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4465_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$procdff$23184 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4471_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$procdff$23183 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4476_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$procdff$23182 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4482_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$procdff$23181 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4487_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$procdff$23180 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [14:13] \soc_I.cpu_I.mem_wdata [6:0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$procdff$23179 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\bd_tx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4498_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.stage[4].l_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$procdff$23052 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:118$4572_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.ctx_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$procdff$23051 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:117$4569_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$procmux$11658_CMP, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$procdff$23050 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:5], Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_loopback [1] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.ctrl_loopback }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$procdff$23049 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [4], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.alarm). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$procdff$23048 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [3], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.ctrl_time_src). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$procdff$23047 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2:1], Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.ctrl_do_crc4 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_mode [0] }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$procdff$23046 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bus_rd_tx_status [0]). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$procdff$23045 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:158$4585_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.rd_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$procdff$23044 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:157$4579_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.wr_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\hdb3_I.$procdff$23495 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\hdb3_I.$procmux$15693_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.hdb3_I.pstate, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24430 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:62$445_Y [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.hdb3_I.pstate). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\hdb3_I.$procdff$23494 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\hdb3_I.$procmux$15704_Y, Q = { \soc_I.e1_I.lb_bit [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.hdb3_I.data [2:0] }, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$24436 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\hdb3_I.$procmux$15702_Y, Q = { \soc_I.e1_I.lb_bit [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.hdb3_I.data [2:0] }). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procdff$23521 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procmux$15764_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.filter_I.cnt_lo, rval = 2'00). Adding EN signal on $auto$opt_dff.cc:702:run$24438 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procmux$15764_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.filter_I.cnt_lo). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procdff$23520 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procmux$15773_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.filter_I.cnt_hi, rval = 2'00). Adding EN signal on $auto$opt_dff.cc:702:run$24442 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procmux$15773_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.filter_I.cnt_hi). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procdff$23519 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procmux$15745_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.in_stb, rval = 1'1). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procdff$23518 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procmux$15750_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.in_lo, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24447 ($sdff) from module top (D = 1'0, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.in_lo). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procdff$23517 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procmux$15755_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.in_hi, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24449 ($sdff) from module top (D = 1'0, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.in_hi). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.\crc_I.$procdff$23568 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$14_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.crc_I.out_crc4). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23565 ($dff) from module top (D = \misc_I.e1_cnt_I[0].sub_I.inc, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.crc_I.in_valid, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23564 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.data [6:0] \soc_I.e1_I.lb_bit [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.data). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23563 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:135$23_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.data_match_fas). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23561 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15903_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.bit_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24455 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:215$37_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.bit_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23560 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15908_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.bit_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24457 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:214$36_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.bit_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23559 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15913_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.bit, rval = 3'000). Adding EN signal on $auto$opt_dff.cc:702:run$24459 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$35_Y [2:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.bit). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23558 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15888_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts_is_ts31, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24461 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:227$41_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts_is_ts31). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23557 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15893_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts_is_ts0, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24463 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts_is_ts31, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts_is_ts0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23556 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15898_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts, rval = 5'00001). Adding EN signal on $auto$opt_dff.cc:702:run$24465 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$40_Y [4:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23555 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15863_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.frame_mf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24467 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:243$47_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.frame_mf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23554 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15868_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.frame_mf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24469 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.frame_mf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.frame_mf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23553 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15873_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.frame_smf_last, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24471 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:241$46_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.frame_smf_last). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23552 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15878_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.frame_smf_first, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24473 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.frame_smf_last, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.frame_smf_first). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23551 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15883_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.frame, rval = 4'0000). Adding EN signal on $auto$opt_dff.cc:702:run$24475 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$45_Y [3:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.frame). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23550 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$xor$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:262$55_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.fas_pos, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23549 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15855_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.mfa_timeout, rval = 7'0111111). Adding EN signal on $auto$opt_dff.cc:702:run$24478 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$59_Y [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.mfa_timeout). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23548 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15840_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24480 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:285$65_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_crc). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23547 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15845_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24482 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:284$64_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts0_msbs_match_mf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23546 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procmux$15850_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts0_msbs, rval = 16'1111111111111111). Adding EN signal on $auto$opt_dff.cc:702:run$24484 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts0_msbs [14:0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.data [0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts0_msbs). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23545 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.crc_I.out_crc4, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.crc_smf). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23544 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:325$87_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ep_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23543 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:326$93_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ed_nfas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23542 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:323$78_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ep_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23541 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:324$83_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ed_fas, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23540 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:340$108_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ep_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23539 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:341$113_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ed_mfa, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23538 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:338$100_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ep_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23537 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:339$105_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ed_crc, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23536 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$130_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ec_mfa, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23535 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$126_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ec_crc, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23534 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$122_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ec_nfas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23533 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$118_Y [1:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ec_fas, rval = 2'00). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23531 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$143_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.out_valid, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23530 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:396$145_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.out_last, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23529 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$and$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:395$144_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.out_first, rval = 1'1). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23527 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.ts, Q = \soc_I.e1_buf_I.buf_rx_ts [4:0], rval = 5'00000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23526 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.frame, Q = \soc_I.e1_buf_I.buf_rx_frame [3:0], rval = 4'0000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23525 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.data, Q = \soc_I.e1_buf_I.buf_rx_data [7:0], rval = 8'00000000). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$procdff$23524 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:389$142_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.aligned, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procdff$23567 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$or$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:37$16_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.enabled, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procdff$23566 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18_Y [5], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.cnt [5], rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procdff$23566 ($dff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procmux$15956_Y [4] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procmux$15956_Y [0] }, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.cnt [4] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.cnt [0] }, rval = 2'01). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procdff$23566 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procmux$15962_Y [3:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.cnt [3:1], rval = 3'111). Adding EN signal on $auto$opt_dff.cc:702:run$24523 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procmux$15962_Y [3:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.cnt [3:1]). Adding EN signal on $auto$opt_dff.cc:702:run$24522 ($sdff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18_Y [4] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18_Y [0] }, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.cnt [4] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.clock_I.cnt [0] }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$procdff$23186 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4460_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.data[1]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$procdff$23185 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4465_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$procdff$23184 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4471_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$procdff$23183 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4476_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$procdff$23182 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4482_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$procdff$23181 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4487_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$procdff$23180 ($adff) from module top (D = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.data[5] [8:7] \soc_I.e1_buf_I.buf_rx_mf [6:0] }, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$procdff$23179 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_out_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4498_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.stage[4].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$procdff$23165 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4506_Y, Q = \soc_I.e1_buf_I.buf_rx_mf [6:0]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$procdff$23164 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4511_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_in_I.stage[1].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$procdff$23163 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4517_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_in_I.data[2]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$procdff$23162 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4522_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_in_I.stage[2].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$procdff$23161 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$ternary$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:61$4528_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_in_I.data[3]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$procdff$23160 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4533_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_in_I.stage[3].l_valid). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$procdff$23159 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [6:0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_in_I.data[4]). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$procdff$23158 ($adff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\bd_rx_in_I.$or$/build/gateware/cores/no2misc//rtl/fifo_sync_shift.v:68$4544_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_in_I.stage[4].l_valid). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$procdff$23041 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:114$4612_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.crx_clear, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$procdff$23040 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:113$4609_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$procmux$11642_CMP, rval = 1'0). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$procdff$23039 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2:1], Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_mode [1] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.ctrl_mode_mf }). Adding EN signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$procdff$23038 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [0], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bus_rd_rx_status [0]). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$procdff$23037 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:149$4625_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.rd_ena, rval = 1'0). Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$procdff$23036 ($dff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$and$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:148$4619_Y, Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_in_I.wr_ena, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23405 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata, Q = \soc_I.cpu_I.mem_rdata_q). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23394 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\mem_state[1:0], Q = \soc_I.cpu_I.mem_state). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23393 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14934_Y, Q = \soc_I.cpu_I.mem_wstrb). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23392 ($dff) from module top (D = \soc_I.cpu_I.mem_la_wdata, Q = \soc_I.cpu_I.mem_wdata). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23390 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\mem_valid[0:0], Q = \soc_I.cpu_I.mem_valid). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23389 ($dff) from module top (D = \soc_I.cpu_I.mem_la_addr, Q = \soc_I.cpu_I.mem_addr). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23373 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$reduce_or$/build/gateware/common/rtl/picorv32.v:846$3775_Y, Q = \soc_I.cpu_I.is_compare, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23372 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:860$3795_Y, Q = \soc_I.cpu_I.is_alu_reg_reg). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23371 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:859$3794_Y, Q = \soc_I.cpu_I.is_alu_reg_imm). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23369 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14315_Y, Q = \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24595 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:856$3791_Y, Q = \soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23366 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$reduce_or$/build/gateware/common/rtl/picorv32.v:842$3771_Y, Q = \soc_I.cpu_I.is_lui_auipc_jal_jalr_addi_add_sub, rval = 1'0). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23365 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1091$4024_Y, Q = \soc_I.cpu_I.is_sll_srl_sra). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23364 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:858$3793_Y, Q = \soc_I.cpu_I.is_sb_sh_sw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23363 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_or$/build/gateware/common/rtl/picorv32.v:1082$4013_Y, Q = \soc_I.cpu_I.is_jalr_addi_slti_sltiu_xori_ori_andi). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23362 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1076$4004_Y, Q = \soc_I.cpu_I.is_slli_srli_srai). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23361 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:857$3792_Y, Q = \soc_I.cpu_I.is_lb_lh_lw_lbu_lhu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23359 ($dff) from module top (D = 1'0, Q = \soc_I.cpu_I.compressed_instr). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24603 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23358 ($dff) from module top (D = { \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [31] \soc_I.cpu_I.mem_rdata_latched [19:12] \soc_I.cpu_I.mem_rdata_latched [20] \soc_I.cpu_I.mem_rdata_latched [30:21] 1'0 }, Q = \soc_I.cpu_I.decoded_imm_uj). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24604 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23357 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361_Y, Q = \soc_I.cpu_I.decoded_imm). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23356 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [24:20], Q = \soc_I.cpu_I.decoded_rs2). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23355 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [19:15], Q = \soc_I.cpu_I.decoded_rs1). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23354 ($dff) from module top (D = \soc_I.cpu_I.mem_rdata_latched [11:7], Q = \soc_I.cpu_I.decoded_rd). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23350 ($dff) from module top (D = 1'0, Q = \soc_I.cpu_I.instr_retirq). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24609 ($dffe) from module top. Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23347 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1068$3971_Y, Q = \soc_I.cpu_I.instr_ecall_ebreak). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23342 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14471_Y, Q = \soc_I.cpu_I.instr_and, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24611 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1059$3940_Y, Q = \soc_I.cpu_I.instr_and). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23341 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14475_Y, Q = \soc_I.cpu_I.instr_or, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24613 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1058$3936_Y, Q = \soc_I.cpu_I.instr_or). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23340 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14479_Y, Q = \soc_I.cpu_I.instr_sra, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24615 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1057$3932_Y, Q = \soc_I.cpu_I.instr_sra). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23339 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14483_Y, Q = \soc_I.cpu_I.instr_srl, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24617 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1056$3928_Y, Q = \soc_I.cpu_I.instr_srl). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23338 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14487_Y, Q = \soc_I.cpu_I.instr_xor, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24619 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1055$3924_Y, Q = \soc_I.cpu_I.instr_xor). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23337 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14491_Y, Q = \soc_I.cpu_I.instr_sltu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24621 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1054$3920_Y, Q = \soc_I.cpu_I.instr_sltu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23336 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14495_Y, Q = \soc_I.cpu_I.instr_slt, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24623 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1053$3916_Y, Q = \soc_I.cpu_I.instr_slt). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23335 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14499_Y, Q = \soc_I.cpu_I.instr_sll, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24625 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1052$3912_Y, Q = \soc_I.cpu_I.instr_sll). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23334 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14503_Y, Q = \soc_I.cpu_I.instr_sub, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24627 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1051$3908_Y, Q = \soc_I.cpu_I.instr_sub). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23333 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14507_Y, Q = \soc_I.cpu_I.instr_add, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24629 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1050$3904_Y, Q = \soc_I.cpu_I.instr_add). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23332 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1048$3900_Y, Q = \soc_I.cpu_I.instr_srai). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23331 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1047$3896_Y, Q = \soc_I.cpu_I.instr_srli). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23330 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1046$3892_Y, Q = \soc_I.cpu_I.instr_slli). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23329 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14517_Y, Q = \soc_I.cpu_I.instr_andi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24634 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1044$3888_Y, Q = \soc_I.cpu_I.instr_andi). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23328 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14521_Y, Q = \soc_I.cpu_I.instr_ori, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24636 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1043$3886_Y, Q = \soc_I.cpu_I.instr_ori). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23327 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14525_Y, Q = \soc_I.cpu_I.instr_xori, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24638 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1042$3884_Y, Q = \soc_I.cpu_I.instr_xori). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23326 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14529_Y, Q = \soc_I.cpu_I.instr_sltiu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24640 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1041$3882_Y, Q = \soc_I.cpu_I.instr_sltiu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23325 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14533_Y, Q = \soc_I.cpu_I.instr_slti, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24642 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1040$3880_Y, Q = \soc_I.cpu_I.instr_slti). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23324 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14537_Y, Q = \soc_I.cpu_I.instr_addi, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24644 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1039$3878_Y, Q = \soc_I.cpu_I.instr_addi). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23323 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1037$3876_Y, Q = \soc_I.cpu_I.instr_sw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23322 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1036$3874_Y, Q = \soc_I.cpu_I.instr_sh). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23321 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1035$3872_Y, Q = \soc_I.cpu_I.instr_sb). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23320 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1033$3870_Y, Q = \soc_I.cpu_I.instr_lhu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23319 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1032$3868_Y, Q = \soc_I.cpu_I.instr_lbu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23318 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1031$3866_Y, Q = \soc_I.cpu_I.instr_lw). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23317 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1030$3864_Y, Q = \soc_I.cpu_I.instr_lh). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23316 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1029$3862_Y, Q = \soc_I.cpu_I.instr_lb). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23315 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14557_Y, Q = \soc_I.cpu_I.instr_bgeu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24654 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1027$3860_Y, Q = \soc_I.cpu_I.instr_bgeu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23314 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14561_Y, Q = \soc_I.cpu_I.instr_bltu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24656 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1026$3858_Y, Q = \soc_I.cpu_I.instr_bltu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23313 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14565_Y, Q = \soc_I.cpu_I.instr_bge, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24658 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1025$3856_Y, Q = \soc_I.cpu_I.instr_bge). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23312 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14569_Y, Q = \soc_I.cpu_I.instr_blt, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24660 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1024$3854_Y, Q = \soc_I.cpu_I.instr_blt). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23311 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14573_Y, Q = \soc_I.cpu_I.instr_bne, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24662 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1023$3852_Y, Q = \soc_I.cpu_I.instr_bne). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23310 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14577_Y, Q = \soc_I.cpu_I.instr_beq, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24664 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1022$3850_Y, Q = \soc_I.cpu_I.instr_beq). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23309 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:852$3782_Y, Q = \soc_I.cpu_I.instr_jalr). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23308 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:851$3779_Y, Q = \soc_I.cpu_I.instr_jal). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23307 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:850$3778_Y, Q = \soc_I.cpu_I.instr_auipc). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23306 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:849$3777_Y, Q = \soc_I.cpu_I.instr_lui). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23302 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13164_Y, Q = \soc_I.cpu_I.alu_wait, rval = 1'0). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23295 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13291_Y, Q = \soc_I.cpu_I.latched_rd, rval = 5'00010). Adding EN signal on $auto$opt_dff.cc:702:run$24673 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13291_Y, Q = \soc_I.cpu_I.latched_rd). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23294 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13317_Y, Q = \soc_I.cpu_I.latched_is_lb, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24683 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13317_Y, Q = \soc_I.cpu_I.latched_is_lb). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23293 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13330_Y, Q = \soc_I.cpu_I.latched_is_lh, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24693 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13330_Y, Q = \soc_I.cpu_I.latched_is_lh). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23292 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13343_Y, Q = \soc_I.cpu_I.latched_is_lu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24703 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13343_Y, Q = \soc_I.cpu_I.latched_is_lu). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23290 ($dff) from module top (D = \soc_I.cpu_I.compressed_instr, Q = \soc_I.cpu_I.latched_compr). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23289 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13388_Y, Q = \soc_I.cpu_I.latched_branch, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24716 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13388_Y, Q = \soc_I.cpu_I.latched_branch). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23288 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13424_Y, Q = \soc_I.cpu_I.latched_stalu, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24724 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13424_Y, Q = \soc_I.cpu_I.latched_stalu). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23287 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13431_Y, Q = \soc_I.cpu_I.latched_store, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24734 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13431_Y, Q = \soc_I.cpu_I.latched_store). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23276 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13057_Y, Q = \soc_I.cpu_I.decoder_pseudo_trigger, rval = 1'0). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23273 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13695_Y, Q = \soc_I.cpu_I.mem_do_wdata, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24745 ($sdff) from module top (D = 1'0, Q = \soc_I.cpu_I.mem_do_wdata). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23272 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13699_Y, Q = \soc_I.cpu_I.mem_do_rdata, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24747 ($sdff) from module top (D = 1'0, Q = \soc_I.cpu_I.mem_do_rdata). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23271 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13770_Y, Q = \soc_I.cpu_I.mem_do_rinst, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24749 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13770_Y, Q = \soc_I.cpu_I.mem_do_rinst). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23270 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13795_Y, Q = \soc_I.cpu_I.mem_do_prefetch, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24765 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:1552$4153_Y, Q = \soc_I.cpu_I.mem_do_prefetch). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23263 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13190_Y, Q = \soc_I.cpu_I.reg_out, rval = 1024). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23262 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13897_Y, Q = \soc_I.cpu_I.reg_op2). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23261 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13920_Y [31], Q = \soc_I.cpu_I.reg_op1 [31]). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23261 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13920_Y [30:0], Q = \soc_I.cpu_I.reg_op1 [30:0]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23260 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12532_Y, Q = \soc_I.cpu_I.reg_next_pc [31:2], rval = 30'000000000000000000000000000000). Adding EN signal on $auto$opt_dff.cc:702:run$24809 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$12521_Y, Q = \soc_I.cpu_I.reg_next_pc [31:2]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23259 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13968_Y, Q = \soc_I.cpu_I.reg_pc [31:2], rval = 30'000000000000000000000000000000). Adding EN signal on $auto$opt_dff.cc:702:run$24811 ($sdff) from module top (D = $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2], Q = \soc_I.cpu_I.reg_pc [31:2]). Adding SRST signal on $flatten\soc_I.\cpu_I.$procdff$23252 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$procmux$13273_Y, Q = \soc_I.cpu_I.trap, rval = 1'0). Adding SRST signal on $flatten\soc_I.\bridge_I.$procdff$23029 ($dff) from module top (D = \soc_I.bridge_I.wb_rdata_or, Q = \soc_I.bridge_I.wb_rdata_reg, rval = 0). Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top (D = 8'xxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_DATA [31:24], rval = 8'00000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$24815 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$24815 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$24815 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$24815 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$24815 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$24815 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$24815 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24815 ($sdff) from module top. Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top (D = 16'xxxxxxxxxxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_DATA [31:16], rval = 16'0000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$24816 ($sdff) from module top. Adding SRST signal on $flatten\soc_I.\bram_I.$procdff$23415 ($dff) from module top (D = 24'xxxxxxxxxxxxxxxxxxxxxxxx, Q = $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_DATA [31:8], rval = 24'000000000000000000000000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$24817 ($sdff) from module top. Adding SRST signal on $flatten\misc_I.\pps_flt_I.$procdff$23240 ($dff) from module top (D = $flatten\misc_I.\pps_flt_I.$procmux$12470_Y, Q = \misc_I.pps_flt_I.state, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24818 ($sdff) from module top (D = 1'1, Q = \misc_I.pps_flt_I.state). Adding SRST signal on $flatten\misc_I.\pdm_e1_I[1].$procdff$23250 ($dff) from module top (D = $flatten\misc_I.\pdm_e1_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4274_Y, Q = \misc_I.pdm_e1_I[1].acc, rval = 9'000000000). Adding SRST signal on $flatten\misc_I.\pdm_e1_I[0].$procdff$23250 ($dff) from module top (D = $flatten\misc_I.\pdm_e1_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4274_Y, Q = \misc_I.pdm_e1_I[0].acc, rval = 9'000000000). Adding SRST signal on $flatten\misc_I.\pdm_clk_I[1].\lfsr_I.$procdff$23462 ($dff) from module top (D = { \misc_I.pdm_clk_I[1].lfsr_I.fb \misc_I.pdm_clk_I[1].lfsr_I.out [7:1] }, Q = \misc_I.pdm_clk_I[1].lfsr_I.out, rval = 8'00000001). Adding SRST signal on $flatten\misc_I.\pdm_clk_I[1].$procdff$23249 ($dff) from module top (D = $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4279_Y, Q = \misc_I.pdm_clk_I[1].acc, rval = 13'0000000000000). Adding SRST signal on $flatten\misc_I.\pdm_clk_I[0].\lfsr_I.$procdff$23462 ($dff) from module top (D = { \misc_I.pdm_clk_I[0].lfsr_I.fb \misc_I.pdm_clk_I[0].lfsr_I.out [7:1] }, Q = \misc_I.pdm_clk_I[0].lfsr_I.out, rval = 8'00000001). Adding SRST signal on $flatten\misc_I.\pdm_clk_I[0].$procdff$23249 ($dff) from module top (D = $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4279_Y, Q = \misc_I.pdm_clk_I[0].acc, rval = 13'0000000000000). Adding SRST signal on $flatten\misc_I.\dfu_I.\btn_flt_I.$procdff$22995 ($dff) from module top (D = $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5625_Y, Q = \misc_I.dfu_I.btn_flt_I.state, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24826 ($sdff) from module top (D = 1'1, Q = \misc_I.dfu_I.btn_flt_I.state). Adding EN signal on $flatten\misc_I.\dfu_I.$procdff$23244 ($adff) from module top (D = $flatten\misc_I.\dfu_I.$procmux$12496_Y, Q = \misc_I.dfu_I.wb_sel). Adding EN signal on $flatten\misc_I.\dfu_I.$procdff$23243 ($adff) from module top (D = $flatten\misc_I.\dfu_I.$procmux$12501_Y, Q = \misc_I.dfu_I.rst_req). Adding SRST signal on $flatten\misc_I.$procdff$23074 ($dff) from module top (D = { $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:126$1634_Y $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:125$1633_Y }, Q = \misc_I.bus_we_pdm_e1, rval = 2'00). Adding SRST signal on $flatten\misc_I.$procdff$23073 ($dff) from module top (D = { $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:124$1632_Y $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:123$1631_Y }, Q = \misc_I.bus_we_pdm_clk, rval = 2'00). Adding SRST signal on $flatten\misc_I.$procdff$23072 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:122$1630_Y, Q = \misc_I.bus_we_led, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$23071 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:121$1629_Y, Q = \misc_I.bus_we_gpio, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$23070 ($dff) from module top (D = $flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:120$1628_Y, Q = \misc_I.bus_we_boot, rval = 1'0). Adding SRST signal on $flatten\misc_I.$procdff$23069 ($dff) from module top (D = $flatten\misc_I.$procmux$11708_Y, Q = \misc_I.wb_rdata, rval = 0). Adding EN signal on $flatten\misc_I.$procdff$23068 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [3:0], Q = \misc_I.gpio_out). Adding EN signal on $flatten\misc_I.$procdff$23067 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [11:8], Q = \misc_I.gpio_oe). Adding EN signal on $flatten\misc_I.$procdff$23066 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [8:0], Q = \misc_I.e1_led). Adding EN signal on $flatten\misc_I.$procdff$23065 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [31] \soc_I.cpu_I.mem_wdata [7:0] }, Q = \misc_I.pdm_e1[1]). Adding EN signal on $flatten\misc_I.$procdff$23064 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [31] \soc_I.cpu_I.mem_wdata [7:0] }, Q = \misc_I.pdm_e1[0]). Adding EN signal on $flatten\misc_I.$procdff$23063 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [31] \soc_I.cpu_I.mem_wdata [11:0] }, Q = \misc_I.pdm_clk[1]). Adding EN signal on $flatten\misc_I.$procdff$23062 ($adff) from module top (D = { \soc_I.cpu_I.mem_wdata [31] \soc_I.cpu_I.mem_wdata [11:0] }, Q = \misc_I.pdm_clk[0]). Adding EN signal on $flatten\misc_I.$procdff$23061 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [2], Q = \misc_I.boot_now). Adding EN signal on $flatten\misc_I.$procdff$23060 ($adff) from module top (D = \soc_I.cpu_I.mem_wdata [1:0], Q = \misc_I.boot_sel). Adding EN signal on $flatten\i2c_I.\core_I.$procdff$23460 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [13:12], Q = \i2c_I.core_I.cmd_cur). Adding SRST signal on $flatten\i2c_I.\core_I.$procdff$23459 ($dff) from module top (D = $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5208_Y [4:0], Q = \i2c_I.core_I.cyc_cnt, rval = 5'00000). Adding EN signal on $flatten\i2c_I.\core_I.$procdff$23458 ($dff) from module top (D = $flatten\i2c_I.\core_I.$0\bit_cnt[3:0], Q = \i2c_I.core_I.bit_cnt). Adding EN signal on $flatten\i2c_I.\core_I.$procdff$23457 ($dff) from module top (D = $flatten\i2c_I.\core_I.$0\data_reg[8:0], Q = \i2c_I.core_I.data_reg). Adding SRST signal on $flatten\i2c_I.\core_I.$procdff$23456 ($dff) from module top (D = $flatten\i2c_I.\core_I.$procmux$15368_Y, Q = \i2c_I.core_I.scl_oe, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24855 ($sdff) from module top (D = $flatten\i2c_I.\core_I.$procmux$15366_Y, Q = \i2c_I.core_I.scl_oe). Adding SRST signal on $flatten\i2c_I.\core_I.$procdff$23455 ($dff) from module top (D = $flatten\i2c_I.\core_I.$procmux$15358_Y, Q = \i2c_I.core_I.sda_oe, rval = 1'0). Adding EN signal on $auto$opt_dff.cc:702:run$24861 ($sdff) from module top (D = $flatten\i2c_I.\core_I.$procmux$15356_Y, Q = \i2c_I.core_I.sda_oe). Adding SRST signal on $flatten\i2c_I.$procdff$23472 ($dff) from module top (D = { \i2c_I.ready \i2c_I.ready \i2c_I.core_I.data_reg [0] \i2c_I.core_I.data_reg [8:1] }, Q = { \i2c_I.wb_rdata [31:30] \i2c_I.wb_rdata [8:0] }, rval = 11'00000000000). Adding EN signal on $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procdff$23025 ($dff) from module top (D = $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5462_DATA, Q = \gps_uart_I.uart_tx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\gps_uart_I.\uart_tx_fifo_I.$procdff$23234 ($adff) from module top (D = $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338_Y [8:0], Q = \gps_uart_I.uart_tx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\gps_uart_I.\uart_tx_fifo_I.$procdff$23233 ($adff) from module top (D = $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340_Y [8:0], Q = \gps_uart_I.uart_tx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\gps_uart_I.\uart_tx_fifo_I.$procdff$23232 ($adff) from module top (D = $flatten\gps_uart_I.\uart_tx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4343_Y, Q = \gps_uart_I.uart_tx_fifo_I.rd_valid). Adding SRST signal on $flatten\gps_uart_I.\uart_tx_I.$procdff$23230 ($dff) from module top (D = $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259_Y [12], Q = \gps_uart_I.uart_tx_I.div_cnt [12], rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.\uart_tx_I.$procdff$23229 ($dff) from module top (D = $flatten\gps_uart_I.\uart_tx_I.$procmux$12449_Y, Q = \gps_uart_I.uart_tx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$24875 ($sdff) from module top (D = $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262_Y [4:0], Q = \gps_uart_I.uart_tx_I.bit_cnt). Adding EN signal on $flatten\gps_uart_I.\uart_tx_I.$procdff$23228 ($adff) from module top (D = $flatten\gps_uart_I.\uart_tx_I.$0\shift[9:0], Q = \gps_uart_I.uart_tx_I.shift). Adding EN signal on $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procdff$23025 ($dff) from module top (D = $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5462_DATA, Q = \gps_uart_I.uart_rx_fifo_I.ram_I.rd_data). Adding EN signal on $flatten\gps_uart_I.\uart_rx_fifo_I.$procdff$23234 ($adff) from module top (D = $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338_Y [8:0], Q = \gps_uart_I.uart_rx_fifo_I.ram_wr_addr). Adding EN signal on $flatten\gps_uart_I.\uart_rx_fifo_I.$procdff$23233 ($adff) from module top (D = $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340_Y [8:0], Q = \gps_uart_I.uart_rx_fifo_I.ram_rd_addr). Adding EN signal on $flatten\gps_uart_I.\uart_rx_fifo_I.$procdff$23232 ($adff) from module top (D = $flatten\gps_uart_I.\uart_rx_fifo_I.$not$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:114$4343_Y, Q = \gps_uart_I.uart_rx_fifo_I.rd_valid). Adding SRST signal on $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procdff$23197 ($dff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4393_Y, Q = \gps_uart_I.uart_rx_I.gf_I.cnt, rval = 2'11). Adding SRST signal on $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procdff$23196 ($dff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12283_Y, Q = \gps_uart_I.uart_rx_I.gf_I.state, rval = 1'1). Adding EN signal on $auto$opt_dff.cc:702:run$24885 ($sdff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12283_Y, Q = \gps_uart_I.uart_rx_I.gf_I.state). Adding SRST signal on $flatten\gps_uart_I.\uart_rx_I.$procdff$23410 ($dff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.$procmux$15248_Y, Q = \gps_uart_I.uart_rx_I.bit_cnt, rval = 5'01000). Adding EN signal on $auto$opt_dff.cc:702:run$24889 ($sdff) from module top (D = $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244_Y [4:0], Q = \gps_uart_I.uart_rx_I.bit_cnt). Adding EN signal on $flatten\gps_uart_I.\uart_rx_I.$procdff$23409 ($dff) from module top (D = { \gps_uart_I.uart_rx_I.gf_I.state \gps_uart_I.uart_rx_I.shift [8:1] }, Q = \gps_uart_I.uart_rx_I.shift). Adding SRST signal on $flatten\gps_uart_I.$procdff$23470 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:174$3295_Y, Q = \gps_uart_I.ub_wr_div, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23469 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:173$3292_Y, Q = \gps_uart_I.ub_wr_data, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23468 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3287_Y, Q = \gps_uart_I.ub_rd_ctrl, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23467 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:171$3283_Y, Q = \gps_uart_I.ub_rd_data, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23466 ($dff) from module top (D = $flatten\gps_uart_I.$and$/build/gateware/cores/no2misc//rtl/uart_wb.v:181$3302_Y, Q = \gps_uart_I.ub_ack, rval = 1'0). Adding SRST signal on $flatten\gps_uart_I.$procdff$23465 ($dff) from module top (D = { \gps_uart_I.urf_overflow \gps_uart_I.uart_tx_fifo_I.rd_empty \gps_uart_I.uart_tx_fifo_I.full \gps_uart_I.uart_div [11:8] }, Q = { \gps_uart_I.ub_rdata [30:28] \gps_uart_I.ub_rdata [11:8] }, rval = 7'0000000). Adding SRST signal on $flatten\gps_uart_I.$procdff$23465 ($dff) from module top (D = { $flatten\gps_uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3307_Y [31] $flatten\gps_uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3307_Y [27:12] $flatten\gps_uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3307_Y [7:0] }, Q = { \gps_uart_I.ub_rdata [31] \gps_uart_I.ub_rdata [27:12] \gps_uart_I.ub_rdata [7:0] }, rval = 25'0000000000000000000000000). Adding EN signal on $flatten\gps_uart_I.$procdff$23464 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:0], Q = \gps_uart_I.uart_div). 75.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 478 unused cells and 547 unused wires. <suppressed ~481 debug messages> 75.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~29 debug messages> 75.12.9. Rerunning OPT passes. (Maybe there is more to do..) 75.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~223 debug messages> 75.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~81 debug messages> Removed a total of 27 cells. 75.12.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24715 ($dffe) from module top. 75.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 31 unused wires. <suppressed ~2 debug messages> 75.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1 debug messages> 75.12.16. Rerunning OPT passes. (Maybe there is more to do..) 75.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~222 debug messages> 75.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.12.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.12.20. Executing OPT_DFF pass (perform DFF optimizations). 75.12.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 1 unused wires. <suppressed ~1 debug messages> 75.12.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.12.23. Rerunning OPT passes. (Maybe there is more to do..) 75.12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~222 debug messages> 75.12.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.12.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.12.27. Executing OPT_DFF pass (perform DFF optimizations). 75.12.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.12.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.12.30. Finished OPT passes. (There is nothing left to do.) 75.13. Executing WREDUCE pass (reducing word size of cells). Removed top 24 address bits (of 32) from memory init port top.$flatten\soc_I.\bram_I.$meminit$\mem$/build/gateware/common/rtl/soc_bram.v:0$3530 (soc_I.bram_I.mem). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24579 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24689 ($ne). Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24677 ($ne). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23769 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24575 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24728 ($ne). Removed top 1 bits (of 6) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24753 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23796 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23792 ($eq). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23777 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23773 ($eq). Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23722 ($eq). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24786 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24344 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24346 ($ne). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24554 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24348 ($ne). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24105 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24109 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24144 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24174 ($eq). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23743 ($eq). Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$24205 ($eq). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23711 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$eq$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:233$5319 ($eq). Removed top 26 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_buf_I.$shiftx$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5330 ($shiftx). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5337 ($shl). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5339 ($and). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_buf_I.$ne$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:253$5357 ($ne). Removed top 1 bits (of 4) from mux cell top.$flatten\soc_I.\e1_buf_I.$procmux$12309 ($mux). Removed cell top.$flatten\soc_I.\e1_buf_I.$procmux$12394 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\e1_I.$eq$/build/gateware/cores/no2e1//rtl/e1_wb.v:149$5376 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12 ($mux). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$14 ($xor). Removed top 1 bits (of 16) from FF cell top.$auto$opt_dff.cc:764:run$24485 ($sdffe). Removed top 1 bits (of 6) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23917 ($eq). Removed top 1 bits (of 6) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23904 ($eq). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$130 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$126 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$122 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$118 ($add). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.\crc_I.$and$/build/gateware/cores/no2e1//rtl/e1_crc4.v:35$6 ($and). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:284$64 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$59 ($sub). Removed top 25 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$59 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$45 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$45 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$40 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$40 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$35 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$35 ($add). Removed cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procmux$15770 ($mux). Removed cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$procmux$15761 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$167 ($sub). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$167 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$163 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$163 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$158 ($sub). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$158 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$154 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$154 ($add). Removed top 2 bits (of 6) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procmux$15962 ($mux). Removed top 2 bits (of 6) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procmux$15959 ($mux). Removed top 5 bits (of 6) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procmux$15956 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18 ($sub). Removed top 26 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:62$445 ($xor). Removed top 31 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_dec.v:62$445 ($xor). Removed top 1 bits (of 2) from FF cell top.$auto$opt_dff.cc:764:run$24546 ($adffe). Removed top 2 bits (of 6) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$eq$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:135$22 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$206 ($sub). Removed top 26 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$206 ($sub). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12 ($mux). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.\crc_I.$xor$/build/gateware/cores/no2e1//rtl/e1_crc4.v:40$14 ($xor). Removed cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$procmux$15709 ($mux). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.\crc_I.$and$/build/gateware/cores/no2e1//rtl/e1_crc4.v:35$6 ($and). Removed top 28 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:196$233 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:196$231 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:196$231 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$216 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$216 ($add). Removed top 27 bits (of 32) from mux cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$208 ($mux). Removed cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$procmux$15678 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$462 ($add). Removed top 30 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$462 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:106$457 ($xor). Removed top 31 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:106$457 ($xor). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:103$456 ($xor). Removed top 31 bits (of 32) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$xor$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:103$456 ($xor). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.$or$/build/gateware/common/rtl/soc_iobuf.v:250$2648 ($or). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5709 ($mux). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5706 ($mux). Removed cell top.$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5702 ($mux). Removed top 20 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:176$5049 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5048 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5048 ($sub). Removed top 23 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:159$5040 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5038 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5038 ($add). Removed top 18 bits (of 32) from mux cell top.$flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:155$5036 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5034 ($add). Removed top 18 bits (of 32) from port Y of cell top.$flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5034 ($add). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5748_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5747_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5746_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5745_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5744_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5743_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5742_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5731_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5730_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5729_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5728_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5727_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5726_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\phy_I.$procmux$5725_CMP0 ($eq). Removed cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11851 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11835_CMP0 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1512 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1510 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1510 ($add). Removed top 30 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1506 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1506 ($add). Removed top 29 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1506 ($add). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4953 ($mux). Removed top 1 bits (of 7) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23891 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1572 ($sub). Removed top 21 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1572 ($sub). Removed top 21 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1572 ($sub). Removed top 21 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1571 ($mux). Removed top 1 bits (of 8) from mux cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:172$1555 ($mux). Removed top 28 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1549 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1549 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1549 ($sub). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\tx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:137$1536 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12229_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12228_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12227_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12214_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12203_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12202_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12201_CMP0 ($eq). Removed top 3 bits (of 4) from mux cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12194 ($mux). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12186_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12185_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12184_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\rx_ll_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_ll.v:98$1291 ($eq). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4953 ($mux). Removed top 1 bits (of 16) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$eq$/build/gateware/cores/no2usb//rtl/usb_crc.v:44$4956 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4966 ($mux). Removed top 2 bits (of 5) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$xor$/build/gateware/cores/no2usb//rtl/usb_crc.v:38$4967 ($xor). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:313$1365 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:311$1361 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:308$1355 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$eq$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:307$1354 ($eq). Removed top 29 bits (of 32) from port A of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1340 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1340 ($sub). Removed top 28 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1340 ($sub). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11916_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11893 ($mux). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$procmux$11891_CMP0 ($eq). Removed cell top.$flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:375$1467 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:303$1449 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:207$1427 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:206$1426 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:205$1425 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:204$1424 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:203$1423 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:202$1422 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$eq$/build/gateware/cores/no2usb//rtl/usb_trans.v:201$1421 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1420 ($add). Removed top 24 bits (of 32) from port Y of cell top.$flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1420 ($add). Removed top 24 bits (of 32) from mux cell top.$flatten\soc_I.\uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3307 ($mux). Removed top 1 bits (of 5) from FF cell top.$auto$opt_dff.cc:764:run$24331 ($adffe). Removed top 1 bits (of 13) from mux cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12455 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12444 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259 ($sub). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5752 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5754 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$procdff$23028 ($dff). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338 ($add). Removed top 1 bits (of 10) from port B of cell top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4327 ($eq). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12280 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5241 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5241 ($sub). Removed top 21 bits (of 32) from port A of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240 ($sub). Removed top 20 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240 ($sub). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5752 ($mux). Removed cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5754 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$procdff$23028 ($dff). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338 ($add). Removed top 1 bits (of 10) from port B of cell top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4327 ($eq). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15261 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15263 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15267 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15269 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15273 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15275 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15279 ($mux). Removed cell top.$flatten\soc_I.\bram_I.$procmux$15281 ($mux). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$23416 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$23419 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$23422 ($dff). Removed top 7 bits (of 8) from FF cell top.$flatten\soc_I.\bram_I.$procdff$23425 ($dff). Removed top 24 bits (of 32) from port A of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5425 ($or). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5427 ($or). Removed top 16 bits (of 32) from port B of cell top.$flatten\soc_I.\bridge_I.$or$/build/gateware/common/rtl/soc_picorv32_bridge.v:152$5431 ($or). Removed top 3 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5438 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5439 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5440 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5441 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5442 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5443 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\bridge_I.$eq$/build/gateware/common/rtl/soc_picorv32_bridge.v:102$5444 ($eq). Removed top 3 bits (of 4) from port A of cell top.$flatten\soc_I.\cpu_I.$shl$/build/gateware/common/rtl/picorv32.v:403$3699 ($shl). Removed top 30 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:601$3758 ($mux). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:849$3777 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:850$3778 ($eq). Removed top 5 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:857$3792 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:858$3793 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:859$3794 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:860$3795 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1023$3851 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1031$3865 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1041$3881 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1048$3899 ($eq). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$4072 ($add). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$4149 ($add). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4200 ($ge). Removed top 29 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4208 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4208 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4215 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4215 ($sub). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12919 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$12922 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13186 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13188 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13193 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13243 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13263 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13286 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13289 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13313 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13315 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13326 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13328 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13339 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13341 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13386 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13419 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13422 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13438 ($mux). Removed top 1 bits (of 2) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23838 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13707 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13712 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13719 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13735 ($pmux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13768 ($mux). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23829 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13916 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13918 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13924 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13926 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$13941 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14062 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14904 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14908 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14914 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\cpu_I.$procmux$14916_CMP0 ($eq). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14917 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14923 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14957 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14967 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14969 ($mux). Removed cell top.$flatten\soc_I.\cpu_I.$procmux$14973 ($mux). Removed top 24 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$procmux$15200 ($pmux). Removed top 1 bits (of 2) from port B of cell top.$flatten\soc_I.\cpu_I.$procmux$15203_CMP0 ($eq). Removed top 16 bits (of 32) from mux cell top.$flatten\soc_I.\cpu_I.$procmux$15209 ($pmux). Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23820 ($eq). Removed top 11 bits (of 31) from FF cell top.$auto$opt_dff.cc:764:run$24604 ($dffe). Removed top 1 bits (of 8) from port B of cell top.$flatten\misc_I.\pdm_clk_I[1].\lfsr_I.$and$/build/gateware/cores/no2misc//rtl/pdm.v:130$5196 ($and). Removed top 1 bits (of 8) from port B of cell top.$flatten\misc_I.\pdm_clk_I[0].\lfsr_I.$and$/build/gateware/cores/no2misc//rtl/pdm.v:130$5196 ($and). Removed top 25 bits (of 26) from port B of cell top.$flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4288 ($add). Removed top 3 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11714_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11713_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11712_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11711_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11710_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\misc_I.$procmux$11709_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:122$1630 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\misc_I.$eq$/build/gateware/icE1usb/rtl/misc.v:121$1629 ($eq). Removed top 3 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23703 ($eq). Removed top 1 bits (of 10) from port B of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4327 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340 ($add). Removed top 7 bits (of 8) from FF cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procdff$23028 ($dff). Removed cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5754 ($mux). Removed cell top.$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5752 ($mux). Removed top 21 bits (of 32) from port A of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240 ($sub). Removed top 20 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5241 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5241 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244 ($sub). Removed cell top.$flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12280 ($mux). Removed top 1 bits (of 10) from port B of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$eq$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:81$4327 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340 ($add). Removed top 23 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340 ($add). Removed top 7 bits (of 8) from FF cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procdff$23028 ($dff). Removed cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5754 ($mux). Removed cell top.$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5752 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259 ($sub). Removed top 19 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262 ($sub). Removed top 27 bits (of 32) from port Y of cell top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262 ($sub). Removed cell top.$flatten\gps_uart_I.\uart_tx_I.$procmux$12444 ($mux). Removed top 1 bits (of 10) from mux cell top.$flatten\gps_uart_I.\uart_tx_I.$procmux$12447 ($mux). Removed top 1 bits (of 13) from mux cell top.$flatten\gps_uart_I.\uart_tx_I.$procmux$12455 ($mux). Removed top 24 bits (of 32) from mux cell top.$flatten\gps_uart_I.$ternary$/build/gateware/cores/no2misc//rtl/uart_wb.v:189$3307 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\gps_uart_I.$eq$/build/gateware/cores/no2misc//rtl/uart_wb.v:172$3286 ($eq). Removed top 2 bits (of 4) from port B of cell top.$auto$opt_dff.cc:218:make_patterns_logic$24223 ($ne). Removed top 1 bits (of 2) from port B of cell top.$flatten\i2c_I.\core_I.$eq$/build/gateware/cores/no2misc//rtl/i2c_master.v:109$5202 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5208 ($add). Removed top 27 bits (of 32) from port Y of cell top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5208 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5213 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5213 ($add). Removed top 1 bits (of 2) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23812 ($eq). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15348 ($mux). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15351 ($mux). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15363 ($mux). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15373 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\i2c_I.\core_I.$procmux$15381_CMP0 ($eq). Removed cell top.$flatten\i2c_I.\core_I.$procmux$15383 ($mux). Removed top 1 bits (of 11) from FF cell top.$auto$opt_dff.cc:702:run$24869 ($sdff). Removed cell top.$flatten\i2c_I.$procmux$15478 ($mux). Removed top 16 bits (of 32) from port B of cell top.$flatten\blinker_I.$and$/build/gateware/icE1usb/rtl/led_blinker.v:57$1593 ($and). Removed top 16 bits (of 32) from port Y of cell top.$flatten\blinker_I.$and$/build/gateware/icE1usb/rtl/led_blinker.v:57$1593 ($and). Removed top 16 bits (of 32) from port A of cell top.$flatten\blinker_I.$and$/build/gateware/icE1usb/rtl/led_blinker.v:57$1593 ($and). Removed top 31 bits (of 32) from port B of cell top.$flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591 ($add). Removed top 16 bits (of 32) from port Y of cell top.$flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591 ($add). Removed top 2 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$procmux$15550_CMP0 ($eq). Removed top 1 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$23707 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$procmux$15492_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$eq$/build/gateware/icE1usb/rtl/sr_btn_if.v:277$3255 ($eq). Removed top 3 bits (of 4) from port Y of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:247$3236 ($and). Removed top 3 bits (of 4) from port B of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3229 ($and). Removed top 3 bits (of 4) from port Y of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3229 ($and). Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$eq$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3228 ($eq). Removed top 28 bits (of 32) from port A of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3225 ($and). Removed top 28 bits (of 32) from port Y of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3225 ($and). Removed top 28 bits (of 32) from port B of cell top.$flatten\spi_mux_I.$and$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3225 ($and). Removed top 31 bits (of 32) from port B of cell top.$flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3224 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3224 ($add). Removed top 2 bits (of 3) from port B of cell top.$flatten\spi_mux_I.$eq$/build/gateware/icE1usb/rtl/sr_btn_if.v:198$3218 ($eq). Removed top 29 bits (of 32) from mux cell top.$flatten\spi_mux_I.$ternary$/build/gateware/icE1usb/rtl/sr_btn_if.v:144$3207 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1717 ($add). Removed top 28 bits (of 32) from port Y of cell top.$flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1717 ($add). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5340 ($or). Removed top 1 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5340 ($or). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_buf_I.$or$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5340 ($or). Removed top 1 bits (of 6) from port Y of cell top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$206 ($sub). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5337 ($shl). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5339 ($and). Removed top 1 bits (of 4) from port B of cell top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5339 ($and). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5338 ($not). Removed top 1 bits (of 4) from port A of cell top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5338 ($not). Removed top 1 bits (of 4) from port Y of cell top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5336 ($shl). Removed top 16 bits (of 32) from wire top.$flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591_Y. Removed top 19 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240_Y. Removed top 27 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244_Y. Removed top 23 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340_Y. Removed top 23 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338_Y. Removed top 1 bits (of 13) from wire top.$flatten\gps_uart_I.\uart_tx_I.$0\div_cnt[12:0]. Removed top 1 bits (of 10) from wire top.$flatten\gps_uart_I.\uart_tx_I.$0\shift[9:0]. Removed top 1 bits (of 10) from wire top.$flatten\gps_uart_I.\uart_tx_I.$procmux$12444_Y. Removed top 19 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259_Y. Removed top 27 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262_Y. Removed top 23 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340_Y. Removed top 23 bits (of 32) from wire top.$flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338_Y. Removed top 27 bits (of 32) from wire top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5208_Y. Removed top 28 bits (of 32) from wire top.$flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5213_Y. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_EN[31:0]$3511. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_DATA[31:0]$3513. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_DATA[31:0]$3516. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_EN[31:0]$3517. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:33$3504_DATA. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_DATA. Removed top 8 bits (of 32) from wire top.$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:35$3506_DATA. Removed top 16 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$2\mem_rdata_word[31:0]. Removed top 24 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$3\mem_rdata_word[31:0]. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4208_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4215_Y. Removed top 2 bits (of 6) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procmux$15956_Y. Removed top 2 bits (of 6) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procmux$15959_Y. Removed top 2 bits (of 6) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$procmux$15962_Y. Removed top 29 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$35_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$40_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$45_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$118_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$122_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$126_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$130_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12_Y. Removed top 3 bits (of 16) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bus_rd_rx_status. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$216_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:196$231_Y. Removed top 28 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:196$233_Y. Removed top 30 bits (of 32) from wire top.$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$and$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5339_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$not$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5338_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5336_Y. Removed top 1 bits (of 4) from wire top.$flatten\soc_I.\e1_buf_I.$shl$/build/gateware/cores/no2e1//rtl/e1_buf_if_wb.v:0$5337_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5241_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338_Y. Removed top 1 bits (of 13) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$0\div_cnt[12:0]. Removed top 1 bits (of 10) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12444_Y. Removed top 19 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259_Y. Removed top 27 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340_Y. Removed top 23 bits (of 32) from wire top.$flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338_Y. Removed top 28 bits (of 32) from wire top.$flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3224_Y. Removed top 29 bits (of 32) from wire top.$flatten\spi_mux_I.$ternary$/build/gateware/icE1usb/rtl/sr_btn_if.v:144$3207_Y. Removed top 28 bits (of 32) from wire top.$flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1717_Y. 75.14. Executing PEEPOPT pass (run peephole optimizers). 75.15. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 147 unused wires. <suppressed ~1 debug messages> 75.16. Executing SHARE pass (SAT-based resource sharing). 75.17. Executing TECHMAP pass (map to technology primitives). 75.17.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/cmp2lut.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 75.17.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~88 debug messages> 75.18. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~3 debug messages> 75.19. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 3 unused wires. <suppressed ~1 debug messages> 75.20. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591 ($add). creating $macc model for $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:66$1595 ($add). creating $macc model for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5241 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4393 ($add). creating $macc model for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340 ($add). creating $macc model for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4323 ($add). creating $macc model for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338 ($add). creating $macc model for $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262 ($sub). creating $macc model for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340 ($add). creating $macc model for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4323 ($add). creating $macc model for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338 ($add). creating $macc model for $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5208 ($add). creating $macc model for $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5213 ($add). creating $macc model for $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4288 ($add). creating $macc model for $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$5183 ($add). creating $macc model for $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4278 ($add). creating $macc model for $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4279 ($add). creating $macc model for $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4278 ($add). creating $macc model for $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4279 ($add). creating $macc model for $flatten\misc_I.\pdm_e1_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4274 ($add). creating $macc model for $flatten\misc_I.\pdm_e1_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4274 ($add). creating $macc model for $flatten\misc_I.\pps_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4309 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1210$4264 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$4072 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$4149 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$4150 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4194 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4219 ($add). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1210$4263 ($sub). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4208 ($sub). creating $macc model for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4215 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$35 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$40 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$45 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$118 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$122 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$126 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$130 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$59 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$154 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$163 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$158 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$167 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4563 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4564 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:117$214 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$216 ($add). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$206 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:196$231 ($sub). creating $macc model for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$462 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5034 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5038 ($add). creating $macc model for $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5048 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5241 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4393 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4323 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262 ($sub). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4323 ($add). creating $macc model for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3494 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3475 ($add). creating $macc model for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3479 ($add). creating $macc model for $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1340 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1420 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1481 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1490 ($add). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1437 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1487 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1506 ($add). creating $macc model for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1510 ($add). creating $macc model for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1549 ($sub). creating $macc model for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1572 ($sub). creating $macc model for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3224 ($add). creating $macc model for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3230 ($add). creating $macc model for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:246$3234 ($add). creating $macc model for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:247$3237 ($add). creating $macc model for $flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1717 ($add). merging $macc model for $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4278 into $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4279. merging $macc model for $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4278 into $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4279. creating $alu model for $macc $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:246$3234. creating $alu model for $macc $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3230. creating $alu model for $macc $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3224. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1572. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1549. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1510. creating $alu model for $macc $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1506. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1487. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1437. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1490. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1481. creating $alu model for $macc $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1420. creating $alu model for $macc $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1340. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3479. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3475. creating $alu model for $macc $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3494. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4323. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4323. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4393. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5241. creating $alu model for $macc $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5048. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5038. creating $alu model for $macc $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5034. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$462. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:196$231. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$206. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$216. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:117$214. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4564. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4563. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$167. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$158. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$163. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$154. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$59. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$130. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$126. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$122. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$118. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$45. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$40. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$35. creating $alu model for $macc $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4215. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4208. creating $alu model for $macc $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1210$4263. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4219. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4194. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$4150. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$4149. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$4072. creating $alu model for $macc $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1210$4264. creating $alu model for $macc $flatten\misc_I.\pps_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4309. creating $alu model for $macc $flatten\misc_I.\pdm_e1_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4274. creating $alu model for $macc $flatten\misc_I.\pdm_e1_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4274. creating $alu model for $macc $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4279. creating $alu model for $macc $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:247$3237. creating $alu model for $macc $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4279. creating $alu model for $macc $flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1717. creating $alu model for $macc $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$5183. creating $alu model for $macc $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4288. creating $alu model for $macc $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5213. creating $alu model for $macc $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5208. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4323. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262. creating $alu model for $macc $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4323. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4393. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5241. creating $alu model for $macc $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240. creating $alu model for $macc $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:66$1595. creating $alu model for $macc $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591. creating $alu model for $flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4200 ($ge): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1212$4267 ($lt): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1213$4268 ($lt): new $alu creating $alu model for $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1211$4266 ($eq): merged with $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1213$4268. creating $alu cell for $flatten\soc_I.\cpu_I.$ge$/build/gateware/common/rtl/picorv32.v:1814$4200: $auto$alumacc.cc:485:replace_alu$24972 creating $alu cell for $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:57$1591: $auto$alumacc.cc:485:replace_alu$24981 creating $alu cell for $flatten\blinker_I.$add$/build/gateware/icE1usb/rtl/led_blinker.v:66$1595: $auto$alumacc.cc:485:replace_alu$24984 creating $alu cell for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240: $auto$alumacc.cc:485:replace_alu$24987 creating $alu cell for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5241: $auto$alumacc.cc:485:replace_alu$24990 creating $alu cell for $flatten\gps_uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244: $auto$alumacc.cc:485:replace_alu$24993 creating $alu cell for $flatten\gps_uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4393: $auto$alumacc.cc:485:replace_alu$24996 creating $alu cell for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340: $auto$alumacc.cc:485:replace_alu$24999 creating $alu cell for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4323: $auto$alumacc.cc:485:replace_alu$25002 creating $alu cell for $flatten\gps_uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338: $auto$alumacc.cc:485:replace_alu$25005 creating $alu cell for $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259: $auto$alumacc.cc:485:replace_alu$25008 creating $alu cell for $flatten\gps_uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262: $auto$alumacc.cc:485:replace_alu$25011 creating $alu cell for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340: $auto$alumacc.cc:485:replace_alu$25014 creating $alu cell for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4323: $auto$alumacc.cc:485:replace_alu$25017 creating $alu cell for $flatten\gps_uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338: $auto$alumacc.cc:485:replace_alu$25020 creating $alu cell for $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:133$5208: $auto$alumacc.cc:485:replace_alu$25023 creating $alu cell for $flatten\i2c_I.\core_I.$add$/build/gateware/cores/no2misc//rtl/i2c_master.v:143$5213: $auto$alumacc.cc:485:replace_alu$25026 creating $alu cell for $flatten\misc_I.\dfu_I.$add$/build/gateware/common/rtl/dfu_helper.v:113$4288: $auto$alumacc.cc:485:replace_alu$25029 creating $alu cell for $flatten\misc_I.\dfu_I.\btn_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$5183: $auto$alumacc.cc:485:replace_alu$25032 creating $alu cell for $flatten\sys_mgr_I.$add$/build/gateware/icE1usb/rtl/sysmgr.v:80$1717: $auto$alumacc.cc:485:replace_alu$25035 creating $alu cell for $flatten\misc_I.\pdm_clk_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4279: $auto$alumacc.cc:485:replace_alu$25038 creating $alu cell for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:247$3237: $auto$alumacc.cc:485:replace_alu$25041 creating $alu cell for $flatten\misc_I.\pdm_clk_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4279: $auto$alumacc.cc:485:replace_alu$25044 creating $alu cell for $flatten\misc_I.\pdm_e1_I[0].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4274: $auto$alumacc.cc:485:replace_alu$25047 creating $alu cell for $flatten\misc_I.\pdm_e1_I[1].$add$/build/gateware/cores/no2misc//rtl/pdm.v:47$4274: $auto$alumacc.cc:485:replace_alu$25050 creating $alu cell for $flatten\misc_I.\pps_flt_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4309: $auto$alumacc.cc:485:replace_alu$25053 creating $alu cell for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1213$4268, $flatten\soc_I.\cpu_I.$eq$/build/gateware/common/rtl/picorv32.v:1211$4266: $auto$alumacc.cc:485:replace_alu$25056 creating $alu cell for $flatten\soc_I.\cpu_I.$lt$/build/gateware/common/rtl/picorv32.v:1212$4267: $auto$alumacc.cc:485:replace_alu$25067 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1210$4264: $auto$alumacc.cc:485:replace_alu$25080 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1296$4072: $auto$alumacc.cc:485:replace_alu$25083 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1539$4149: $auto$alumacc.cc:485:replace_alu$25086 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1548$4150: $auto$alumacc.cc:485:replace_alu$25089 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1785$4194: $auto$alumacc.cc:485:replace_alu$25092 creating $alu cell for $flatten\soc_I.\cpu_I.$add$/build/gateware/common/rtl/picorv32.v:1848$4219: $auto$alumacc.cc:485:replace_alu$25095 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1210$4263: $auto$alumacc.cc:485:replace_alu$25098 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1821$4208: $auto$alumacc.cc:485:replace_alu$25101 creating $alu cell for $flatten\soc_I.\cpu_I.$sub$/build/gateware/common/rtl/picorv32.v:1829$4215: $auto$alumacc.cc:485:replace_alu$25104 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\clock_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_clock_recovery.v:49$18: $auto$alumacc.cc:485:replace_alu$25107 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:213$35: $auto$alumacc.cc:485:replace_alu$25110 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:225$40: $auto$alumacc.cc:485:replace_alu$25113 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:239$45: $auto$alumacc.cc:485:replace_alu$25116 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:351$118: $auto$alumacc.cc:485:replace_alu$25119 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:352$122: $auto$alumacc.cc:485:replace_alu$25122 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:353$126: $auto$alumacc.cc:485:replace_alu$25125 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:354$130: $auto$alumacc.cc:485:replace_alu$25128 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_deframer.v:270$59: $auto$alumacc.cc:485:replace_alu$25131 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:54$154: $auto$alumacc.cc:485:replace_alu$25134 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$add$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:62$163: $auto$alumacc.cc:485:replace_alu$25137 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:56$158: $auto$alumacc.cc:485:replace_alu$25140 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\filter_I.$sub$/build/gateware/cores/no2e1//rtl/e1_rx_filter.v:64$167: $auto$alumacc.cc:485:replace_alu$25143 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4563: $auto$alumacc.cc:485:replace_alu$25146 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4564: $auto$alumacc.cc:485:replace_alu$25149 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:117$214: $auto$alumacc.cc:485:replace_alu$25152 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$add$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:126$216: $auto$alumacc.cc:485:replace_alu$25155 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:101$206: $auto$alumacc.cc:485:replace_alu$25158 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:196$231: $auto$alumacc.cc:485:replace_alu$25161 creating $alu cell for $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\hdb3_I.$add$/build/gateware/cores/no2e1//rtl/hdb3_enc.v:120$462: $auto$alumacc.cc:485:replace_alu$25164 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:155$5034: $auto$alumacc.cc:485:replace_alu$25167 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$add$/build/gateware/common/rtl/wb_dma.v:159$5038: $auto$alumacc.cc:485:replace_alu$25170 creating $alu cell for $flatten\soc_I.\iobuf_I.\dma_I.$sub$/build/gateware/common/rtl/wb_dma.v:176$5048: $auto$alumacc.cc:485:replace_alu$25173 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:79$5240: $auto$alumacc.cc:485:replace_alu$25176 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:83$5241: $auto$alumacc.cc:485:replace_alu$25179 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_rx.v:92$5244: $auto$alumacc.cc:485:replace_alu$25182 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$add$/build/gateware/cores/no2misc//rtl/glitch_filter.v:74$4393: $auto$alumacc.cc:485:replace_alu$25185 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340: $auto$alumacc.cc:485:replace_alu$25188 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4323: $auto$alumacc.cc:485:replace_alu$25191 creating $alu cell for $flatten\soc_I.\uart_I.\uart_rx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338: $auto$alumacc.cc:485:replace_alu$25194 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:46$5259: $auto$alumacc.cc:485:replace_alu$25197 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_I.$sub$/build/gateware/cores/no2misc//rtl/uart_tx.v:55$5262: $auto$alumacc.cc:485:replace_alu$25200 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:112$4340: $auto$alumacc.cc:485:replace_alu$25203 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:71$4323: $auto$alumacc.cc:485:replace_alu$25206 creating $alu cell for $flatten\soc_I.\uart_I.\uart_tx_fifo_I.$add$/build/gateware/cores/no2misc//rtl/fifo_sync_ram.v:99$4338: $auto$alumacc.cc:485:replace_alu$25209 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:540$3494: $auto$alumacc.cc:485:replace_alu$25212 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:623$3475: $auto$alumacc.cc:485:replace_alu$25215 creating $alu cell for $flatten\soc_I.\usb_I.$add$/build/gateware/cores/no2usb//rtl/usb.v:632$3479: $auto$alumacc.cc:485:replace_alu$25218 creating $alu cell for $flatten\soc_I.\usb_I.\rx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_rx_pkt.v:224$1340: $auto$alumacc.cc:485:replace_alu$25221 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:179$1420: $auto$alumacc.cc:485:replace_alu$25224 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:415$1481: $auto$alumacc.cc:485:replace_alu$25227 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$add$/build/gateware/cores/no2usb//rtl/usb_trans.v:429$1490: $auto$alumacc.cc:485:replace_alu$25230 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:258$1437: $auto$alumacc.cc:485:replace_alu$25233 creating $alu cell for $flatten\soc_I.\usb_I.\trans_I.$sub$/build/gateware/cores/no2usb//rtl/usb_trans.v:425$1487: $auto$alumacc.cc:485:replace_alu$25236 creating $alu cell for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:80$1506: $auto$alumacc.cc:485:replace_alu$25239 creating $alu cell for $flatten\soc_I.\usb_I.\tx_ll_I.$add$/build/gateware/cores/no2usb//rtl/usb_tx_ll.v:94$1510: $auto$alumacc.cc:485:replace_alu$25242 creating $alu cell for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154$1549: $auto$alumacc.cc:485:replace_alu$25245 creating $alu cell for $flatten\soc_I.\usb_I.\tx_pkt_I.$sub$/build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:193$1572: $auto$alumacc.cc:485:replace_alu$25248 creating $alu cell for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:216$3224: $auto$alumacc.cc:485:replace_alu$25251 creating $alu cell for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:229$3230: $auto$alumacc.cc:485:replace_alu$25254 creating $alu cell for $flatten\spi_mux_I.$add$/build/gateware/icE1usb/rtl/sr_btn_if.v:246$3234: $auto$alumacc.cc:485:replace_alu$25257 created 88 $alu and 0 $macc cells. 75.21. Executing OPT pass (performing simple optimizations). 75.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~24 debug messages> Removed a total of 8 cells. 75.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~204 debug messages> 75.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13709: { \soc_I.cpu_I.cpu_state [1] \soc_I.cpu_I.cpu_state [2] $auto$opt_reduce.cc:134:opt_mux$25261 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13920: { \soc_I.cpu_I.cpu_state [2] \soc_I.cpu_I.cpu_state [4] $auto$opt_reduce.cc:134:opt_mux$25263 } New ctrl vector for $pmux cell $flatten\soc_I.\cpu_I.$procmux$14906: { $flatten\soc_I.\cpu_I.$logic_and$/build/gateware/common/rtl/picorv32.v:364$3667_Y $flatten\soc_I.\cpu_I.$procmux$14916_CMP $auto$opt_reduce.cc:134:opt_mux$25265 } Optimizing cells in module \top. Performed a total of 3 changes. 75.21.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 75.21.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 16 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 17 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 18 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 19 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 20 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 21 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 22 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 23 on $flatten\soc_I.\bram_I.$procdff$23424 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 8 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 9 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 10 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 11 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 12 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 13 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 14 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 15 on $flatten\soc_I.\bram_I.$procdff$23421 ($dff) from module top. Setting constant 1-bit at position 0 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 1 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 2 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 3 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 4 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 5 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 6 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 1-bit at position 7 on $flatten\soc_I.\bram_I.$procdff$23418 ($dff) from module top. Setting constant 0-bit at position 0 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 1 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 2 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 3 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 4 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 5 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 6 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 7 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 8 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 9 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 10 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 11 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 12 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 13 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 14 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 15 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 16 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 17 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 18 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 19 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 0-bit at position 20 on $flatten\i2c_I.$procdff$23472 ($dff) from module top. Setting constant 1-bit at position 9 on $auto$opt_dff.cc:764:run$24879 ($adffe) from module top. Adding SRST signal on $auto$opt_dff.cc:764:run$24582 ($dffe) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14959_Y, Q = \soc_I.cpu_I.mem_valid, rval = 1'0). Adding SRST signal on $auto$opt_dff.cc:764:run$24565 ($dffe) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14906_Y, Q = \soc_I.cpu_I.mem_state, rval = 2'00). Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$24902 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 16 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 17 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 18 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 19 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 20 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 21 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 22 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. Setting constant 0-bit at position 23 on $auto$opt_dff.cc:702:run$24324 ($sdff) from module top. 75.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 4 unused cells and 17 unused wires. <suppressed ~5 debug messages> 75.21.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.21.9. Rerunning OPT passes. (Maybe there is more to do..) 75.21.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~204 debug messages> 75.21.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.21.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.21.13. Executing OPT_DFF pass (perform DFF optimizations). 75.21.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.21.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.21.16. Finished OPT passes. (There is nothing left to do.) 75.22. Executing MEMORY pass. 75.22.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 75.22.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). Checking cell `$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5463' in module `\top': merged $dff to cell. Checking cell `$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5463' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3531' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3532' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3533' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3534' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5463' in module `\top': merged $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5463' in module `\top': merged $dff to cell. Checking cell `$flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5462' in module `\top': merged data $dff to cell. Checking cell `$flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5462' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\bram_I.$memrd$\mem$/build/gateware/common/rtl/soc_bram.v:32$3521' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5462' in module `\top': merged data $dff to cell. Checking cell `$flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5462' in module `\top': merged data $dff to cell. 75.22.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 25 unused cells and 30 unused wires. <suppressed ~26 debug messages> 75.22.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating write ports of memory top.soc_I.bram_I.mem by address: New clock domain: posedge \blinker_I.clk Port 0 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3531) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000000000000000000011111111 Port 1 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3532) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000000000001111111100000000 Merging port 0 into this one. Active bits: 00000000000000001111111111111111 Port 2 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3533) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 00000000111111110000000000000000 Merging port 1 into this one. Active bits: 00000000111111111111111111111111 Port 3 ($flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3534) has addr \soc_I.cpu_I.mem_addr [9:2]. Active bits: 11111111000000000000000000000000 Merging port 2 into this one. Active bits: 11111111111111111111111111111111 75.22.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.22.6. Executing MEMORY_COLLECT pass (generating $mem cells). Collecting $memrd, $memwr and $meminit for memory `\gps_uart_I.uart_rx_fifo_I.ram_I.ram' in module `\top': $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5463 ($memwr) $flatten\gps_uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5462 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\gps_uart_I.uart_tx_fifo_I.ram_I.ram' in module `\top': $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5463 ($memwr) $flatten\gps_uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5462 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.bram_I.mem' in module `\top': $flatten\soc_I.\bram_I.$meminit$\mem$/build/gateware/common/rtl/soc_bram.v:0$3530 ($meminit) $flatten\soc_I.\bram_I.$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:0$3534 ($memwr) $flatten\soc_I.\bram_I.$memrd$\mem$/build/gateware/common/rtl/soc_bram.v:32$3521 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.uart_I.uart_rx_fifo_I.ram_I.ram' in module `\top': $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5463 ($memwr) $flatten\soc_I.\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5462 ($memrd) Collecting $memrd, $memwr and $meminit for memory `\soc_I.uart_I.uart_tx_fifo_I.ram_I.ram' in module `\top': $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memwr$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:0$5463 ($memwr) $flatten\soc_I.\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/build/gateware/cores/no2misc//rtl/ram_sdp.v:43$5462 ($memrd) 75.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). Processing top.gps_uart_I.uart_rx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: gps_uart_I.uart_rx_fifo_I.ram_I.ram.0.0.0 Processing top.gps_uart_I.uart_tx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: gps_uart_I.uart_tx_fifo_I.ram_I.ram.0.0.0 Processing top.soc_I.bram_I.mem: Properties: ports=2 bits=8192 rports=1 wports=1 dbits=32 abits=8 words=256 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3584 efficiency=12 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=256 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=768 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1792 dwaste=0 bwaste=3584 waste=3584 efficiency=12 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=12, cells=16, acells=1 Efficiency for rule 4.2: efficiency=25, cells=8, acells=1 Efficiency for rule 4.1: efficiency=50, cells=4, acells=1 Efficiency for rule 1.1: efficiency=100, cells=2, acells=1 Selected rule 1.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M0 cell at grid position <0 0 0>: soc_I.bram_I.mem.0.0.0 Creating $__ICE40_RAM4K_M0 cell at grid position <1 0 0>: soc_I.bram_I.mem.1.0.0 Processing top.soc_I.uart_I.uart_rx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: soc_I.uart_I.uart_rx_fifo_I.ram_I.ram.0.0.0 Processing top.soc_I.uart_I.uart_tx_fifo_I.ram_I.ram: Properties: ports=2 bits=4096 rports=1 wports=1 dbits=8 abits=9 words=512 Checking rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #1 for bram type $__ICE40_RAM4K_M0 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M0 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #2 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1): Bram geometry: abits=8 dbits=16 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M0: awaste=0 dwaste=8 bwaste=2048 waste=2048 efficiency=50 Rule #3 for bram type $__ICE40_RAM4K_M0 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 1) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=0 efficiency=100 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 2) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 2): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=2048 efficiency=50 Storing for later selection. Checking rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #4 for bram type $__ICE40_RAM4K_M123 (variant 3) accepted. Mapping to bram type $__ICE40_RAM4K_M123 (variant 3): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Updated properties: dups=1 waste=3072 efficiency=25 Storing for later selection. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #5 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1): Bram geometry: abits=9 dbits=8 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 1) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2): Bram geometry: abits=10 dbits=4 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=512 dwaste=0 bwaste=2048 waste=2048 efficiency=50 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 2) rejected: requirement 'max wports 0' not met. Checking rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3): Bram geometry: abits=11 dbits=2 wports=0 rports=0 Estimated number of duplicates for more read ports: dups=1 Metrics for $__ICE40_RAM4K_M123: awaste=1536 dwaste=0 bwaste=3072 waste=3072 efficiency=25 Rule #6 for bram type $__ICE40_RAM4K_M123 (variant 3) rejected: requirement 'max wports 0' not met. Selecting best of 4 rules: Efficiency for rule 4.3: efficiency=25, cells=4, acells=1 Efficiency for rule 4.2: efficiency=50, cells=2, acells=1 Efficiency for rule 4.1: efficiency=100, cells=1, acells=1 Efficiency for rule 1.1: efficiency=50, cells=2, acells=2 Selected rule 4.1 with efficiency 100. Mapping to bram type $__ICE40_RAM4K_M123 (variant 1): Write port #0 is in clock domain \blinker_I.clk. Mapped to bram port B1. Read port #0 is in clock domain \blinker_I.clk. Mapped to bram port A1.1. Creating $__ICE40_RAM4K_M123 cell at grid position <0 0 0>: soc_I.uart_I.uart_tx_fifo_I.ram_I.ram.0.0.0 75.25. Executing TECHMAP pass (map to technology primitives). 75.25.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'. Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'. Successfully finished Verilog frontend. 75.25.2. Continuing TECHMAP pass. Using template $paramod\$__ICE40_RAM4K_M123\CFG_ABITS=9\CFG_DBITS=8\CLKPOL2=1\CLKPOL3=1 for cells of type $__ICE40_RAM4K_M123. Using template $paramod$b9e8582c288289ac723b215129f56c6fb55d152a\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. Using template $paramod$4db28c01ad2f8fb3d28d8b45acd344e29c76a5e2\$__ICE40_RAM4K_M0 for cells of type $__ICE40_RAM4K_M0. Using template $paramod$604ec1e346c2dd44ad2f04f633da753d2abbf02c\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. Using template $paramod$66c3fa288a62dc560ce3ddd26d81551ab195105f\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. Using template $paramod$7577afd8fd444532bbc3532c110d9d682708035f\$__ICE40_RAM4K for cells of type $__ICE40_RAM4K. No more expansions possible. <suppressed ~211 debug messages> 75.26. Executing ICE40_BRAMINIT pass. Processing soc_I.usb_I.trans_I.mc_rom_I : usb_trans_mc.hex 75.27. Executing OPT pass (performing simple optimizations). 75.27.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~301 debug messages> 75.27.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.27.3. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\soc_I.\cpu_I.$procdff$23264 ($dff) from module top (D = $flatten\soc_I.\cpu_I.$0\reg_sh[4:0] [1:0], Q = \soc_I.cpu_I.reg_sh [1:0]). 75.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 39 unused cells and 264 unused wires. <suppressed ~51 debug messages> 75.27.5. Rerunning OPT passes. (Removed registers in this run.) 75.27.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.27.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.27.8. Executing OPT_DFF pass (perform DFF optimizations). 75.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.27.10. Finished fast OPT passes. 75.28. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 75.29. Executing OPT pass (performing simple optimizations). 75.29.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~185 debug messages> 75.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $techmap$techmap25296\soc_I.bram_I.mem.0.0.0.$reduce_or$/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v:222$25295: { $auto$wreduce.cc:454:run$24918 [7] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:34$3505_EN[31:0]$3514 [15] } New input vector for $reduce_or cell $techmap$techmap25293\soc_I.bram_I.mem.1.0.0.$reduce_or$/opt/fpga-toolchain/bin/../share/yosys/ice40/brams_map.v:222$25292: { $auto$wreduce.cc:454:run$24921 [23] $flatten\soc_I.\bram_I.$0$memwr$\mem$/build/gateware/common/rtl/soc_bram.v:36$3507_EN[31:0]$3520 [31] } Consolidated identical input bits for $mux cell $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592: Old ports: A=16'1111111111111111, B=16'0000000000000000, Y=$flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y New ports: A=1'1, B=1'0, Y=$flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] New connections: $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [15:1] = { $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] $flatten\blinker_I.$ternary$/build/gateware/icE1usb/rtl/led_blinker.v:57$1592_Y [0] } Consolidated identical input bits for $mux cell $flatten\gps_uart_I.\uart_rx_I.\gf_I.$procmux$12292: Old ports: A=2'00, B=2'11, Y=$flatten\gps_uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] New ports: A=1'0, B=1'1, Y=$flatten\gps_uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0] New connections: $flatten\gps_uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [1] = $flatten\gps_uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0] Consolidated identical input bits for $mux cell $flatten\i2c_I.\core_I.$procmux$15378: Old ports: A=4'1000, B=4'0000, Y=$flatten\i2c_I.\core_I.$procmux$15378_Y New ports: A=1'1, B=1'0, Y=$flatten\i2c_I.\core_I.$procmux$15378_Y [3] New connections: $flatten\i2c_I.\core_I.$procmux$15378_Y [2:0] = 3'000 Consolidated identical input bits for $mux cell $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5637: Old ports: A=4'0000, B=4'1111, Y=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] New ports: A=1'0, B=1'1, Y=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] New connections: $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [3:1] = { $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] } Consolidated identical input bits for $mux cell $flatten\misc_I.\pps_flt_I.$procmux$12482: Old ports: A=2'00, B=2'11, Y=$flatten\misc_I.\pps_flt_I.$2\cnt_move[1:0] New ports: A=1'0, B=1'1, Y=$flatten\misc_I.\pps_flt_I.$2\cnt_move[1:0] [0] New connections: $flatten\misc_I.\pps_flt_I.$2\cnt_move[1:0] [1] = $flatten\misc_I.\pps_flt_I.$2\cnt_move[1:0] [0] Consolidated identical input bits for $pmux cell $flatten\soc_I.\cpu_I.$procmux$13182: Old ports: A=\soc_I.cpu_I.mem_rdata_word, B={ \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15:0] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7:0] }, Y=$flatten\soc_I.\cpu_I.$procmux$13182_Y New ports: A=\soc_I.cpu_I.mem_rdata_word [31:8], B={ \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15] \soc_I.cpu_I.mem_rdata_word [15:7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] \soc_I.cpu_I.mem_rdata_word [7] }, Y=$flatten\soc_I.\cpu_I.$procmux$13182_Y [31:8] New connections: $flatten\soc_I.\cpu_I.$procmux$13182_Y [7:0] = \soc_I.cpu_I.mem_rdata_word [7:0] Consolidated identical input bits for $pmux cell $flatten\soc_I.\cpu_I.$procmux$15225: Old ports: A=\soc_I.cpu_I.reg_op2, B={ \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] }, Y=\soc_I.cpu_I.mem_la_wdata New ports: A=\soc_I.cpu_I.reg_op2 [31:8], B={ \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [15:0] \soc_I.cpu_I.reg_op2 [7:0] \soc_I.cpu_I.reg_op2 [7:0] }, Y=\soc_I.cpu_I.mem_la_wdata [31:8] New connections: \soc_I.cpu_I.mem_la_wdata [7:0] = \soc_I.cpu_I.reg_op2 [7:0] Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1192$4040: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B={ \soc_I.cpu_I.reg_out [31:1] 1'0 }, Y=\soc_I.cpu_I.next_pc New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=\soc_I.cpu_I.reg_out [31:1], Y=\soc_I.cpu_I.next_pc [31:1] New connections: \soc_I.cpu_I.next_pc [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4109: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B={ $auto$opt_expr.cc:205:group_cell_inputs$25364 1'0 }, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4109_Y New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=$auto$opt_expr.cc:205:group_cell_inputs$25364, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4109_Y [31:1] New connections: $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4109_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$4162: Old ports: A={ \soc_I.cpu_I.reg_pc [31:2] 2'00 }, B=0, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$4162_Y New ports: A=\soc_I.cpu_I.reg_pc [31:2], B=30'000000000000000000000000000000, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$4162_Y [31:2] New connections: $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1621$4162_Y [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:366$3683: Old ports: A={ \soc_I.cpu_I.reg_op1 [31:2] 2'00 }, B={ \soc_I.cpu_I.next_pc [31:2] 2'00 }, Y=\soc_I.cpu_I.mem_la_addr New ports: A=\soc_I.cpu_I.reg_op1 [31:2], B=\soc_I.cpu_I.next_pc [31:2], Y=\soc_I.cpu_I.mem_la_addr [31:2] New connections: \soc_I.cpu_I.mem_la_addr [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3698: Old ports: A=4'0011, B=4'1100, Y=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3698_Y New ports: A=2'01, B=2'10, Y={ $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3698_Y [2] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3698_Y [0] } New connections: { $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3698_Y [3] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3698_Y [1] } = { $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3698_Y [2] $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:395$3698_Y [0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:601$3758: Old ports: A=2'11, B=2'00, Y=$flatten\soc_I.\cpu_I.$procmux$14912_Y New ports: A=1'1, B=1'0, Y=$flatten\soc_I.\cpu_I.$procmux$14912_Y [0] New connections: $flatten\soc_I.\cpu_I.$procmux$14912_Y [1] = $flatten\soc_I.\cpu_I.$procmux$14912_Y [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4627: Old ports: A={ 3'000 $auto$wreduce.cc:454:run$24940 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_in_I.rd_empty 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$24940 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.data[1] [8:7] 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4627_Y New ports: A={ 3'000 $auto$wreduce.cc:454:run$24940 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_in_I.rd_empty 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.aligned $auto$wreduce.cc:454:run$24940 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.stage[1].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.data[1] [8:7] 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.data[1] [6:0] }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4627_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4627_Y [6:0] } New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4627_Y [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.\rx_I.\deframer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [1] = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.rx_I.deframer_I.crc_I.state_upd_mux [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4587: Old ports: A={ 3'000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bus_rd_tx_status [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.rd_empty 7'0000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bus_rd_tx_status [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.stage[1].l_valid 8'00000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.data[1] }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4587_Y New ports: A={ 1'0 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bus_rd_tx_status [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_in_I.rd_empty 6'000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bus_rd_tx_status [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.stage[1].l_valid 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.bd_tx_out_I.data[1] }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4587_Y [15] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4587_Y [12:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4587_Y [6:0] } New connections: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4587_Y [14:13] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4587_Y [7] } = 3'000 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4561: Old ports: A=5'00000, B=5'11001, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4561_Y New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4561_Y [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4561_Y [4:1] = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4561_Y [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4561_Y [0] 2'00 } Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4562: Old ports: A=5'00000, B=5'11001, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4562_Y New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4562_Y [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4562_Y [4:1] = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4562_Y [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4562_Y [0] 2'00 } Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.\framer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [0] New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [1] = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_buf_I.$procmux$12437: Old ports: A=2'00, B=2'10, Y=\soc_I.e1_buf_I.t_nxt_chan New ports: A=1'0, B=1'1, Y=\soc_I.e1_buf_I.t_nxt_chan [1] New connections: \soc_I.e1_buf_I.t_nxt_chan [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:115$5016: Old ports: A=2'10, B=2'00, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5702_Y New ports: A=1'1, B=1'0, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5702_Y [1] New connections: $flatten\soc_I.\iobuf_I.\dma_I.$procmux$5702_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:205$5066: Old ports: A=16'0000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir 1'0 \soc_I.iobuf_I.dma_I.len }, Y=\soc_I.iobuf_I.wb_rdata_dma [15:0] New ports: A=15'000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir \soc_I.iobuf_I.dma_I.len }, Y={ \soc_I.iobuf_I.wb_rdata_dma [15:14] \soc_I.iobuf_I.wb_rdata_dma [12:0] } New connections: \soc_I.iobuf_I.wb_rdata_dma [13] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5134: Old ports: A=0, B={ \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte }, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5134_Y New ports: A=8'00000000, B=\soc_I.e1_buf_I.wb_wdata_byte, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5134_Y [7:0] New connections: $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5134_Y [31:8] = { $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5134_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5134_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5134_Y [7:0] } Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12292: Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0] New connections: $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [1] = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0] Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12447: Old ports: A={ 1'1 \soc_I.uart_I.uart_tx_I.shift [9:1] }, B={ 1'1 \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] New ports: A=\soc_I.uart_I.uart_tx_I.shift [9:1], B={ \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [8:0] New connections: $flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [9] = 1'1 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4953: Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] New connections: \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4966: Old ports: A=3'000, B=3'101, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:0] New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0] New connections: \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:1] = { \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11893: Old ports: A=3'000, B=3'110, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [2:0] New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [1] New connections: { $flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [2] $flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [0] } = { $flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [1] 1'0 } Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11896: Old ports: A={ 1'0 $flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [2:0] }, B=4'0100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11896_Y New ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11896_Y [2:0] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11896_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:340$1451: Old ports: A={ 8'00000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup 2'00 \soc_I.usb_I.trans_I.xfer_length }, Y=\soc_I.usb_I.ep_status_I.p_din_0 New ports: A={ 6'000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup \soc_I.usb_I.trans_I.xfer_length }, Y={ \soc_I.usb_I.ep_status_I.p_din_0 [15:12] \soc_I.usb_I.ep_status_I.p_din_0 [9:0] } New connections: \soc_I.usb_I.ep_status_I.p_din_0 [11:10] = 2'00 Consolidated identical input bits for $pmux cell $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11844: Old ports: A=3'000, B=6'110111, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11844_Y New ports: A=2'00, B=4'1011, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11844_Y [1:0] New connections: $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11844_Y [2] = $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11844_Y [1] Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4953: Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] New connections: \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\spi_mux_I.$ternary$/build/gateware/icE1usb/rtl/sr_btn_if.v:144$3207: Old ports: A=3'010, B=3'100, Y=$auto$wreduce.cc:454:run$24961 [2:0] New ports: A=2'01, B=2'10, Y=$auto$wreduce.cc:454:run$24961 [2:1] New connections: $auto$wreduce.cc:454:run$24961 [0] = 1'0 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5643: Old ports: A=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0], B=4'0001, Y=\misc_I.dfu_I.btn_flt_I.cnt_move New ports: A={ $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] }, B=2'01, Y=\misc_I.dfu_I.btn_flt_I.cnt_move [1:0] New connections: \misc_I.dfu_I.btn_flt_I.cnt_move [3:2] = { \misc_I.dfu_I.btn_flt_I.cnt_move [1] \misc_I.dfu_I.btn_flt_I.cnt_move [1] } Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$procmux$12916: Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4109_Y, Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$25087 [1:0] } New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4109_Y [31:1], Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$25087 [1] } New connections: $auto$alumacc.cc:501:replace_alu$25087 [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4628: Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4627_Y, Y=\soc_I.e1_I.bus_rdata_rx[0] New ports: A=15'000000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4627_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4627_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_rx[0] [15:8] \soc_I.e1_I.bus_rdata_rx[0] [6:0] } New connections: \soc_I.e1_I.bus_rdata_rx[0] [7] = 1'0 Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4588: Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4587_Y, Y=\soc_I.e1_I.bus_rdata_tx[0] New ports: A=13'0000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4587_Y [15] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4587_Y [12:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4587_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_tx[0] [15] \soc_I.e1_I.bus_rdata_tx[0] [12:8] \soc_I.e1_I.bus_rdata_tx[0] [6:0] } New connections: { \soc_I.e1_I.bus_rdata_tx[0] [14:13] \soc_I.e1_I.bus_rdata_tx[0] [7] } = 3'000 Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11896: Old ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11896_Y [2:0] New ports: A={ $flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [1] $flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [1] }, B=2'10, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11896_Y [2:1] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11896_Y [0] = 1'0 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11899: Old ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11896_Y, B=4'1000, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11899_Y New ports: A={ 1'0 $flatten\soc_I.\usb_I.\trans_I.$procmux$11896_Y [2:1] }, B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11899_Y [3:1] New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11899_Y [0] = 1'0 Optimizing cells in module \top. Performed a total of 41 changes. 75.29.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.29.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23173 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:10], Q = \soc_I.usb_I.ep_status_I.din_1 [11:10], rval = 2'00). Adding SRST signal on $auto$opt_dff.cc:702:run$24404 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4563_Y [2:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.pg_hi [2:1], rval = 2'00). Adding SRST signal on $auto$opt_dff.cc:702:run$24403 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4564_Y [2:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.pg_lo [2:1], rval = 2'00). 75.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.29.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~37 debug messages> 75.29.9. Rerunning OPT passes. (Maybe there is more to do..) 75.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12403. dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12418. Removed 2 multiplexer ports. <suppressed ~186 debug messages> 75.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.29.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 75.29.13. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$opt_dff.cc:764:run$24851 ($dffe) from module top (D = $auto$wreduce.cc:454:run$24917 [2:0], Q = \i2c_I.core_I.bit_cnt [2:0], rval = 3'000). Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24587 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$24587 ($dffe) from module top. Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24358 ($dffe) from module top. Setting constant 1-bit at position 9 on $auto$opt_dff.cc:764:run$24306 ($adffe) from module top. 75.29.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 20 unused wires. <suppressed ~2 debug messages> 75.29.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.16. Rerunning OPT passes. (Maybe there is more to do..) 75.29.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~186 debug messages> 75.29.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.29.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.29.20. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24369 ($sdff) from module top. Adding SRST signal on $auto$opt_dff.cc:702:run$24369 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.data[1] [8:7], Q = \soc_I.e1_I.wb_rdata [14:13], rval = 2'00). Removing never-active SRST on $auto$opt_dff.cc:702:run$24364 ($sdffce) from module top. Removing never-active SRST on $auto$opt_dff.cc:702:run$24362 ($sdffce) from module top. Removing never-active SRST on $auto$opt_dff.cc:702:run$24360 ($sdffce) from module top. 75.29.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.29.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 75.29.23. Rerunning OPT passes. (Maybe there is more to do..) 75.29.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~186 debug messages> 75.29.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.29.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 75.29.27. Executing OPT_DFF pass (perform DFF optimizations). 75.29.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 3 unused wires. <suppressed ~1 debug messages> 75.29.29. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.30. Rerunning OPT passes. (Maybe there is more to do..) 75.29.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~186 debug messages> 75.29.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 75.29.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.29.34. Executing OPT_DFF pass (perform DFF optimizations). 75.29.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.29.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.29.37. Finished OPT passes. (There is nothing left to do.) 75.30. Executing ICE40_WRAPCARRY pass (wrap carries). 75.31. Executing TECHMAP pass (map to technology primitives). 75.31.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/techmap.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 75.31.2. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. 75.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $adffe. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $adff. Using extmapper simplemap for cells of type $mux. Using template $paramod$constmap:37b3cc4e06391b7a7ef418215dc52e2abb59f048$paramod$71443bc33ec938a4dea8c4b4bbb3a548919fd2a5\_90_shift_shiftx for cells of type $shiftx. Using template $paramod$constmap:f131a727070ba63172385ab8bc15babdfc05a11a$paramod$4d8c31a57f918e2cd1d0bc24d8284efd6d83f4a8\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=1\Y_WIDTH=7 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $logic_or. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=1\Y_WIDTH=5 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu. Using template $paramod$constmap:98a2574d6790db88f29c592e698ccfc2583099ee$paramod$da4b7a069bab2d2cb126ab511d2c5f5d67aa4129\_90_shift_shiftx for cells of type $shiftx. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=14\Y_WIDTH=14 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu. Using template $paramod$constmap:2a578b20caa92a5095129d48a2f94bbad08a990f$paramod$5c10e52cdc159999f3945c97d8a1bfa2ca0de2dc\_90_shift_shiftx for cells of type $shiftx. Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=12 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=1\Y_WIDTH=13 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu. Using extmapper simplemap for cells of type $reduce_xor. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=20\Y_WIDTH=20 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=16\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=4 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=11 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=6 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=8 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=6 for cells of type $pmux. Using extmapper simplemap for cells of type $reduce_xnor. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=1\Y_WIDTH=9 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using template $paramod$constmap:66d421c313e4e958be776b99540ac2de3b59fdbc$paramod$9b74a473ccd678a23e1df4cc12019cbbece20051\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=31\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=30\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=16\Y_WIDTH=16 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=1\Y_WIDTH=6 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu. Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=4 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=5 for cells of type $pmux. Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=26\Y_WIDTH=26 for cells of type $alu. Using template $paramod$constmap:684fca2758d270a6aba8ac07bc0dd26758fbc9a0$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx for cells of type $shiftx. Analyzing pattern of constant bits for this cell: Constant input on bit 0 of port A: 1'0 Constant input on bit 1 of port A: 1'0 Constant input on bit 2 of port A: 1'0 Constant input on bit 3 of port A: 1'0 Constant input on bit 4 of port A: 1'1 Constant input on bit 5 of port A: 1'1 Constant input on bit 6 of port A: 1'1 Constant input on bit 7 of port A: 1'1 Constant input on bit 8 of port A: 1'0 Constant input on bit 9 of port A: 1'0 Constant input on bit 10 of port A: 1'0 Constant input on bit 11 of port A: 1'0 Constant input on bit 12 of port A: 1'1 Constant input on bit 13 of port A: 1'1 Constant input on bit 14 of port A: 1'1 Constant input on bit 15 of port A: 1'1 Creating constmapped module `$paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx'. 75.31.141. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $procmux$36239. dead port 2/2 on $mux $procmux$36233. dead port 2/2 on $mux $procmux$36227. dead port 2/2 on $mux $procmux$36221. Removed 4 multiplexer ports. <suppressed ~4033 debug messages> 75.31.142. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx. <suppressed ~3 debug messages> Removed 0 unused cells and 11 unused wires. Using template $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx for cells of type $shiftx. Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=7 for cells of type $pmux. Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=13\Y_WIDTH=13 for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu. No more expansions possible. <suppressed ~1299 debug messages> 75.32. Executing OPT pass (performing simple optimizations). 75.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~3446 debug messages> 75.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3954 debug messages> Removed a total of 1318 cells. 75.32.3. Executing OPT_DFF pass (perform DFF optimizations). 75.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 979 unused cells and 4656 unused wires. <suppressed ~991 debug messages> 75.32.5. Finished fast OPT passes. 75.33. Executing ICE40_OPT pass (performing simple optimizations). 75.33.1. Running ICE40 specific optimizations. Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24972.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24972.BB [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24981.slice[0].carry: CO=\blinker_I.tick_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24987.slice[0].carry: CO=\gps_uart_I.uart_div [1] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24987.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$24987.C [11] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24990.slice[0].carry: CO=\gps_uart_I.uart_rx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24993.slice[0].carry: CO=\gps_uart_I.uart_rx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24999.slice[0].carry: CO=\gps_uart_I.uart_rx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25005.slice[0].carry: CO=\gps_uart_I.uart_rx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25008.slice[0].carry: CO=\gps_uart_I.uart_tx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25011.slice[0].carry: CO=\gps_uart_I.uart_tx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25014.slice[0].carry: CO=\gps_uart_I.uart_tx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25020.slice[0].carry: CO=\gps_uart_I.uart_tx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25023.slice[0].carry: CO=\i2c_I.core_I.cyc_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25026.slice[0].carry: CO=\i2c_I.core_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25035.slice[0].carry: CO=\sys_mgr_I.rst_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25083.slice[0].carry: CO=\soc_I.cpu_I.reg_pc [2] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25086.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25086.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25101.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [2] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25104.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25107.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25107.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25110.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25110.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25113.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25113.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25116.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25116.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25131.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25131.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25155.slice[0].carry: CO=\soc_I.e1_buf_I.buf_tx_ts [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25158.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25158.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25161.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25161.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25167.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m0_addr_i [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25170.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m1_addr_i [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25173.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.len [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25176.slice[0].carry: CO=\soc_I.uart_I.uart_div [1] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25176.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$25176.C [11] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25179.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25182.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25188.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25194.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25197.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.div_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25200.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25203.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25209.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25221.slice[0].carry: CO=\soc_I.usb_I.rx_pkt_I.bit_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25221.slice[3].carry: CO=$auto$alumacc.cc:485:replace_alu$25221.C [3] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25224.slice[0].carry: CO=\soc_I.usb_I.trans_I.mc_pc [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25239.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25239.B [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25239.slice[2].carry: CO=1'0 Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25242.slice[0].carry: CO=\soc_I.usb_I.tx_ll_I.bs_cnt [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25245.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25245.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25248.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25248.A [0] Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25251.slice[0].carry: CO=\spi_mux_I.tick_cnt [0] 75.33.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~42 debug messages> 75.33.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.33.4. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30655 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12179.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30654 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12179.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30653 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12179.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30651 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12196.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30650 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12196.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30649 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12196.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35249 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [31], Q = \misc_I.wb_rdata [31], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35248 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [30], Q = \misc_I.wb_rdata [30], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35247 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [29], Q = \misc_I.wb_rdata [29], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35246 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [28], Q = \misc_I.wb_rdata [28], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35245 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [27], Q = \misc_I.wb_rdata [27], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35244 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [26], Q = \misc_I.wb_rdata [26], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35243 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [25], Q = \misc_I.wb_rdata [25], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35242 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [24], Q = \misc_I.wb_rdata [24], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35241 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [23], Q = \misc_I.wb_rdata [23], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35240 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [22], Q = \misc_I.wb_rdata [22], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35239 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [21], Q = \misc_I.wb_rdata [21], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35238 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [20], Q = \misc_I.wb_rdata [20], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35233 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [15], Q = \misc_I.wb_rdata [15], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35232 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [14], Q = \misc_I.wb_rdata [14], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35231 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [13], Q = \misc_I.wb_rdata [13], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35230 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [12], Q = \misc_I.wb_rdata [12], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35225 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [7], Q = \misc_I.wb_rdata [7], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35224 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [6], Q = \misc_I.wb_rdata [6], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35223 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [5], Q = \misc_I.wb_rdata [5], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35222 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [4], Q = \misc_I.wb_rdata [4], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$31251 ($_SDFF_PP0_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12222.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.samp_cnt [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34819 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [31], Q = \soc_I.cpu_I.decoded_imm [31], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34818 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [30], Q = \soc_I.cpu_I.decoded_imm [30], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34817 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [29], Q = \soc_I.cpu_I.decoded_imm [29], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34816 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [28], Q = \soc_I.cpu_I.decoded_imm [28], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34815 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [27], Q = \soc_I.cpu_I.decoded_imm [27], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34814 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [26], Q = \soc_I.cpu_I.decoded_imm [26], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34813 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [25], Q = \soc_I.cpu_I.decoded_imm [25], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34812 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [24], Q = \soc_I.cpu_I.decoded_imm [24], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34811 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [23], Q = \soc_I.cpu_I.decoded_imm [23], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34810 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [22], Q = \soc_I.cpu_I.decoded_imm [22], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34809 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [21], Q = \soc_I.cpu_I.decoded_imm [21], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34808 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [20], Q = \soc_I.cpu_I.decoded_imm [20], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34807 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [19], Q = \soc_I.cpu_I.decoded_imm [19], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34806 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [18], Q = \soc_I.cpu_I.decoded_imm [18], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34805 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [17], Q = \soc_I.cpu_I.decoded_imm [17], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34804 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [16], Q = \soc_I.cpu_I.decoded_imm [16], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34803 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [15], Q = \soc_I.cpu_I.decoded_imm [15], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34802 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [14], Q = \soc_I.cpu_I.decoded_imm [14], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34801 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [13], Q = \soc_I.cpu_I.decoded_imm [13], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34800 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [12], Q = \soc_I.cpu_I.decoded_imm [12], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34799 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [11], Q = \soc_I.cpu_I.decoded_imm [11], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34798 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [10], Q = \soc_I.cpu_I.decoded_imm [10], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34797 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [9], Q = \soc_I.cpu_I.decoded_imm [9], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34796 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [8], Q = \soc_I.cpu_I.decoded_imm [8], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34795 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [7], Q = \soc_I.cpu_I.decoded_imm [7], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34794 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [6], Q = \soc_I.cpu_I.decoded_imm [6], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34793 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [5], Q = \soc_I.cpu_I.decoded_imm [5], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34792 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [4], Q = \soc_I.cpu_I.decoded_imm [4], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34791 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [3], Q = \soc_I.cpu_I.decoded_imm [3], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34790 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [2], Q = \soc_I.cpu_I.decoded_imm [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34789 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [1], Q = \soc_I.cpu_I.decoded_imm [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30645 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12211.B_AND_S [2], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30644 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12211.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [1], rval = 1'0). Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30643 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12211.Y_B [0], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [0], rval = 1'0). 75.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 62 unused cells and 32 unused wires. <suppressed ~63 debug messages> 75.33.6. Rerunning OPT passes. (Removed registers in this run.) 75.33.7. Running ICE40 specific optimizations. 75.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.33.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~132 debug messages> Removed a total of 44 cells. 75.33.10. Executing OPT_DFF pass (perform DFF optimizations). 75.33.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 44 unused wires. <suppressed ~1 debug messages> 75.33.12. Rerunning OPT passes. (Removed registers in this run.) 75.33.13. Running ICE40 specific optimizations. 75.33.14. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.33.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.33.16. Executing OPT_DFF pass (perform DFF optimizations). 75.33.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.33.18. Finished OPT passes. (There is nothing left to do.) 75.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 75.35. Executing TECHMAP pass (map to technology primitives). 75.35.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 75.35.2. Continuing TECHMAP pass. Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_. Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_. Using template \$_DFF_P_ for cells of type $_DFF_P_. Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_. Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_. Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_. Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. No more expansions possible. <suppressed ~2236 debug messages> 75.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping top.$auto$alumacc.cc:485:replace_alu$24981.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24987.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24987.slice[11].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24990.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24993.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$24999.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25005.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25008.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25011.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25014.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25020.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25023.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25026.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25035.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25083.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25086.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25101.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25104.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25107.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25110.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25113.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25116.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25131.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25155.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25158.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25161.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25167.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25170.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25173.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25176.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25176.slice[11].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25179.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25182.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25188.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25194.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25197.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25200.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25203.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25209.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25221.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25221.slice[3].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25224.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25239.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25239.slice[2].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25242.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25245.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25248.slice[0].carry ($lut). Mapping top.$auto$alumacc.cc:485:replace_alu$25251.slice[0].carry ($lut). 75.38. Executing ICE40_OPT pass (performing simple optimizations). 75.38.1. Running ICE40 specific optimizations. 75.38.2. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1263 debug messages> 75.38.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~1359 debug messages> Removed a total of 453 cells. 75.38.4. Executing OPT_DFF pass (perform DFF optimizations). 75.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 12113 unused wires. <suppressed ~1 debug messages> 75.38.6. Rerunning OPT passes. (Removed registers in this run.) 75.38.7. Running ICE40 specific optimizations. 75.38.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 75.38.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 75.38.10. Executing OPT_DFF pass (perform DFF optimizations). 75.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 75.38.12. Finished OPT passes. (There is nothing left to do.) 75.39. Executing TECHMAP pass (map to technology primitives). 75.39.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 75.39.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 75.40. Executing ABC pass (technology mapping using ABC). 75.40.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'.. Extracted 6569 gates and 9036 wires to a netlist network with 2465 inputs and 1841 outputs. 75.40.1.1. Executing ABC. Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_blif <abc-temp-dir>/input.blif ABC: + read_lut <abc-temp-dir>/lutdefs.txt ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + dch -f ABC: + if ABC: + mfs2 ABC: + lutpack -S 1 ABC: + dress ABC: Total number of equiv classes = 2250. ABC: Participating nodes from both networks = 4762. ABC: Participating nodes from the first network = 2268. ( 79.38 % of nodes) ABC: Participating nodes from the second network = 2494. ( 87.29 % of nodes) ABC: Node pairs (any polarity) = 2268. ( 79.38 % of names can be moved) ABC: Node pairs (same polarity) = 1998. ( 69.93 % of names can be moved) ABC: Total runtime = 0.08 sec ABC: + write_blif <abc-temp-dir>/output.blif 75.40.1.2. Re-integrating ABC results. ABC RESULTS: $lut cells: 2856 ABC RESULTS: internal signals: 4730 ABC RESULTS: input signals: 2465 ABC RESULTS: output signals: 1841 Removing temp directory. 75.41. Executing ICE40_WRAPCARRY pass (wrap carries). 75.42. Executing TECHMAP pass (map to technology primitives). 75.42.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. 75.42.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~22 debug messages> Removed 140 unused cells and 5969 unused wires. 75.43. Executing OPT_LUT pass (optimize LUTs). Discovering LUTs. Number of LUTs: 3533 1-LUT 149 2-LUT 978 3-LUT 1253 4-LUT 1153 Eliminating LUTs. Number of LUTs: 3529 1-LUT 149 2-LUT 978 3-LUT 1249 4-LUT 1153 Combining LUTs. Number of LUTs: 3268 1-LUT 148 2-LUT 653 3-LUT 1128 4-LUT 1339 Eliminated 4 LUTs. Combined 261 LUTs. <suppressed ~18883 debug messages> 75.44. Executing TECHMAP pass (map to technology primitives). 75.44.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 75.44.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011110011111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101110111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100111110100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111110001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1101001100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111001111000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101111111110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001001100111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111010001000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001101011100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011101100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100010011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000110011001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110101100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010101010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111011111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011011100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100011101110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001111110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110101110111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110010100011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010101111101010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010111111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11110001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000100011110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110011111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000110100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101100001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111001011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001011001101001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111011101110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000101010100010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010001111001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001110111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100010000001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000011101110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011010111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101001111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010000011001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100111000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011100100001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1011101111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'00011000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'11100111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100101111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000110000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111110000001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101110001010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010111111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010001000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110110000110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000011111 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'01000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000111111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000100000001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010001010001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010100000101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000101010100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0011101000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=3\LUT=8'10111100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0001000101000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010001000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010101011000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1000101110111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100010100 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0010000100010010 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000010000000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100010100110101 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1100001101100110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'0101010111000011 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1111011101000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=4\LUT=16'1001110010011100 for cells of type $lut. No more expansions possible. <suppressed ~6274 debug messages> Removed 0 unused cells and 6958 unused wires. 75.45. Executing AUTONAME pass. Renamed 174767 objects in module top (112 iterations). <suppressed ~8268 debug messages> 75.46. Executing HIERARCHY pass (managing design hierarchy). 75.46.1. Analyzing design hierarchy.. Top module: \top 75.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 75.47. Printing statistics. === top === Number of wires: 3777 Number of wire bits: 18573 Number of public wires: 3777 Number of public wire bits: 18573 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 6302 SB_CARRY 719 SB_DFF 317 SB_DFFE 575 SB_DFFER 431 SB_DFFES 44 SB_DFFESR 220 SB_DFFESS 45 SB_DFFR 131 SB_DFFS 49 SB_DFFSR 374 SB_DFFSS 27 SB_GB 2 SB_GB_IO 1 SB_IO 25 SB_LEDDA_IP 1 SB_LUT4 3307 SB_MAC16 6 SB_PLL40_CORE 1 SB_RAM40_4K 16 SB_RAM40_4KNR 4 SB_RGBA_DRV 1 SB_SPI 1 SB_SPRAM256KA 4 SB_WARMBOOT 1 75.48. Executing CHECK pass (checking for obvious problems). checking module top.. found and reported 0 problems. 75.49. Executing JSON backend. Warnings: 9 unique messages, 17 total End of script. Logfile hash: e7c68d8612, CPU: user 21.53s system 0.15s, MEM: 289.16 MB peak Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os) Time spent: 22% 38x opt_expr (5 sec), 19% 31x opt_clean (4 sec), ... nextpnr-ice40 --pre-pack data/clocks.py --pre-pack data/opt.py --seed 15 --no-promote-globals --timing-allow-fail \ --up5k --package sg48 \ -l /build/gateware/icE1usb/build-tmp/icE1usb.pnr.rpt \ --json /build/gateware/icE1usb/build-tmp/icE1usb.json \ --pcf /build/gateware/icE1usb/data/top-ice1usb.pcf \ --asc /build/gateware/icE1usb/build-tmp/icE1usb.asc Info: constrained 'e1A_rx_hi_p' to bel 'X8/Y31/io0' Warning: unmatched constraint 'e1A_rx_hi_n' (on line 3) Info: constrained 'e1A_rx_lo_p' to bel 'X16/Y31/io0' Warning: unmatched constraint 'e1A_rx_lo_n' (on line 5) Info: constrained 'e1A_tx_hi' to bel 'X9/Y31/io0' Info: constrained 'e1A_tx_lo' to bel 'X9/Y31/io1' Info: constrained 'e1B_rx_hi_p' to bel 'X19/Y31/io0' Warning: unmatched constraint 'e1B_rx_hi_n' (on line 10) Info: constrained 'e1B_rx_lo_p' to bel 'X18/Y31/io0' Warning: unmatched constraint 'e1B_rx_lo_n' (on line 12) Info: constrained 'e1B_tx_hi' to bel 'X13/Y31/io1' Info: constrained 'e1B_tx_lo' to bel 'X13/Y31/io0' Info: constrained 'e1_rx_bias[0]' to bel 'X17/Y31/io0' Info: constrained 'e1_rx_bias[1]' to bel 'X12/Y31/io1' Info: constrained 'usb_dp' to bel 'X16/Y0/io0' Info: constrained 'usb_dn' to bel 'X15/Y0/io0' Info: constrained 'usb_pu' to bel 'X17/Y0/io0' Info: constrained 'flash_mosi' to bel 'X23/Y0/io0' Info: constrained 'flash_miso' to bel 'X23/Y0/io1' Info: constrained 'flash_clk' to bel 'X24/Y0/io0' Info: constrained 'flash_cs_n' to bel 'X24/Y0/io1' Info: constrained 'e1_led_rclk' to bel 'X22/Y0/io1' Info: constrained 'gps_reset_n' to bel 'X13/Y0/io1' Info: constrained 'gps_rx' to bel 'X6/Y0/io0' Info: constrained 'gps_tx' to bel 'X5/Y0/io0' Info: constrained 'gps_pps' to bel 'X8/Y0/io0' Info: constrained 'i2c_sda' to bel 'X9/Y0/io1' Info: constrained 'i2c_scl' to bel 'X9/Y0/io0' Info: constrained 'gpio[0]' to bel 'X19/Y0/io0' Info: constrained 'gpio[1]' to bel 'X19/Y0/io1' Info: constrained 'gpio[2]' to bel 'X21/Y0/io1' Info: constrained 'clk_in' to bel 'X6/Y0/io1' Info: constrained 'clk_tune_hi' to bel 'X7/Y0/io0' Info: constrained 'clk_tune_lo' to bel 'X7/Y0/io1' Info: constrained 'dbg_rx' to bel 'X18/Y0/io1' Info: constrained 'dbg_tx' to bel 'X18/Y0/io0' Info: constrained 'rgb[0]' to bel 'X4/Y31/io0' Info: constrained 'rgb[1]' to bel 'X5/Y31/io0' Info: constrained 'rgb[2]' to bel 'X6/Y31/io0' Info: constraining clock net 'clk_sys' to 30.72 MHz Info: constraining clock net 'clk_48m' to 48.00 MHz 1 251 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='wb_ack[1]', ena=None, clk='clk_sys') -------------- 0 252 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='spi_mux_I.srio_dat_o_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 1 257 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.wb_ack[1]', ena=None, clk='clk_sys') -------------- 0 72 ControlSet(rs=None, ena=None, clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.tx_ll_I.lvl_prev_SB_DFFSS_Q_S', ena=None, clk='clk_48m') -------------- 1 73 ControlSet(rs=None, ena=None, clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O', ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m') 1 12 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O', ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m') -------------- 2 75 ControlSet(rs=None, ena=None, clk='clk_48m') 2 ControlSet(rs='soc_I.usb_I.rx_pkt_I.state[0]', ena='soc_I.usb_I.rx_pkt_I.crc5_ok_SB_DFFESR_Q_E', clk='clk_48m') -------------- 3 80 ControlSet(rs=None, ena=None, clk='clk_48m') 5 ControlSet(rs='soc_I.usb_I.rx_pkt_I.state[0]', ena='soc_I.usb_I.rx_pkt_I.bit_cnt_SB_DFFESR_Q_E', clk='clk_48m') -------------- 0 82 ControlSet(rs=None, ena=None, clk='clk_48m') 2 ControlSet(rs='soc_I.usb_I.rx_ll_I.samp_sync', ena=None, clk='clk_48m') -------------- 0 83 ControlSet(rs=None, ena=None, clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.rx_ll_I.samp_cnt_SB_DFFSR_Q_R', ena=None, clk='clk_48m') -------------- 0 84 ControlSet(rs=None, ena=None, clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_LUT4_I2_O[1]', ena='soc_I.usb_I.rx_pkt_I.crc_in_first_SB_DFFESS_Q_E', clk='clk_48m') -------------- 5 15 ControlSet(rs=None, ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_eop_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_rep_state_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sym_same_0_SB_LUT4_I3_1_O', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sym_se_0', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 3 87 ControlSet(rs=None, ena=None, clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') -------------- 0 86 ControlSet(rs=None, ena=None, clk='clk_48m') 2 ControlSet(rs='soc_I.usb_I.eps_write_0', ena=None, clk='clk_48m') -------------- 0 89 ControlSet(rs=None, ena=None, clk='clk_48m') 3 ControlSet(rs='soc_I.usb_I.eps_bus_clear', ena=None, clk='clk_48m') -------------- 0 94 ControlSet(rs=None, ena=None, clk='clk_48m') 5 ControlSet(rs='soc_I.usb_I.csr_bus_clear', ena=None, clk='clk_48m') -------------- 0 264 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='soc_I.uart_I.ub_rdata_SB_DFFSR_Q_9_R', ena=None, clk='clk_sys') -------------- 0 265 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', ena=None, clk='clk_sys') -------------- 4 270 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.uart_I.uart_tx_I.bit_cnt_SB_DFFESS_Q_S', ena='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', clk='clk_sys') -------------- 4 275 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_S', ena='soc_I.uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_E', clk='clk_sys') -------------- 1 276 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_store_SB_DFFESS_Q_E', clk='clk_sys') -------------- 5 281 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_stalu_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O', clk='clk_sys') -------------- 0 282 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_stalu_SB_DFFESR_Q_E', clk='clk_sys') -------------- 2 284 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_is_lh_SB_DFFESR_Q_E', clk='clk_sys') -------------- 1 285 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_branch_SB_DFFESR_Q_E[2]', clk='clk_sys') -------------- 1 286 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 13 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys') 1 ControlSet(rs='soc_I.iobuf_I.dma_I.ack_rd_SB_LUT4_O_I2_SB_LUT4_I2_O[1]', ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys') 1 287 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.iobuf_I.dma_I.ack_rd_SB_LUT4_O_I2_SB_LUT4_I2_O[1]', ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys') -------------- 0 288 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.wb_rdata_SB_DFFSR_Q_14_R', ena=None, clk='clk_sys') -------------- 0 290 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_DFFSR_D_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys') -------------- 0 292 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_I3_SB_DFFSR_D_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys') -------------- 0 296 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_DFF_D_Q_SB_LUT4_I3_2_O', ena=None, clk='clk_sys') -------------- 0 297 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S_SB_DFFSS_D_Q_SB_LUT4_I3_1_O_SB_LUT4_I2_O', ena=None, clk='clk_sys') -------------- 1 299 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S_SB_DFFSS_D_Q_SB_LUT4_I3_1_O[0]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S_SB_DFFSS_D_Q_SB_LUT4_I3_O_SB_LUT4_I3_O', clk='clk_sys') -------------- 0 300 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S[2]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_E', clk='clk_sys') -------------- 0 301 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_DFFESS_Q_S[2]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_DFFESS_Q_E', clk='clk_sys') -------------- 0 302 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_DFFESS_Q_S[2]', ena=None, clk='clk_sys') -------------- 3 19 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_buf_I.buf_tx_re_SB_LUT4_O_I3', clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_DFFER_Q_E[1]', clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_LUT4_I2_O', clk='clk_sys') -------------- 1 303 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 304 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I2_O', clk='clk_sys') -------------- 0 308 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 0 312 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O', ena=None, clk='clk_sys') -------------- 0 316 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_I2_SB_LUT4_I3_O', ena=None, clk='clk_sys') -------------- 0 318 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_DFF_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 0 320 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_DFF_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 5 327 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_1_O_SB_LUT4_O_I3_SB_LUT4_I2_O', clk='clk_sys') -------------- 4 332 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_1_O_SB_LUT4_O_I3_SB_DFFESR_Q_E', clk='clk_sys') -------------- 6 339 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_1_O_SB_LUT4_I2_O', clk='clk_sys') -------------- 0 340 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_DFF_D_Q[0]', ena=None, clk='clk_sys') -------------- 0 341 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.mem_state_SB_DFFESR_Q_R', ena='soc_I.cpu_I.mem_valid_SB_DFFESR_Q_E', clk='clk_sys') -------------- 2 343 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='soc_I.cpu_I.mem_state_SB_DFFESR_Q_R', ena='soc_I.cpu_I.mem_state_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 344 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.mem_do_wdata_SB_DFFESS_Q_S[0]', ena='soc_I.cpu_I.mem_do_wdata_SB_DFFESS_Q_E', clk='clk_sys') -------------- 0 345 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.mem_do_rdata_SB_DFFESS_Q_S[2]', ena='soc_I.cpu_I.mem_do_rdata_SB_DFFESS_Q_E', clk='clk_sys') -------------- 0 346 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.instr_or_SB_DFFESR_Q_E', ena=None, clk='clk_sys') -------------- 0 347 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.instr_lbu_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]', ena='soc_I.cpu_I.mem_do_prefetch_SB_DFFESR_Q_E', clk='clk_sys') -------------- 1 348 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.instr_lbu_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I3_O[0]', ena='soc_I.cpu_I.mem_do_rinst_SB_DFFESS_Q_E', clk='clk_sys') -------------- 0 349 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.decoder_pseudo_trigger_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 0 350 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='soc_I.cpu_I.alu_wait_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 1 192 ControlSet(rs='rst_sys', ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys') 3 ControlSet(rs='rst_sys', ena='misc_I.bus_we_boot', clk='clk_sys') 3 ControlSet(rs='rst_sys', ena='misc_I.dfu_I.wb_sel_SB_DFFER_Q_E', clk='clk_sys') 2 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E', clk='clk_sys') 7 ControlSet(rs='rst_sys', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I3_SB_DFFER_Q_E', clk='clk_sys') 2 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.dma_I.state_SB_DFFER_Q_E', clk='clk_sys') 3 ControlSet(rs='rst_sys', ena='soc_I.rgb_I.led_ctrl_SB_DFFER_Q_E', clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys') -------------- 0 351 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_I.gf_I.state_SB_DFFESS_Q_E', clk='clk_sys') -------------- 1 352 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='i2c_I.core_I.sda_oe_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 353 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='i2c_I.core_I.scl_oe_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 354 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_I.gf_I.state_SB_DFFESS_Q_E', clk='clk_sys') -------------- 5 67 ControlSet(rs='rst_48m', ena=None, clk='clk_48m') 3 ControlSet(rs='rst_48m', ena='soc_I.usb_I.tx_ll_I.state_SB_DFFER_Q_E', clk='clk_48m') 2 ControlSet(rs='rst_48m', ena='soc_I.usb_I.tx_ll_I.br_cnt[2]', clk='clk_48m') -------------- 0 355 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='misc_I.pps_flt_I.state_SB_LUT4_I1_O[1]', ena='misc_I.pps_flt_I.state_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 356 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='misc_I.dfu_I.btn_flt_I.fall_SB_DFF_Q_D', ena='misc_I.dfu_I.btn_flt_I.state_SB_DFFESR_Q_E', clk='clk_sys') -------------- 0 363 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='misc_I.bus_we_led_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 0 368 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='i2c_I.core_I.cyc_cnt_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 2 371 ControlSet(rs=None, ena=None, clk='clk_sys') 3 ControlSet(rs='i2c_I.core_I.bit_cnt_SB_DFFESR_Q_R[1]', ena='i2c_I.core_I.bit_last_SB_DFFE_Q_E', clk='clk_sys') -------------- 0 378 ControlSet(rs=None, ena=None, clk='clk_sys') 7 ControlSet(rs='gps_uart_I.ub_rdata_SB_DFFSR_Q_R', ena=None, clk='clk_sys') -------------- 0 379 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='gps_uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', ena=None, clk='clk_sys') -------------- 4 384 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='gps_uart_I.uart_tx_I.bit_cnt_SB_DFFESS_Q_S', ena='gps_uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', clk='clk_sys') -------------- 4 389 ControlSet(rs=None, ena=None, clk='clk_sys') 5 ControlSet(rs='gps_uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_S', ena='gps_uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_E', clk='clk_sys') -------------- 0 390 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_DFFESR_Q_E', clk='clk_sys') -------------- 3 393 ControlSet(rs=None, ena=None, clk='clk_sys') 3 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S_SB_DFFSS_D_Q_SB_LUT4_I3_O_SB_LUT4_I3_O', clk='clk_sys') -------------- 3 397 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S_SB_DFFSS_D_Q_SB_LUT4_I3_O[0]', clk='clk_sys') -------------- 1 399 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='e1A_rx_lo_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O_SB_LUT4_I2_O', clk='clk_sys') -------------- 1 401 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O_SB_LUT4_I2_O', clk='clk_sys') -------------- 1 405 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs=None, ena='tick_e1_tx[0]', clk='clk_sys') -------------- 0 96 ControlSet(rs=None, ena=None, clk='clk_48m') 2 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_data_crc_SB_DFFE_Q_E', clk='clk_48m') -------------- 1 100 ControlSet(rs=None, ena=None, clk='clk_48m') 4 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.mc_op_tx', clk='clk_48m') -------------- 4 104 ControlSet(rs=None, ena=None, clk='clk_48m') 4 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.mc_op_ld', clk='clk_48m') -------------- 2 111 ControlSet(rs=None, ena=None, clk='clk_48m') 7 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.epfw_issue_wb_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]', clk='clk_48m') -------------- 1 117 ControlSet(rs=None, ena=None, clk='clk_48m') 6 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.ep_bd_dual_SB_LUT4_I2_O[2]', clk='clk_48m') -------------- 3 120 ControlSet(rs=None, ena=None, clk='clk_48m') 3 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.bd_state_SB_DFFE_Q_E', clk='clk_48m') -------------- 0 124 ControlSet(rs=None, ena=None, clk='clk_48m') 4 ControlSet(rs=None, ena='soc_I.usb_I.rxpkt_done_ok', clk='clk_48m') -------------- 0 127 ControlSet(rs=None, ena=None, clk='clk_48m') 3 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.token_data_SB_DFFE_Q_E[1]', clk='clk_48m') -------------- 0 406 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.ack_rd_SB_LUT4_O_I2_SB_LUT4_I2_O[1]', clk='clk_sys') -------------- 1 410 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs=None, ena='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I3_I2', clk='clk_sys') -------------- 0 414 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs=None, ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_1_D_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_LUT4_I0_O[0]', clk='clk_sys') -------------- 1 415 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs=None, ena='soc_I.cpu_I.reg_op1_SB_DFFE_Q_31_E', clk='clk_sys') -------------- 2 417 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs=None, ena='soc_I.cpu_I.instr_sra_SB_LUT4_I2_O[3]', clk='clk_sys') -------------- 4 421 ControlSet(rs=None, ena=None, clk='clk_sys') 4 ControlSet(rs=None, ena='soc_I.bridge_I.ram_rdy_SB_LUT4_I0_O[1]', clk='clk_sys') -------------- 0 423 ControlSet(rs=None, ena=None, clk='clk_sys') 2 ControlSet(rs=None, ena='i2c_I.stb', clk='clk_sys') -------------- 1 424 ControlSet(rs=None, ena=None, clk='clk_sys') 1 ControlSet(rs=None, ena='i2c_I.core_I.bit_last_SB_DFFE_Q_E', clk='clk_sys') -------------- Control Set Optimizer: cost 100 to reduce control sets from 207 to 99 Total control sets: 99 1 2 3 1 4 1 6 1 8 13 9 21 10 12 11 3 12 3 13 5 14 2 15 2 16 5 17 2 18 1 19 1 20 4 24 1 25 1 26 1 29 1 31 2 32 5 33 2 45 1 55 1 60 1 67 1 127 1 192 1 424 1 1 ControlSet(rs='sys_mgr_I.rst_30m72_i', ena=None, clk='clk_48m') 1 ControlSet(rs='sys_mgr_I.pll_lock_SB_LUT4_I3_O', ena=None, clk='clk_sys') 3 ControlSet(rs='sys_mgr_I.pll_lock_SB_LUT4_I3_O', ena='sys_mgr_I.rst_30m72_i', clk='clk_sys') 4 ControlSet(rs='soc_I.usb_I.txll_start', ena='soc_I.usb_I.tx_ll_I.br_cnt[2]', clk='clk_48m') 6 ControlSet(rs='rst_sys', ena=None, clk='clk_48m') 8 ControlSet(rs=None, ena='spi_mux_I.shift_ce', clk='clk_sys') 8 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.token_data_SB_DFFE_Q_9_E[1]', clk='clk_48m') 8 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_I1', ena='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_DFFESR_Q_D_SB_LUT4_I2_O', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[4]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[4]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[3]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[1]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='misc_I.bus_we_gpio', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[1]', clk='clk_sys') 8 ControlSet(rs=None, ena='soc_I.e1_buf_I.t_done[2]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[2]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[3]', clk='clk_sys') 8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[2]', clk='clk_sys') 9 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.pid_cap', clk='clk_48m') 9 ControlSet(rs='soc_I.uart_I.ub_rdata_rst', ena=None, clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.ub_wr_data', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_fifo_I.ram_rd_ena', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='dbg_tx_SB_DFFES_Q_E', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.urf_wren', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_fifo_I.ram_rd_ena', clk='clk_sys') 9 ControlSet(rs=None, ena='soc_I.uart_I.uart_rx_I.ce', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_led', clk='clk_sys') 9 ControlSet(rs=None, ena='tick_e1_rx[0]', clk='clk_sys') 9 ControlSet(rs=None, ena='i2c_I.ack_out_SB_DFFE_Q_E', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_uart_I.ub_wr_data', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_tx_SB_DFFES_Q_E', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_fifo_I.ram_rd_ena', clk='clk_sys') 9 ControlSet(rs=None, ena='gps_uart_I.uart_rx_I.ce', clk='clk_sys') 9 ControlSet(rs='gps_uart_I.ub_rdata_rst', ena=None, clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_e1[1]', clk='clk_sys') 9 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.m1_addr_ce', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_e1[0]', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_fifo_I.ram_rd_ena', clk='clk_sys') 9 ControlSet(rs='rst_sys', ena='gps_uart_I.urf_wren', clk='clk_sys') 10 ControlSet(rs='soc_I.usb_I.trans_I.len_ld', ena=None, clk='clk_48m') 10 ControlSet(rs='rst_48m', ena='soc_I.usb_I.cr_bus_we', clk='clk_48m') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[4]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[4]', clk='clk_sys') 10 ControlSet(rs='i2c_I.bus_clr', ena=None, clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[3]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[2]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[3]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[1]', clk='clk_sys') 10 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I3_O[2]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[2]', clk='clk_sys') 10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[1]', clk='clk_sys') 11 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m') 11 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.len_dec', clk='clk_48m') 11 ControlSet(rs='soc_I.usb_I.trans_I.mc_op_zlen', ena=None, clk='clk_48m') 12 ControlSet(rs=None, ena='soc_I.uart_I.ub_wr_div', clk='clk_sys') 12 ControlSet(rs='misc_I.bus_clr', ena=None, clk='clk_sys') 12 ControlSet(rs=None, ena='gps_uart_I.ub_wr_div', clk='clk_sys') 13 ControlSet(rs=None, ena='soc_I.cpu_I.decoder_pseudo_trigger_SB_LUT4_I2_O[0]', clk='clk_sys') 13 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys') 13 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_clk[1]', clk='clk_sys') 13 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_clk[0]', clk='clk_sys') 13 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_buf_I.buf_tx_ts_SB_DFFES_Q_E', clk='clk_sys') 14 ControlSet(rs=None, ena='soc_I.usb_I.ep_status_I.p_read_2', clk='clk_48m') 14 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.m0_addr_ce', clk='clk_sys') 15 ControlSet(rs=None, ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m') 15 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='tick_e1_tx[0]', clk='clk_sys') 16 ControlSet(rs='soc_I.wb_48m_xclk_I.s_cyc_SB_LUT4_I3_O', ena=None, clk='clk_sys') 16 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.crc_in_valid', clk='clk_48m') 16 ControlSet(rs='soc_I.usb_I.ep_status_I.s_zero_2', ena='soc_I.usb_I.ep_status_I.s_read_2', clk='clk_48m') 16 ControlSet(rs=None, ena='soc_I.ub_ack', clk='clk_48m') 16 ControlSet(rs=None, ena='soc_I.e1_buf_tx_re[0]', clk='clk_sys') 17 ControlSet(rs='soc_I.e1_I.bus_clr', ena=None, clk='clk_sys') 17 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_1_D_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_LUT4_I0_1_O', clk='clk_sys') 18 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.instr_or_SB_DFFESR_Q_E', clk='clk_sys') 19 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena=None, clk='clk_sys') 20 ControlSet(rs='soc_I.usb_I.oob_sof_SB_LUT4_I2_O', ena=None, clk='clk_48m') 20 ControlSet(rs='soc_I.usb_I.phy_I.rx_dn_SB_LUT4_I2_O', ena=None, clk='clk_48m') 20 ControlSet(rs=None, ena='soc_I.cpu_I.trap_SB_LUT4_I3_1_O', clk='clk_sys') 20 ControlSet(rs='misc_I.wb_ack_SB_LUT4_I2_O_SB_LUT4_I3_O', ena=None, clk='clk_sys') 24 ControlSet(rs=None, ena='soc_I.e1_buf_rx_we[0]', clk='clk_sys') 25 ControlSet(rs=None, ena='soc_I.e1_buf_I.t_busy_SB_LUT4_I3_O', clk='clk_sys') 26 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena=None, clk='clk_sys') 29 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.crc_in_valid', clk='clk_48m') 31 ControlSet(rs=None, ena='soc_I.cpu_I.instr_lbu_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3]', clk='clk_sys') 31 ControlSet(rs='soc_I.cpu_I.decoded_imm_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I2_1_O', ena='soc_I.cpu_I.decoder_pseudo_trigger_SB_LUT4_I2_O[0]', clk='clk_sys') 32 ControlSet(rs=None, ena='soc_I.pb_rst_n_SB_LUT4_I2_O', clk='clk_sys') 32 ControlSet(rs=None, ena='soc_I.cpu_I.trap_SB_LUT4_I2_O', clk='clk_sys') 32 ControlSet(rs='soc_I.bridge_I.wb_cyc_rst', ena=None, clk='clk_sys') 32 ControlSet(rs=None, ena='soc_I.cpu_I.instr_ecall_ebreak_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[3]', clk='clk_sys') 32 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.ack_rd', clk='clk_sys') 33 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena=None, clk='clk_sys') 33 ControlSet(rs=None, ena='soc_I.cpu_I.alu_ltu_SB_LUT4_I2_O[3]', clk='clk_sys') 45 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.epbam_arb_I.reselect', clk='clk_sys') 55 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.spram_arb_I.reselect', clk='clk_sys') 60 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.alu_wait_SB_LUT4_I3_O[0]', clk='clk_sys') 67 ControlSet(rs='rst_48m', ena=None, clk='clk_48m') 127 ControlSet(rs=None, ena=None, clk='clk_48m') 192 ControlSet(rs='rst_sys', ena=None, clk='clk_sys') 424 ControlSet(rs=None, ena=None, clk='clk_sys') LUT replication: 0 new LUTs in 0 groups Info: Packing constants.. Info: Packing IOs.. Info: clk_in feeds SB_IO sys_mgr_I.gb_in, removing $nextpnr_ibuf clk_in. Info: clk_tune_hi feeds SB_IO misc_I.pdm_clk_I[1].io_reg_I, removing $nextpnr_obuf clk_tune_hi. Info: clk_tune_lo feeds SB_IO misc_I.pdm_clk_I[0].io_reg_I, removing $nextpnr_obuf clk_tune_lo. Info: e1A_rx_hi_p feeds SB_IO e1A_rx_hi_p_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_hi_p. Info: e1A_rx_lo_p feeds SB_IO e1A_rx_lo_p_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_lo_p. Info: e1A_tx_hi feeds SB_IO e1A_tx_hi_SB_IO_PACKAGE_PIN, removing $nextpnr_obuf e1A_tx_hi. Info: e1A_tx_lo feeds SB_IO e1A_tx_lo_SB_IO_PACKAGE_PIN, removing $nextpnr_obuf e1A_tx_lo. Info: e1B_rx_hi_p feeds SB_IO e1_dummy_rx_I[1], removing $nextpnr_ibuf e1B_rx_hi_p. Info: e1B_rx_lo_p feeds SB_IO e1_dummy_rx_I[0], removing $nextpnr_ibuf e1B_rx_lo_p. Info: e1B_tx_hi feeds SB_IO e1_dummy_tx_I[1], removing $nextpnr_obuf e1B_tx_hi. Info: e1B_tx_lo feeds SB_IO e1_dummy_tx_I[0], removing $nextpnr_obuf e1B_tx_lo. Info: e1_led_rclk feeds SB_IO spi_mux_I.iob_I[0], removing $nextpnr_iobuf e1_led_rclk. Info: flash_clk feeds SB_IO spi_mux_I.iob_I[1], removing $nextpnr_iobuf flash_clk. Info: flash_miso feeds SB_IO spi_mux_I.iob_I[2], removing $nextpnr_iobuf flash_miso. Info: flash_mosi feeds SB_IO spi_mux_I.iob_I[3], removing $nextpnr_iobuf flash_mosi. Info: gps_pps feeds SB_IO misc_I.pps_iob_I, removing $nextpnr_ibuf gps_pps. Info: gps_reset_n feeds SB_IO misc_I.gpio_iob_I[3], removing $nextpnr_obuf gps_reset_n. Info: i2c_scl feeds SB_IO i2c_iob_I[1], removing $nextpnr_iobuf i2c_scl. Info: i2c_sda feeds SB_IO i2c_iob_I[0], removing $nextpnr_iobuf i2c_sda. Info: usb_dn feeds SB_IO soc_I.usb_I.phy_I.io_dn_I, removing $nextpnr_iobuf usb_dn. Info: usb_dp feeds SB_IO soc_I.usb_I.phy_I.io_dp_I, removing $nextpnr_iobuf usb_dp. Info: gpio[0] feeds SB_IO misc_I.gpio_iob_I[0], removing $nextpnr_iobuf gpio[0]. Info: gpio[1] feeds SB_IO misc_I.gpio_iob_I[1], removing $nextpnr_iobuf gpio[1]. Info: gpio[2] feeds SB_IO misc_I.gpio_iob_I[2], removing $nextpnr_iobuf gpio[2]. Info: e1_rx_bias[0] feeds SB_IO misc_I.pdm_e1_I[0].io_reg_I, removing $nextpnr_obuf e1_rx_bias[0]. Info: e1_rx_bias[1] feeds SB_IO misc_I.pdm_e1_I[1].io_reg_I, removing $nextpnr_obuf e1_rx_bias[1]. Info: rgb[0] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: rgb[1] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: rgb[2] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO Info: Packing LUT-FFs.. Info: 1791 LCs used as LUT4 only Info: 1703 LCs used as LUT4 and DFF Info: Packing non-LUT FFs.. Info: 510 LCs used as DFF only Info: Packing carries.. Info: 270 LCs used as CARRY only Info: Packing RAMs.. Info: Placing PLLs.. Info: constrained PLL 'sys_mgr_I.pll_I' to X12/Y31/pll_3 Info: Packing special functions.. Info: constrained SB_LEDDA_IP 'soc_I.rgb_I.led_I' to X0/Y31/ledda_ip_2 Info: constrained SB_RGBA_DRV 'soc_I.rgb_I.rgb_drv_I' to X0/Y30/rgba_drv_0 Info: constrained SB_SPI 'soc_I.spi_I.spi_I' to X0/Y0/spi_0 Info: PLL 'sys_mgr_I.pll_I' has LOCK output, need to pass all outputs via LUT Info: constrained 'sys_mgr_I.pll_lock_SB_LUT4_I3_LC' to X1/Y30/lc0 Info: Constraining chains... Info: 216 LCs used to legalise carry chains. Info: Checksum: 0xbd206b2f Info: Annotating ports with timing budgets for target frequency 12.00 MHz Info: Checksum: 0x290952ac Info: Device utilisation: Info: ICESTORM_LC: 4495/ 5280 85% Info: ICESTORM_RAM: 20/ 30 66% Info: SB_IO: 32/ 96 33% Info: SB_GB: 4/ 8 50% Info: ICESTORM_PLL: 1/ 1 100% Info: SB_WARMBOOT: 1/ 1 100% Info: ICESTORM_DSP: 6/ 8 75% Info: ICESTORM_HFOSC: 0/ 1 0% Info: ICESTORM_LFOSC: 0/ 1 0% Info: SB_I2C: 0/ 2 0% Info: SB_SPI: 1/ 2 50% Info: IO_I3C: 0/ 2 0% Info: SB_LEDDA_IP: 1/ 1 100% Info: SB_RGBA_DRV: 1/ 1 100% Info: ICESTORM_SPRAM: 4/ 4 100% Info: Placed 39 cells based on constraints. Info: Creating initial analytic placement for 3600 cells, random placement wirelen = 110077. Info: at initial placer iter 0, wirelen = 3525 Info: at initial placer iter 1, wirelen = 3266 Info: at initial placer iter 2, wirelen = 3326 Info: at initial placer iter 3, wirelen = 3318 Info: Running main analytical placer. Info: at iteration #1, type ALL: wirelen solved = 3253, spread = 38465, legal = 55181; time = 0.43s Info: at iteration #2, type ALL: wirelen solved = 4546, spread = 30601, legal = 48931; time = 0.38s Info: at iteration #3, type ALL: wirelen solved = 5816, spread = 28522, legal = 47169; time = 0.39s Info: at iteration #4, type ALL: wirelen solved = 6568, spread = 27769, legal = 39876; time = 0.38s Info: at iteration #5, type ALL: wirelen solved = 7865, spread = 26743, legal = 42812; time = 0.23s Info: at iteration #6, type ALL: wirelen solved = 8347, spread = 26353, legal = 48459; time = 0.44s Info: at iteration #7, type ALL: wirelen solved = 8919, spread = 26392, legal = 40823; time = 0.30s Info: at iteration #8, type ALL: wirelen solved = 9364, spread = 26336, legal = 38573; time = 0.28s Info: at iteration #9, type ALL: wirelen solved = 9686, spread = 26025, legal = 40567; time = 0.25s Info: at iteration #10, type ALL: wirelen solved = 10169, spread = 25720, legal = 44681; time = 0.32s Info: at iteration #11, type ALL: wirelen solved = 10572, spread = 26140, legal = 40978; time = 0.33s Info: at iteration #12, type ALL: wirelen solved = 11019, spread = 26172, legal = 45327; time = 0.45s Info: at iteration #13, type ALL: wirelen solved = 11243, spread = 25782, legal = 42859; time = 0.34s Info: HeAP Placer Time: 5.44s Info: of which solving equations: 1.32s Info: of which spreading cells: 0.20s Info: of which strict legalisation: 3.20s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 790, wirelen = 38573 Info: at iteration #5: temp = 0.000000, timing cost = 586, wirelen = 32008 Info: at iteration #10: temp = 0.000000, timing cost = 532, wirelen = 30292 Info: at iteration #15: temp = 0.000000, timing cost = 529, wirelen = 29339 Info: at iteration #20: temp = 0.000000, timing cost = 539, wirelen = 28590 Info: at iteration #25: temp = 0.000000, timing cost = 534, wirelen = 28403 Info: at iteration #30: temp = 0.000000, timing cost = 531, wirelen = 28356 Info: at iteration #32: temp = 0.000000, timing cost = 531, wirelen = 28351 Info: SA placement time 8.75s Info: Max frequency for clock 'clk_sys': 32.81 MHz (PASS at 30.72 MHz) Info: Max frequency for clock 'clk_48m': 51.22 MHz (PASS at 48.00 MHz) Info: Max delay <async> -> posedge clk_sys: 7.02 ns Info: Max delay posedge clk_48m -> <async> : 4.95 ns Info: Max delay posedge clk_48m -> posedge clk_sys: 5.80 ns Info: Max delay posedge clk_sys -> <async> : 12.72 ns Info: Max delay posedge clk_sys -> posedge clk_48m: 14.54 ns Info: Slack histogram: Info: legend: * represents 55 endpoint(s) Info: + represents [1,55) endpoint(s) Info: [ 1310, 5254) |*+ Info: [ 5254, 9198) |*****+ Info: [ 9198, 13142) |*********+ Info: [ 13142, 17086) |*******************************+ Info: [ 17086, 21030) |***********************+ Info: [ 21030, 24974) |*******************************+ Info: [ 24974, 28918) |************************************************************ Info: [ 28918, 32862) |**+ Info: [ 32862, 36806) | Info: [ 36806, 40750) | Info: [ 40750, 44694) | Info: [ 44694, 48638) | Info: [ 48638, 52582) | Info: [ 52582, 56526) | Info: [ 56526, 60470) | Info: [ 60470, 64414) | Info: [ 64414, 68358) | Info: [ 68358, 72302) |+ Info: [ 72302, 76246) |+ Info: [ 76246, 80190) |+ Info: Checksum: 0x373cc6b7 Info: Routing.. Info: Setting up routing queue. Info: Routing 15492 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 41 958 | 41 958 | 14537| 0.10 0.10| Info: 2000 | 63 1936 | 22 978 | 13562| 0.08 0.18| Info: 3000 | 130 2869 | 67 933 | 12642| 0.20 0.37| Info: 4000 | 243 3756 | 113 887 | 11794| 0.23 0.60| Info: 5000 | 365 4634 | 122 878 | 10931| 0.22 0.82| Info: 6000 | 539 5460 | 174 826 | 10183| 0.25 1.08| Info: 7000 | 733 6266 | 194 806 | 9456| 0.32 1.39| Info: 8000 | 957 7042 | 224 776 | 8753| 0.32 1.71| Info: 9000 | 1162 7837 | 205 795 | 8013| 0.26 1.97| Info: 10000 | 1502 8497 | 340 660 | 7527| 0.51 2.48| Info: 11000 | 1990 9009 | 488 512 | 7303| 0.70 3.19| Info: 12000 | 2504 9495 | 514 486 | 7152| 0.79 3.98| Info: 13000 | 2989 10010 | 485 515 | 6901| 0.76 4.74| Info: 14000 | 3491 10508 | 502 498 | 6739| 0.75 5.49| Info: 15000 | 4048 10951 | 557 443 | 6588| 0.61 6.10| Info: 16000 | 4484 11515 | 436 564 | 6265| 0.51 6.61| Info: 17000 | 5019 11980 | 535 465 | 6102| 0.63 7.24| Info: 18000 | 5460 12539 | 441 559 | 5769| 0.48 7.72| Info: 19000 | 5757 13242 | 297 703 | 5217| 0.47 8.20| Info: 20000 | 6170 13829 | 413 587 | 4842| 0.41 8.61| Info: 21000 | 6613 14386 | 443 557 | 4452| 1.63 10.24| Info: 22000 | 7149 14850 | 536 464 | 4314| 1.23 11.47| Info: 23000 | 7735 15264 | 586 414 | 4258| 0.83 12.30| Info: 24000 | 8300 15699 | 565 435 | 4195| 0.77 13.07| Info: 25000 | 8867 16132 | 567 433 | 4128| 0.92 14.00| Info: 26000 | 9471 16528 | 604 396 | 4064| 0.84 14.84| Info: 27000 | 10046 16953 | 575 425 | 3955| 0.90 15.74| Info: 28000 | 10617 17382 | 571 429 | 3858| 0.64 16.37| Info: 29000 | 11110 17889 | 493 507 | 3734| 0.76 17.13| Info: 30000 | 11706 18293 | 596 404 | 3682| 0.61 17.74| Info: 31000 | 12274 18725 | 568 432 | 3602| 0.66 18.40| Info: 32000 | 12782 19217 | 508 492 | 3451| 0.58 18.98| Info: 33000 | 13354 19645 | 572 428 | 3381| 0.77 19.74| Info: 34000 | 13880 20119 | 526 474 | 3260| 0.55 20.29| Info: 35000 | 14391 20608 | 511 489 | 3180| 0.64 20.93| Info: 36000 | 14965 21034 | 574 426 | 3102| 0.55 21.49| Info: 37000 | 15533 21466 | 568 432 | 3015| 0.54 22.03| Info: 38000 | 16126 21873 | 593 407 | 2915| 0.79 22.82| Info: 39000 | 16701 22298 | 575 425 | 2853| 0.70 23.52| Info: 40000 | 17260 22739 | 559 441 | 2781| 0.71 24.23| Info: 41000 | 17803 23196 | 543 457 | 2688| 0.77 25.00| Info: 42000 | 18205 23794 | 402 598 | 2277| 0.47 25.48| Info: 43000 | 18579 24420 | 374 626 | 1826| 0.48 25.96| Info: 44000 | 19020 24979 | 441 559 | 1438| 0.87 26.83| Info: 45000 | 19564 25435 | 544 456 | 1335| 1.06 27.89| Info: 46000 | 19932 26067 | 368 632 | 916| 1.40 29.29| Info: 47000 | 20283 26716 | 351 649 | 507| 2.00 31.29| Info: 48000 | 20767 27232 | 484 516 | 283| 1.47 32.76| Info: 48415 | 20868 27547 | 101 315 | 0| 0.25 33.01| Info: Routing complete. Info: Router1 time 33.01s Info: Checksum: 0x82d39c99 Info: Critical path report for clock 'clk_sys' (posedge -> posedge): Info: curr total Info: 1.4 1.4 Source soc_I.cpu_I.latched_is_lb_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_5_LC.O Info: 3.6 5.0 Net soc_I.cpu_I.reg_out[1] budget 1.920000 ns (7,9) -> (3,11) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_O_LC.I1 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:160.52-160.59 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: 1.2 6.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_O_LC.O Info: 1.8 8.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2[0] budget 1.947000 ns (3,11) -> (4,12) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_LC.I1 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 9.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_LC.O Info: 3.0 12.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O[0] budget 1.596000 ns (4,12) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0$CARRY.I1 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:29.22-29.23 Info: 0.7 12.9 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0$CARRY.COUT Info: 0.0 12.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[1] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_22_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 13.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_22_LC.COUT Info: 0.0 13.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[2] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_11_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 13.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_11_LC.COUT Info: 0.0 13.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[3] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_9_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 13.7 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_9_LC.COUT Info: 0.0 13.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[4] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_8_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_8_LC.COUT Info: 0.0 14.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[5] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_7_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_7_LC.COUT Info: 0.0 14.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[6] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_6_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_6_LC.COUT Info: 0.0 14.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[7] budget 0.000000 ns (4,17) -> (4,17) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_5_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 14.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_5_LC.COUT Info: 0.6 15.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[8] budget 0.560000 ns (4,17) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_4_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.7 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_4_LC.COUT Info: 0.0 15.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[9] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_3_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 15.9 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_3_LC.COUT Info: 0.0 15.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[10] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_2_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_2_LC.COUT Info: 0.0 16.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[11] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_1_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_1_LC.COUT Info: 0.0 16.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[12] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 16.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_LC.COUT Info: 0.0 16.8 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[13] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_29_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_29_LC.COUT Info: 0.0 17.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[14] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_28_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_28_LC.COUT Info: 0.0 17.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[15] budget 0.000000 ns (4,18) -> (4,18) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_27_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 17.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_27_LC.COUT Info: 0.6 18.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[16] budget 0.560000 ns (4,18) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_26_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_26_LC.COUT Info: 0.0 18.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[17] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_25_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.7 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_25_LC.COUT Info: 0.0 18.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[18] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_24_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 19.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_24_LC.COUT Info: 0.0 19.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[19] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_23_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 19.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_23_LC.COUT Info: 0.0 19.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[20] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_21_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 19.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_21_LC.COUT Info: 0.0 19.6 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[21] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_20_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 19.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_20_LC.COUT Info: 0.0 19.8 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[22] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_19_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 20.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_19_LC.COUT Info: 0.0 20.1 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[23] budget 0.000000 ns (4,19) -> (4,19) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_18_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 20.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_18_LC.COUT Info: 0.6 20.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[24] budget 0.560000 ns (4,19) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_17_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 21.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_17_LC.COUT Info: 0.0 21.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[25] budget 0.000000 ns (4,20) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_16_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 21.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_16_LC.COUT Info: 0.0 21.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[26] budget 0.000000 ns (4,20) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_15_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 21.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_15_LC.COUT Info: 0.0 21.8 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[27] budget 0.000000 ns (4,20) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_14_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 22.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_14_LC.COUT Info: 0.0 22.1 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[28] budget 0.000000 ns (4,20) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_13_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 22.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_13_LC.COUT Info: 0.0 22.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[29] budget 0.000000 ns (4,20) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_12_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 22.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_12_LC.COUT Info: 0.7 23.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[30] budget 0.660000 ns (4,20) -> (4,20) Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_10_LC.I3 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.9 24.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_10_LC.O Info: 2.4 26.6 Net soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_29_D_SB_LUT4_O_I0[30] budget 2.501000 ns (4,20) -> (5,23) Info: Sink soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_LC.I0 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49 Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:33.26-33.27 Info: 1.3 27.8 Source soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_LC.O Info: 2.4 30.2 Net soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1[0] budget 2.736000 ns (5,23) -> (4,20) Info: Sink soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_LC.I1 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 31.4 Setup soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_LC.I1 Info: 15.9 ns logic, 15.5 ns routing Info: Critical path report for clock 'clk_48m' (posedge -> posedge): Info: curr total Info: 1.4 1.4 Source soc_I.usb_I.tx_ll_I.ll_ack_SB_DFF_Q_D_SB_LUT4_O_LC.O Info: 4.2 5.6 Net soc_I.usb_I.txll_ack budget 2.514000 ns (20,2) -> (20,16) Info: Sink soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_LC.I2 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:72.7-72.15 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: 1.2 6.8 Source soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_LC.O Info: 1.8 8.6 Net soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O[0] budget 1.615000 ns (20,16) -> (21,17) Info: Sink soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_LC.I2 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 1.2 9.8 Source soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_LC.O Info: 1.8 11.5 Net soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O budget 1.694000 ns (21,17) -> (22,16) Info: Sink soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_O_2_LC.I3 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.9 12.4 Source soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_O_2_LC.O Info: 1.8 14.2 Net soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O[0] budget 1.511000 ns (22,16) -> (22,16) Info: Sink soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_I3_LC.I3 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:231.13-244.3 Info: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154.17-154.58 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:33.26-33.27 Info: 0.9 15.1 Source soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_I3_LC.O Info: 1.8 16.8 Net soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_I3[1] budget 1.511000 ns (22,16) -> (21,16) Info: Sink $nextpnr_ICESTORM_LC_212.I1 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:231.13-244.3 Info: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154.17-154.58 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:29.22-29.23 Info: 0.7 17.5 Source $nextpnr_ICESTORM_LC_212.COUT Info: 0.0 17.5 Net $nextpnr_ICESTORM_LC_212$O budget 0.000000 ns (21,16) -> (21,16) Info: Sink soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_O_1_LC.CIN Info: 0.3 17.8 Source soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_O_1_LC.COUT Info: 0.0 17.8 Net soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_I3[2] budget 0.000000 ns (21,16) -> (21,16) Info: Sink soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_O_LC.CIN Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:231.13-244.3 Info: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154.17-154.58 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.3 18.0 Source soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_O_LC.COUT Info: 0.7 18.7 Net soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_I3[3] budget 0.660000 ns (21,16) -> (21,16) Info: Sink soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_LC.I3 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:231.13-244.3 Info: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154.17-154.58 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 Info: 0.8 19.5 Setup soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_LC.I3 Info: 7.6 ns logic, 11.9 ns routing Info: Critical path report for cross-domain path '<async>' -> 'posedge clk_sys': Info: curr total Info: 0.0 0.0 Source spi_mux_I.iob_I[2].D_IN_0 Info: 8.2 8.2 Net flash_miso_i budget 31.052000 ns (23,0) -> (0,0) Info: Sink soc_I.spi_I.spi_I.MI Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:374.4-400.3 Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:32.14-32.24 Info: 1.5 9.7 Setup soc_I.spi_I.spi_I.MI Info: 1.5 ns logic, 8.2 ns routing Info: Critical path report for cross-domain path 'posedge clk_48m' -> '<async>': Info: curr total Info: 1.4 1.4 Source soc_I.usb_I.pad_pu_SB_DFFSR_Q_DFFLC.O Info: 3.6 5.0 Net usb_pu$SB_IO_OUT budget 81.943001 ns (15,7) -> (17,0) Info: Sink usb_pu$sb_io.D_OUT_0 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:39.14-39.20 Info: 1.4 ns logic, 3.6 ns routing Info: Critical path report for cross-domain path 'posedge clk_48m' -> 'posedge clk_sys': Info: curr total Info: 1.4 1.4 Source soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_15_LC.O Info: 3.1 4.4 Net soc_I.wb_48m_xclk_I.m_rdata_i[0] budget 29.927999 ns (15,13) -> (15,8) Info: Sink soc_I.wb_48m_xclk_I.s_rdata_SB_DFFSR_Q_15_DFFLC.I0 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2misc//rtl/xclk_wb.v:53.15-53.24 Info: /build/gateware/common/rtl/soc_base.v:400.4-416.3 Info: 1.2 5.7 Setup soc_I.wb_48m_xclk_I.s_rdata_SB_DFFSR_Q_15_DFFLC.I0 Info: 2.6 ns logic, 3.1 ns routing Info: Critical path report for cross-domain path 'posedge clk_sys' -> '<async>': Info: curr total Info: 1.5 1.5 Source soc_I.spi_I.spi_I.SCKO Info: 8.3 9.8 Net flash_clk_o budget 40.313999 ns (0,0) -> (22,1) Info: Sink spi_mux_I.sio_clk_o_SB_LUT4_O_LC.I2 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:374.4-400.3 Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:37.14-37.23 Info: 1.2 11.0 Source spi_mux_I.sio_clk_o_SB_LUT4_O_LC.O Info: 4.4 15.4 Net spi_mux_I.sio_clk_o budget 38.433998 ns (22,1) -> (24,0) Info: Sink spi_mux_I.iob_I[1].D_OUT_0 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:374.4-400.3 Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:89.7-89.16 Info: 2.7 ns logic, 12.7 ns routing Info: Critical path report for cross-domain path 'posedge clk_sys' -> 'posedge clk_48m': Info: curr total Info: 1.4 1.4 Source soc_I.cpu_I.mem_la_addr_SB_LUT4_O_8_LC.O Info: 3.6 5.0 Net wb_addr[11] budget 5.238000 ns (10,16) -> (15,14) Info: Sink soc_I.wb_48m_xclk_I.m_cyc_i_SB_LUT4_I3_LC.I1 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:91.18-91.25 Info: 1.2 6.2 Source soc_I.wb_48m_xclk_I.m_cyc_i_SB_LUT4_I3_LC.O Info: 3.0 9.2 Net soc_I.usb_I.csr_bus_req_SB_DFF_Q_D budget 3.731000 ns (15,14) -> (15,10) Info: Sink soc_I.usb_I.csr_bus_clear_SB_LUT4_O_LC.I3 Info: Defined in: Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.9 10.0 Source soc_I.usb_I.csr_bus_clear_SB_LUT4_O_LC.O Info: 3.0 13.0 Net soc_I.usb_I.csr_bus_clear budget 4.123000 ns (15,10) -> (16,13) Info: Sink soc_I.usb_I.evt_rd_ack_SB_DFFSR_Q_D_SB_LUT4_O_LC.I0 Info: Defined in: Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3 Info: /build/gateware/cores/no2usb//rtl/usb.v:151.7-151.20 Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3 Info: 1.2 14.2 Setup soc_I.usb_I.evt_rd_ack_SB_DFFSR_Q_D_SB_LUT4_O_LC.I0 Info: 4.7 ns logic, 9.5 ns routing Info: Max frequency for clock 'clk_sys': 31.82 MHz (PASS at 30.72 MHz) Info: Max frequency for clock 'clk_48m': 51.20 MHz (PASS at 48.00 MHz) Info: Max delay <async> -> posedge clk_sys: 9.74 ns Info: Max delay posedge clk_48m -> <async> : 4.99 ns Info: Max delay posedge clk_48m -> posedge clk_sys: 5.68 ns Info: Max delay posedge clk_sys -> <async> : 15.43 ns Info: Max delay posedge clk_sys -> posedge clk_48m: 14.23 ns Info: Slack histogram: Info: legend: * represents 54 endpoint(s) Info: + represents [1,54) endpoint(s) Info: [ 1123, 5076) |*+ Info: [ 5076, 9029) |****+ Info: [ 9029, 12982) |**********+ Info: [ 12982, 16935) |****************************+ Info: [ 16935, 20888) |****************+ Info: [ 20888, 24841) |******************************************+ Info: [ 24841, 28794) |************************************************************ Info: [ 28794, 32747) |**+ Info: [ 32747, 36700) | Info: [ 36700, 40653) | Info: [ 40653, 44606) | Info: [ 44606, 48559) | Info: [ 48559, 52512) | Info: [ 52512, 56465) | Info: [ 56465, 60418) | Info: [ 60418, 64371) | Info: [ 64371, 68324) |+ Info: [ 68324, 72277) |+ Info: [ 72277, 76230) |+ Info: [ 76230, 80183) |+ 4 warnings, 0 errors icepack -s /build/gateware/icE1usb/build-tmp/icE1usb.asc /build/gateware/icE1usb/build-tmp/icE1usb.bin make: Leaving directory '/build/gateware/icE1usb' Finished: SUCCESS