Skipping 2,185 KB..
Full Log New connections: { \soc_I.e1_I.bus_rdata_tx[0] [14:13] \soc_I.e1_I.bus_rdata_tx[0] [7] } = 3'000
Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11896:
Old ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11896_Y [2:0]
New ports: A={ $flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [1] $flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [1] }, B=2'10, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11896_Y [2:1]
New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11896_Y [0] = 1'0
Optimizing cells in module \top.
Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11899:
Old ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11896_Y, B=4'1000, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11899_Y
New ports: A={ 1'0 $flatten\soc_I.\usb_I.\trans_I.$procmux$11896_Y [2:1] }, B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11899_Y [3:1]
New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11899_Y [0] = 1'0
Optimizing cells in module \top.
Performed a total of 41 changes.
75.29.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
75.29.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23173 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:10], Q = \soc_I.usb_I.ep_status_I.din_1 [11:10], rval = 2'00).
Adding SRST signal on $auto$opt_dff.cc:702:run$24404 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4563_Y [2:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.pg_hi [2:1], rval = 2'00).
Adding SRST signal on $auto$opt_dff.cc:702:run$24403 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4564_Y [2:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\stx_I.tx_I.pg_lo [2:1], rval = 2'00).
75.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
75.29.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~37 debug messages>
75.29.9. Rerunning OPT passes. (Maybe there is more to do..)
75.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12403.
dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12418.
Removed 2 multiplexer ports.
<suppressed ~186 debug messages>
75.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
75.29.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.
75.29.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$opt_dff.cc:764:run$24851 ($dffe) from module top (D = $auto$wreduce.cc:454:run$24917 [2:0], Q = \i2c_I.core_I.bit_cnt [2:0], rval = 3'000).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24587 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$24587 ($dffe) from module top.
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24358 ($dffe) from module top.
Setting constant 1-bit at position 9 on $auto$opt_dff.cc:764:run$24306 ($adffe) from module top.
75.29.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 20 unused wires.
<suppressed ~2 debug messages>
75.29.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.29.16. Rerunning OPT passes. (Maybe there is more to do..)
75.29.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~186 debug messages>
75.29.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
75.29.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
75.29.20. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24369 ($sdff) from module top.
Adding SRST signal on $auto$opt_dff.cc:702:run$24369 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5362[0].\srx_I.bd_rx_out_I.data[1] [8:7], Q = \soc_I.e1_I.wb_rdata [14:13], rval = 2'00).
Removing never-active SRST on $auto$opt_dff.cc:702:run$24364 ($sdffce) from module top.
Removing never-active SRST on $auto$opt_dff.cc:702:run$24362 ($sdffce) from module top.
Removing never-active SRST on $auto$opt_dff.cc:702:run$24360 ($sdffce) from module top.
75.29.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
75.29.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>
75.29.23. Rerunning OPT passes. (Maybe there is more to do..)
75.29.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~186 debug messages>
75.29.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
75.29.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.
75.29.27. Executing OPT_DFF pass (perform DFF optimizations).
75.29.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
<suppressed ~1 debug messages>
75.29.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.29.30. Rerunning OPT passes. (Maybe there is more to do..)
75.29.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~186 debug messages>
75.29.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
75.29.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
75.29.34. Executing OPT_DFF pass (perform DFF optimizations).
75.29.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
75.29.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.29.37. Finished OPT passes. (There is nothing left to do.)
75.30. Executing ICE40_WRAPCARRY pass (wrap carries).
75.31. Executing TECHMAP pass (map to technology primitives).
75.31.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
75.31.2. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.
75.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $sdffce.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $adffe.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $adff.
Using extmapper simplemap for cells of type $mux.
Using template $paramod$constmap:37b3cc4e06391b7a7ef418215dc52e2abb59f048$paramod$71443bc33ec938a4dea8c4b4bbb3a548919fd2a5\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod$constmap:f131a727070ba63172385ab8bc15babdfc05a11a$paramod$4d8c31a57f918e2cd1d0bc24d8284efd6d83f4a8\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=1\Y_WIDTH=7 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=1\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu.
Using template $paramod$constmap:98a2574d6790db88f29c592e698ccfc2583099ee$paramod$da4b7a069bab2d2cb126ab511d2c5f5d67aa4129\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=14\Y_WIDTH=14 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using template $paramod$constmap:2a578b20caa92a5095129d48a2f94bbad08a990f$paramod$5c10e52cdc159999f3945c97d8a1bfa2ca0de2dc\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=12 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=1\Y_WIDTH=13 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_xor.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=20\Y_WIDTH=20 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=16\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=5 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=6 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=8 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=6 for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_xnor.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=1\Y_WIDTH=9 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=3 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
Using template $paramod$constmap:66d421c313e4e958be776b99540ac2de3b59fdbc$paramod$9b74a473ccd678a23e1df4cc12019cbbece20051\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=31\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=30\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=16\Y_WIDTH=16 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=1\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=5 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=5 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=26\Y_WIDTH=26 for cells of type $alu.
Using template $paramod$constmap:684fca2758d270a6aba8ac07bc0dd26758fbc9a0$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx for cells of type $shiftx.
Analyzing pattern of constant bits for this cell:
Constant input on bit 0 of port A: 1'0
Constant input on bit 1 of port A: 1'0
Constant input on bit 2 of port A: 1'0
Constant input on bit 3 of port A: 1'0
Constant input on bit 4 of port A: 1'1
Constant input on bit 5 of port A: 1'1
Constant input on bit 6 of port A: 1'1
Constant input on bit 7 of port A: 1'1
Constant input on bit 8 of port A: 1'0
Constant input on bit 9 of port A: 1'0
Constant input on bit 10 of port A: 1'0
Constant input on bit 11 of port A: 1'0
Constant input on bit 12 of port A: 1'1
Constant input on bit 13 of port A: 1'1
Constant input on bit 14 of port A: 1'1
Constant input on bit 15 of port A: 1'1
Creating constmapped module `$paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx'.
75.31.141. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 2/2 on $mux $procmux$36239.
dead port 2/2 on $mux $procmux$36233.
dead port 2/2 on $mux $procmux$36227.
dead port 2/2 on $mux $procmux$36221.
Removed 4 multiplexer ports.
<suppressed ~4033 debug messages>
75.31.142. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx.
<suppressed ~3 debug messages>
Removed 0 unused cells and 11 unused wires.
Using template $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=7 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=13\Y_WIDTH=13 for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu.
No more expansions possible.
<suppressed ~1299 debug messages>
75.32. Executing OPT pass (performing simple optimizations).
75.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3446 debug messages>
75.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3954 debug messages>
Removed a total of 1318 cells.
75.32.3. Executing OPT_DFF pass (perform DFF optimizations).
75.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 979 unused cells and 4656 unused wires.
<suppressed ~991 debug messages>
75.32.5. Finished fast OPT passes.
75.33. Executing ICE40_OPT pass (performing simple optimizations).
75.33.1. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24972.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24972.BB [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24981.slice[0].carry: CO=\blinker_I.tick_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24987.slice[0].carry: CO=\gps_uart_I.uart_div [1]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24987.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$24987.C [11]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24990.slice[0].carry: CO=\gps_uart_I.uart_rx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24993.slice[0].carry: CO=\gps_uart_I.uart_rx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24999.slice[0].carry: CO=\gps_uart_I.uart_rx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25005.slice[0].carry: CO=\gps_uart_I.uart_rx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25008.slice[0].carry: CO=\gps_uart_I.uart_tx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25011.slice[0].carry: CO=\gps_uart_I.uart_tx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25014.slice[0].carry: CO=\gps_uart_I.uart_tx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25020.slice[0].carry: CO=\gps_uart_I.uart_tx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25023.slice[0].carry: CO=\i2c_I.core_I.cyc_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25026.slice[0].carry: CO=\i2c_I.core_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25035.slice[0].carry: CO=\sys_mgr_I.rst_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25083.slice[0].carry: CO=\soc_I.cpu_I.reg_pc [2]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25086.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25086.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25101.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [2]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25104.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25107.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25107.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25110.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25110.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25113.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25113.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25116.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25116.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25131.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25131.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25155.slice[0].carry: CO=\soc_I.e1_buf_I.buf_tx_ts [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25158.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25158.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25161.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25161.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25167.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m0_addr_i [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25170.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m1_addr_i [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25173.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.len [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25176.slice[0].carry: CO=\soc_I.uart_I.uart_div [1]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25176.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$25176.C [11]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25179.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25182.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25188.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25194.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25197.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25200.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25203.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25209.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25221.slice[0].carry: CO=\soc_I.usb_I.rx_pkt_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25221.slice[3].carry: CO=$auto$alumacc.cc:485:replace_alu$25221.C [3]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25224.slice[0].carry: CO=\soc_I.usb_I.trans_I.mc_pc [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25239.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25239.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25239.slice[2].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25242.slice[0].carry: CO=\soc_I.usb_I.tx_ll_I.bs_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25245.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25245.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25248.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25248.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25251.slice[0].carry: CO=\spi_mux_I.tick_cnt [0]
75.33.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~42 debug messages>
75.33.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
75.33.4. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30655 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12179.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30654 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12179.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30653 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12179.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30651 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12196.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [3], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30650 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12196.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30649 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12196.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35249 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [31], Q = \misc_I.wb_rdata [31], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35248 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [30], Q = \misc_I.wb_rdata [30], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35247 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [29], Q = \misc_I.wb_rdata [29], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35246 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [28], Q = \misc_I.wb_rdata [28], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35245 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [27], Q = \misc_I.wb_rdata [27], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35244 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [26], Q = \misc_I.wb_rdata [26], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35243 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [25], Q = \misc_I.wb_rdata [25], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35242 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [24], Q = \misc_I.wb_rdata [24], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35241 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [23], Q = \misc_I.wb_rdata [23], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35240 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [22], Q = \misc_I.wb_rdata [22], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35239 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [21], Q = \misc_I.wb_rdata [21], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35238 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [20], Q = \misc_I.wb_rdata [20], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35233 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [15], Q = \misc_I.wb_rdata [15], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35232 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [14], Q = \misc_I.wb_rdata [14], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35231 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [13], Q = \misc_I.wb_rdata [13], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35230 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [12], Q = \misc_I.wb_rdata [12], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35225 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [7], Q = \misc_I.wb_rdata [7], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35224 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [6], Q = \misc_I.wb_rdata [6], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35223 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [5], Q = \misc_I.wb_rdata [5], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35222 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11708.Y_B [4], Q = \misc_I.wb_rdata [4], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$31251 ($_SDFF_PP0_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12222.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.samp_cnt [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34819 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [31], Q = \soc_I.cpu_I.decoded_imm [31], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34818 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [30], Q = \soc_I.cpu_I.decoded_imm [30], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34817 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [29], Q = \soc_I.cpu_I.decoded_imm [29], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34816 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [28], Q = \soc_I.cpu_I.decoded_imm [28], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34815 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [27], Q = \soc_I.cpu_I.decoded_imm [27], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34814 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [26], Q = \soc_I.cpu_I.decoded_imm [26], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34813 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [25], Q = \soc_I.cpu_I.decoded_imm [25], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34812 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [24], Q = \soc_I.cpu_I.decoded_imm [24], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34811 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [23], Q = \soc_I.cpu_I.decoded_imm [23], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34810 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [22], Q = \soc_I.cpu_I.decoded_imm [22], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34809 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [21], Q = \soc_I.cpu_I.decoded_imm [21], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34808 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [20], Q = \soc_I.cpu_I.decoded_imm [20], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34807 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [19], Q = \soc_I.cpu_I.decoded_imm [19], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34806 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [18], Q = \soc_I.cpu_I.decoded_imm [18], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34805 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [17], Q = \soc_I.cpu_I.decoded_imm [17], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34804 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [16], Q = \soc_I.cpu_I.decoded_imm [16], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34803 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [15], Q = \soc_I.cpu_I.decoded_imm [15], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34802 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [14], Q = \soc_I.cpu_I.decoded_imm [14], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34801 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [13], Q = \soc_I.cpu_I.decoded_imm [13], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34800 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [12], Q = \soc_I.cpu_I.decoded_imm [12], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34799 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [11], Q = \soc_I.cpu_I.decoded_imm [11], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34798 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [10], Q = \soc_I.cpu_I.decoded_imm [10], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34797 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [9], Q = \soc_I.cpu_I.decoded_imm [9], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34796 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [8], Q = \soc_I.cpu_I.decoded_imm [8], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34795 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [7], Q = \soc_I.cpu_I.decoded_imm [7], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34794 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [6], Q = \soc_I.cpu_I.decoded_imm [6], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34793 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [5], Q = \soc_I.cpu_I.decoded_imm [5], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34792 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [4], Q = \soc_I.cpu_I.decoded_imm [4], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34791 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [3], Q = \soc_I.cpu_I.decoded_imm [3], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34790 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [2], Q = \soc_I.cpu_I.decoded_imm [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34789 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14361.Y_B [1], Q = \soc_I.cpu_I.decoded_imm [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30645 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12211.B_AND_S [2], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30644 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12211.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30643 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12211.Y_B [0], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [0], rval = 1'0).
75.33.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 62 unused cells and 32 unused wires.
<suppressed ~63 debug messages>
75.33.6. Rerunning OPT passes. (Removed registers in this run.)
75.33.7. Running ICE40 specific optimizations.
75.33.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.33.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~132 debug messages>
Removed a total of 44 cells.
75.33.10. Executing OPT_DFF pass (perform DFF optimizations).
75.33.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 44 unused wires.
<suppressed ~1 debug messages>
75.33.12. Rerunning OPT passes. (Removed registers in this run.)
75.33.13. Running ICE40 specific optimizations.
75.33.14. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.33.15. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
75.33.16. Executing OPT_DFF pass (perform DFF optimizations).
75.33.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
75.33.18. Finished OPT passes. (There is nothing left to do.)
75.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
75.35. Executing TECHMAP pass (map to technology primitives).
75.35.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.
75.35.2. Continuing TECHMAP pass.
Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_.
Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_.
Using template \$_DFF_P_ for cells of type $_DFF_P_.
Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_.
Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_.
Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_.
Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
No more expansions possible.
<suppressed ~2236 debug messages>
75.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping top.$auto$alumacc.cc:485:replace_alu$24981.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$24987.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$24987.slice[11].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$24990.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$24993.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$24999.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25005.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25008.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25011.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25014.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25020.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25023.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25026.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25035.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25083.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25086.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25101.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25104.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25107.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25110.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25113.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25116.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25131.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25155.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25158.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25161.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25167.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25170.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25173.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25176.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25176.slice[11].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25179.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25182.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25188.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25194.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25197.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25200.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25203.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25209.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25221.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25221.slice[3].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25224.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25239.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25239.slice[2].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25242.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25245.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25248.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25251.slice[0].carry ($lut).
75.38. Executing ICE40_OPT pass (performing simple optimizations).
75.38.1. Running ICE40 specific optimizations.
75.38.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~1263 debug messages>
75.38.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~1359 debug messages>
Removed a total of 453 cells.
75.38.4. Executing OPT_DFF pass (perform DFF optimizations).
75.38.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 12113 unused wires.
<suppressed ~1 debug messages>
75.38.6. Rerunning OPT passes. (Removed registers in this run.)
75.38.7. Running ICE40 specific optimizations.
75.38.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.38.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
75.38.10. Executing OPT_DFF pass (perform DFF optimizations).
75.38.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
75.38.12. Finished OPT passes. (There is nothing left to do.)
75.39. Executing TECHMAP pass (map to technology primitives).
75.39.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.
75.39.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
75.40. Executing ABC pass (technology mapping using ABC).
75.40.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 6569 gates and 9036 wires to a netlist network with 2465 inputs and 1841 outputs.
75.40.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC:
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
ABC: + strash
ABC: + ifraig
ABC: + scorr
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2
ABC: + dretime
ABC: + strash
ABC: + dch -f
ABC: + if
ABC: + mfs2
ABC: + lutpack -S 1
ABC: + dress
ABC: Total number of equiv classes = 2250.
ABC: Participating nodes from both networks = 4762.
ABC: Participating nodes from the first network = 2268. ( 79.38 % of nodes)
ABC: Participating nodes from the second network = 2494. ( 87.29 % of nodes)
ABC: Node pairs (any polarity) = 2268. ( 79.38 % of names can be moved)
ABC: Node pairs (same polarity) = 1998. ( 69.93 % of names can be moved)
ABC: Total runtime = 0.08 sec
ABC: + write_blif <abc-temp-dir>/output.blif
75.40.1.2. Re-integrating ABC results.
ABC RESULTS: $lut cells: 2856
ABC RESULTS: internal signals: 4730
ABC RESULTS: input signals: 2465
ABC RESULTS: output signals: 1841
Removing temp directory.
75.41. Executing ICE40_WRAPCARRY pass (wrap carries).
75.42. Executing TECHMAP pass (map to technology primitives).
75.42.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.
75.42.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~22 debug messages>
Removed 140 unused cells and 5969 unused wires.
75.43. Executing OPT_LUT pass (optimize LUTs).
Discovering LUTs.
Number of LUTs: 3533
1-LUT 149
2-LUT 978
3-LUT 1253
4-LUT 1153
Eliminating LUTs.
Number of LUTs: 3529
1-LUT 149
2-LUT 978
3-LUT 1249
4-LUT 1153
Combining LUTs.
Number of LUTs: 3268
1-LUT 148
2-LUT 653
3-LUT 1128
4-LUT 1339
Eliminated 4 LUTs.
Combined 261 LUTs.
<suppressed ~18883 debug messages>
75.44. Executing TECHMAP pass (map to technology primitives).
75.44.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
75.44.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011110011111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101110111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100111110100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011110011001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111110001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1101001100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011101111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111001111000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11101111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101111111110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001001100111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101110011001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111010001000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01011100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001101011100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011101100110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100010011110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000110011001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110101100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000000101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010101010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10110010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111011111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011011100110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000000011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011101110110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100011101110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111001111110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111110110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110101110111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110010100011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010101111101010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001010111111100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000100011110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111110011111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011101100001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111001011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001011001101001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111011101110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000101010100010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010001111001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001110111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100010000001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000011101110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010000011001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100111000001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011100100001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011101111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00011000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11100111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000110000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111110000001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101110001010011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0010111111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001010001000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110110000110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000011111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01000010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000100000001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0010001010001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0010100000101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101010100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011101000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10111100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000101000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010001000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010101011000011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000101110111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0010000100010010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010000000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100010100110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100001101100110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101010111000011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111011101000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001110010011100 for cells of type $lut.
No more expansions possible.
<suppressed ~6274 debug messages>
Removed 0 unused cells and 6958 unused wires.
75.45. Executing AUTONAME pass.
Renamed 174767 objects in module top (112 iterations).
<suppressed ~8268 debug messages>
75.46. Executing HIERARCHY pass (managing design hierarchy).
75.46.1. Analyzing design hierarchy..
Top module: \top
75.46.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
75.47. Printing statistics.
=== top ===
Number of wires: 3777
Number of wire bits: 18573
Number of public wires: 3777
Number of public wire bits: 18573
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 6302
SB_CARRY 719
SB_DFF 317
SB_DFFE 575
SB_DFFER 431
SB_DFFES 44
SB_DFFESR 220
SB_DFFESS 45
SB_DFFR 131
SB_DFFS 49
SB_DFFSR 374
SB_DFFSS 27
SB_GB 2
SB_GB_IO 1
SB_IO 25
SB_LEDDA_IP 1
SB_LUT4 3307
SB_MAC16 6
SB_PLL40_CORE 1
SB_RAM40_4K 16
SB_RAM40_4KNR 4
SB_RGBA_DRV 1
SB_SPI 1
SB_SPRAM256KA 4
SB_WARMBOOT 1
75.48. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.
75.49. Executing JSON backend.
Warnings: 9 unique messages, 17 total
End of script. Logfile hash: e7c68d8612, CPU: user 21.53s system 0.15s, MEM: 289.16 MB peak
Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os)
Time spent: 22% 38x opt_expr (5 sec), 19% 31x opt_clean (4 sec), ...
nextpnr-ice40 --pre-pack data/clocks.py --pre-pack data/opt.py --seed 15 --no-promote-globals --timing-allow-fail \
--up5k --package sg48 \
-l /build/gateware/icE1usb/build-tmp/icE1usb.pnr.rpt \
--json /build/gateware/icE1usb/build-tmp/icE1usb.json \
--pcf /build/gateware/icE1usb/data/top-ice1usb.pcf \
--asc /build/gateware/icE1usb/build-tmp/icE1usb.asc
Info: constrained 'e1A_rx_hi_p' to bel 'X8/Y31/io0'
Warning: unmatched constraint 'e1A_rx_hi_n' (on line 3)
Info: constrained 'e1A_rx_lo_p' to bel 'X16/Y31/io0'
Warning: unmatched constraint 'e1A_rx_lo_n' (on line 5)
Info: constrained 'e1A_tx_hi' to bel 'X9/Y31/io0'
Info: constrained 'e1A_tx_lo' to bel 'X9/Y31/io1'
Info: constrained 'e1B_rx_hi_p' to bel 'X19/Y31/io0'
Warning: unmatched constraint 'e1B_rx_hi_n' (on line 10)
Info: constrained 'e1B_rx_lo_p' to bel 'X18/Y31/io0'
Warning: unmatched constraint 'e1B_rx_lo_n' (on line 12)
Info: constrained 'e1B_tx_hi' to bel 'X13/Y31/io1'
Info: constrained 'e1B_tx_lo' to bel 'X13/Y31/io0'
Info: constrained 'e1_rx_bias[0]' to bel 'X17/Y31/io0'
Info: constrained 'e1_rx_bias[1]' to bel 'X12/Y31/io1'
Info: constrained 'usb_dp' to bel 'X16/Y0/io0'
Info: constrained 'usb_dn' to bel 'X15/Y0/io0'
Info: constrained 'usb_pu' to bel 'X17/Y0/io0'
Info: constrained 'flash_mosi' to bel 'X23/Y0/io0'
Info: constrained 'flash_miso' to bel 'X23/Y0/io1'
Info: constrained 'flash_clk' to bel 'X24/Y0/io0'
Info: constrained 'flash_cs_n' to bel 'X24/Y0/io1'
Info: constrained 'e1_led_rclk' to bel 'X22/Y0/io1'
Info: constrained 'gps_reset_n' to bel 'X13/Y0/io1'
Info: constrained 'gps_rx' to bel 'X6/Y0/io0'
Info: constrained 'gps_tx' to bel 'X5/Y0/io0'
Info: constrained 'gps_pps' to bel 'X8/Y0/io0'
Info: constrained 'i2c_sda' to bel 'X9/Y0/io1'
Info: constrained 'i2c_scl' to bel 'X9/Y0/io0'
Info: constrained 'gpio[0]' to bel 'X19/Y0/io0'
Info: constrained 'gpio[1]' to bel 'X19/Y0/io1'
Info: constrained 'gpio[2]' to bel 'X21/Y0/io1'
Info: constrained 'clk_in' to bel 'X6/Y0/io1'
Info: constrained 'clk_tune_hi' to bel 'X7/Y0/io0'
Info: constrained 'clk_tune_lo' to bel 'X7/Y0/io1'
Info: constrained 'dbg_rx' to bel 'X18/Y0/io1'
Info: constrained 'dbg_tx' to bel 'X18/Y0/io0'
Info: constrained 'rgb[0]' to bel 'X4/Y31/io0'
Info: constrained 'rgb[1]' to bel 'X5/Y31/io0'
Info: constrained 'rgb[2]' to bel 'X6/Y31/io0'
Info: constraining clock net 'clk_sys' to 30.72 MHz
Info: constraining clock net 'clk_48m' to 48.00 MHz
1 251 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='wb_ack[1]', ena=None, clk='clk_sys')
--------------
0 252 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='spi_mux_I.srio_dat_o_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
1 257 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='soc_I.wb_ack[1]', ena=None, clk='clk_sys')
--------------
0 72 ControlSet(rs=None, ena=None, clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.tx_ll_I.lvl_prev_SB_DFFSS_Q_S', ena=None, clk='clk_48m')
--------------
1 73 ControlSet(rs=None, ena=None, clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O', ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m')
1 12 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O', ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m')
--------------
2 75 ControlSet(rs=None, ena=None, clk='clk_48m')
2 ControlSet(rs='soc_I.usb_I.rx_pkt_I.state[0]', ena='soc_I.usb_I.rx_pkt_I.crc5_ok_SB_DFFESR_Q_E', clk='clk_48m')
--------------
3 80 ControlSet(rs=None, ena=None, clk='clk_48m')
5 ControlSet(rs='soc_I.usb_I.rx_pkt_I.state[0]', ena='soc_I.usb_I.rx_pkt_I.bit_cnt_SB_DFFESR_Q_E', clk='clk_48m')
--------------
0 82 ControlSet(rs=None, ena=None, clk='clk_48m')
2 ControlSet(rs='soc_I.usb_I.rx_ll_I.samp_sync', ena=None, clk='clk_48m')
--------------
0 83 ControlSet(rs=None, ena=None, clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.rx_ll_I.samp_cnt_SB_DFFSR_Q_R', ena=None, clk='clk_48m')
--------------
0 84 ControlSet(rs=None, ena=None, clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_LUT4_I2_O[1]', ena='soc_I.usb_I.rx_pkt_I.crc_in_first_SB_DFFESS_Q_E', clk='clk_48m')
--------------
5 15 ControlSet(rs=None, ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_eop_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_rep_state_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sym_same_0_SB_LUT4_I3_1_O', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sym_se_0', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
3 87 ControlSet(rs=None, ena=None, clk='clk_48m')
3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
--------------
0 86 ControlSet(rs=None, ena=None, clk='clk_48m')
2 ControlSet(rs='soc_I.usb_I.eps_write_0', ena=None, clk='clk_48m')
--------------
0 89 ControlSet(rs=None, ena=None, clk='clk_48m')
3 ControlSet(rs='soc_I.usb_I.eps_bus_clear', ena=None, clk='clk_48m')
--------------
0 94 ControlSet(rs=None, ena=None, clk='clk_48m')
5 ControlSet(rs='soc_I.usb_I.csr_bus_clear', ena=None, clk='clk_48m')
--------------
0 264 ControlSet(rs=None, ena=None, clk='clk_sys')
7 ControlSet(rs='soc_I.uart_I.ub_rdata_SB_DFFSR_Q_9_R', ena=None, clk='clk_sys')
--------------
0 265 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', ena=None, clk='clk_sys')
--------------
4 270 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='soc_I.uart_I.uart_tx_I.bit_cnt_SB_DFFESS_Q_S', ena='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', clk='clk_sys')
--------------
4 275 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='soc_I.uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_S', ena='soc_I.uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_E', clk='clk_sys')
--------------
1 276 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_store_SB_DFFESS_Q_E', clk='clk_sys')
--------------
5 281 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_stalu_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O', clk='clk_sys')
--------------
0 282 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_stalu_SB_DFFESR_Q_E', clk='clk_sys')
--------------
2 284 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_is_lh_SB_DFFESR_Q_E', clk='clk_sys')
--------------
1 285 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_branch_SB_DFFESR_Q_E[2]', clk='clk_sys')
--------------
1 286 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 13 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys')
1 ControlSet(rs='soc_I.iobuf_I.dma_I.ack_rd_SB_LUT4_O_I2_SB_LUT4_I2_O[1]', ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys')
1 287 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.iobuf_I.dma_I.ack_rd_SB_LUT4_O_I2_SB_LUT4_I2_O[1]', ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys')
--------------
0 288 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.e1_I.wb_rdata_SB_DFFSR_Q_14_R', ena=None, clk='clk_sys')
--------------
0 290 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_DFFSR_D_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys')
--------------
0 292 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_I3_SB_DFFSR_D_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys')
--------------
0 296 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_DFF_D_Q_SB_LUT4_I3_2_O', ena=None, clk='clk_sys')
--------------
0 297 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S_SB_DFFSS_D_Q_SB_LUT4_I3_1_O_SB_LUT4_I2_O', ena=None, clk='clk_sys')
--------------
1 299 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S_SB_DFFSS_D_Q_SB_LUT4_I3_1_O[0]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S_SB_DFFSS_D_Q_SB_LUT4_I3_O_SB_LUT4_I3_O', clk='clk_sys')
--------------
0 300 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S[2]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_E', clk='clk_sys')
--------------
0 301 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_DFFESS_Q_S[2]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_DFFESS_Q_E', clk='clk_sys')
--------------
0 302 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_DFFESS_Q_S[2]', ena=None, clk='clk_sys')
--------------
3 19 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_buf_I.buf_tx_re_SB_LUT4_O_I3', clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_DFFER_Q_E[1]', clk='clk_sys')
4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_LUT4_I2_O', clk='clk_sys')
--------------
1 303 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 304 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I2_O', clk='clk_sys')
--------------
0 308 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
0 312 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O', ena=None, clk='clk_sys')
--------------
0 316 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_I2_SB_LUT4_I3_O', ena=None, clk='clk_sys')
--------------
0 318 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_DFF_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
0 320 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_DFF_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
5 327 ControlSet(rs=None, ena=None, clk='clk_sys')
7 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_1_O_SB_LUT4_O_I3_SB_LUT4_I2_O', clk='clk_sys')
--------------
4 332 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_1_O_SB_LUT4_O_I3_SB_DFFESR_Q_E', clk='clk_sys')
--------------
6 339 ControlSet(rs=None, ena=None, clk='clk_sys')
7 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_1_O_SB_LUT4_I2_O', clk='clk_sys')
--------------
0 340 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_DFF_D_Q[0]', ena=None, clk='clk_sys')
--------------
0 341 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.mem_state_SB_DFFESR_Q_R', ena='soc_I.cpu_I.mem_valid_SB_DFFESR_Q_E', clk='clk_sys')
--------------
2 343 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.cpu_I.mem_state_SB_DFFESR_Q_R', ena='soc_I.cpu_I.mem_state_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 344 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.mem_do_wdata_SB_DFFESS_Q_S[0]', ena='soc_I.cpu_I.mem_do_wdata_SB_DFFESS_Q_E', clk='clk_sys')
--------------
0 345 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.mem_do_rdata_SB_DFFESS_Q_S[2]', ena='soc_I.cpu_I.mem_do_rdata_SB_DFFESS_Q_E', clk='clk_sys')
--------------
0 346 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.instr_or_SB_DFFESR_Q_E', ena=None, clk='clk_sys')
--------------
0 347 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.instr_lbu_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]', ena='soc_I.cpu_I.mem_do_prefetch_SB_DFFESR_Q_E', clk='clk_sys')
--------------
1 348 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.instr_lbu_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I3_O[0]', ena='soc_I.cpu_I.mem_do_rinst_SB_DFFESS_Q_E', clk='clk_sys')
--------------
0 349 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.decoder_pseudo_trigger_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
0 350 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.alu_wait_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
1 192 ControlSet(rs='rst_sys', ena=None, clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys')
3 ControlSet(rs='rst_sys', ena='misc_I.bus_we_boot', clk='clk_sys')
3 ControlSet(rs='rst_sys', ena='misc_I.dfu_I.wb_sel_SB_DFFER_Q_E', clk='clk_sys')
2 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E', clk='clk_sys')
7 ControlSet(rs='rst_sys', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I3_SB_DFFER_Q_E', clk='clk_sys')
2 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.dma_I.state_SB_DFFER_Q_E', clk='clk_sys')
3 ControlSet(rs='rst_sys', ena='soc_I.rgb_I.led_ctrl_SB_DFFER_Q_E', clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys')
--------------
0 351 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_I.gf_I.state_SB_DFFESS_Q_E', clk='clk_sys')
--------------
1 352 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='i2c_I.core_I.sda_oe_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 353 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='i2c_I.core_I.scl_oe_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 354 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_I.gf_I.state_SB_DFFESS_Q_E', clk='clk_sys')
--------------
5 67 ControlSet(rs='rst_48m', ena=None, clk='clk_48m')
3 ControlSet(rs='rst_48m', ena='soc_I.usb_I.tx_ll_I.state_SB_DFFER_Q_E', clk='clk_48m')
2 ControlSet(rs='rst_48m', ena='soc_I.usb_I.tx_ll_I.br_cnt[2]', clk='clk_48m')
--------------
0 355 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='misc_I.pps_flt_I.state_SB_LUT4_I1_O[1]', ena='misc_I.pps_flt_I.state_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 356 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='misc_I.dfu_I.btn_flt_I.fall_SB_DFF_Q_D', ena='misc_I.dfu_I.btn_flt_I.state_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 363 ControlSet(rs=None, ena=None, clk='clk_sys')
7 ControlSet(rs='misc_I.bus_we_led_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
0 368 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='i2c_I.core_I.cyc_cnt_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
2 371 ControlSet(rs=None, ena=None, clk='clk_sys')
3 ControlSet(rs='i2c_I.core_I.bit_cnt_SB_DFFESR_Q_R[1]', ena='i2c_I.core_I.bit_last_SB_DFFE_Q_E', clk='clk_sys')
--------------
0 378 ControlSet(rs=None, ena=None, clk='clk_sys')
7 ControlSet(rs='gps_uart_I.ub_rdata_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
0 379 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='gps_uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', ena=None, clk='clk_sys')
--------------
4 384 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='gps_uart_I.uart_tx_I.bit_cnt_SB_DFFESS_Q_S', ena='gps_uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', clk='clk_sys')
--------------
4 389 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='gps_uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_S', ena='gps_uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_E', clk='clk_sys')
--------------
0 390 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_DFFESR_Q_E', clk='clk_sys')
--------------
3 393 ControlSet(rs=None, ena=None, clk='clk_sys')
3 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S_SB_DFFSS_D_Q_SB_LUT4_I3_O_SB_LUT4_I3_O', clk='clk_sys')
--------------
3 397 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S_SB_DFFSS_D_Q_SB_LUT4_I3_O[0]', clk='clk_sys')
--------------
1 399 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='e1A_rx_lo_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O_SB_LUT4_I2_O', clk='clk_sys')
--------------
1 401 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O_SB_LUT4_I2_O', clk='clk_sys')
--------------
1 405 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs=None, ena='tick_e1_tx[0]', clk='clk_sys')
--------------
0 96 ControlSet(rs=None, ena=None, clk='clk_48m')
2 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_data_crc_SB_DFFE_Q_E', clk='clk_48m')
--------------
1 100 ControlSet(rs=None, ena=None, clk='clk_48m')
4 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.mc_op_tx', clk='clk_48m')
--------------
4 104 ControlSet(rs=None, ena=None, clk='clk_48m')
4 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.mc_op_ld', clk='clk_48m')
--------------
2 111 ControlSet(rs=None, ena=None, clk='clk_48m')
7 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.epfw_issue_wb_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]', clk='clk_48m')
--------------
1 117 ControlSet(rs=None, ena=None, clk='clk_48m')
6 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.ep_bd_dual_SB_LUT4_I2_O[2]', clk='clk_48m')
--------------
3 120 ControlSet(rs=None, ena=None, clk='clk_48m')
3 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.bd_state_SB_DFFE_Q_E', clk='clk_48m')
--------------
0 124 ControlSet(rs=None, ena=None, clk='clk_48m')
4 ControlSet(rs=None, ena='soc_I.usb_I.rxpkt_done_ok', clk='clk_48m')
--------------
0 127 ControlSet(rs=None, ena=None, clk='clk_48m')
3 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.token_data_SB_DFFE_Q_E[1]', clk='clk_48m')
--------------
0 406 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.ack_rd_SB_LUT4_O_I2_SB_LUT4_I2_O[1]', clk='clk_sys')
--------------
1 410 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs=None, ena='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I3_I2', clk='clk_sys')
--------------
0 414 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs=None, ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_1_D_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_LUT4_I0_O[0]', clk='clk_sys')
--------------
1 415 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs=None, ena='soc_I.cpu_I.reg_op1_SB_DFFE_Q_31_E', clk='clk_sys')
--------------
2 417 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs=None, ena='soc_I.cpu_I.instr_sra_SB_LUT4_I2_O[3]', clk='clk_sys')
--------------
4 421 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs=None, ena='soc_I.bridge_I.ram_rdy_SB_LUT4_I0_O[1]', clk='clk_sys')
--------------
0 423 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs=None, ena='i2c_I.stb', clk='clk_sys')
--------------
1 424 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs=None, ena='i2c_I.core_I.bit_last_SB_DFFE_Q_E', clk='clk_sys')
--------------
Control Set Optimizer: cost 100 to reduce control sets from 207 to 99
Total control sets: 99
1 2
3 1
4 1
6 1
8 13
9 21
10 12
11 3
12 3
13 5
14 2
15 2
16 5
17 2
18 1
19 1
20 4
24 1
25 1
26 1
29 1
31 2
32 5
33 2
45 1
55 1
60 1
67 1
127 1
192 1
424 1
1 ControlSet(rs='sys_mgr_I.rst_30m72_i', ena=None, clk='clk_48m')
1 ControlSet(rs='sys_mgr_I.pll_lock_SB_LUT4_I3_O', ena=None, clk='clk_sys')
3 ControlSet(rs='sys_mgr_I.pll_lock_SB_LUT4_I3_O', ena='sys_mgr_I.rst_30m72_i', clk='clk_sys')
4 ControlSet(rs='soc_I.usb_I.txll_start', ena='soc_I.usb_I.tx_ll_I.br_cnt[2]', clk='clk_48m')
6 ControlSet(rs='rst_sys', ena=None, clk='clk_48m')
8 ControlSet(rs=None, ena='spi_mux_I.shift_ce', clk='clk_sys')
8 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.token_data_SB_DFFE_Q_9_E[1]', clk='clk_48m')
8 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_I1', ena='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_DFFESR_Q_D_SB_LUT4_I2_O', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[4]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[4]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[3]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[1]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='misc_I.bus_we_gpio', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[1]', clk='clk_sys')
8 ControlSet(rs=None, ena='soc_I.e1_buf_I.t_done[2]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[2]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[3]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[2]', clk='clk_sys')
9 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.pid_cap', clk='clk_48m')
9 ControlSet(rs='soc_I.uart_I.ub_rdata_rst', ena=None, clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.ub_wr_data', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_fifo_I.ram_rd_ena', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='dbg_tx_SB_DFFES_Q_E', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.urf_wren', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_fifo_I.ram_rd_ena', clk='clk_sys')
9 ControlSet(rs=None, ena='soc_I.uart_I.uart_rx_I.ce', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_led', clk='clk_sys')
9 ControlSet(rs=None, ena='tick_e1_rx[0]', clk='clk_sys')
9 ControlSet(rs=None, ena='i2c_I.ack_out_SB_DFFE_Q_E', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_uart_I.ub_wr_data', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_tx_SB_DFFES_Q_E', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_fifo_I.ram_rd_ena', clk='clk_sys')
9 ControlSet(rs=None, ena='gps_uart_I.uart_rx_I.ce', clk='clk_sys')
9 ControlSet(rs='gps_uart_I.ub_rdata_rst', ena=None, clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_e1[1]', clk='clk_sys')
9 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.m1_addr_ce', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_e1[0]', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_fifo_I.ram_rd_ena', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_uart_I.urf_wren', clk='clk_sys')
10 ControlSet(rs='soc_I.usb_I.trans_I.len_ld', ena=None, clk='clk_48m')
10 ControlSet(rs='rst_48m', ena='soc_I.usb_I.cr_bus_we', clk='clk_48m')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[4]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[4]', clk='clk_sys')
10 ControlSet(rs='i2c_I.bus_clr', ena=None, clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[3]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[2]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[3]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[1]', clk='clk_sys')
10 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I3_O[2]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[2]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[1]', clk='clk_sys')
11 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m')
11 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.len_dec', clk='clk_48m')
11 ControlSet(rs='soc_I.usb_I.trans_I.mc_op_zlen', ena=None, clk='clk_48m')
12 ControlSet(rs=None, ena='soc_I.uart_I.ub_wr_div', clk='clk_sys')
12 ControlSet(rs='misc_I.bus_clr', ena=None, clk='clk_sys')
12 ControlSet(rs=None, ena='gps_uart_I.ub_wr_div', clk='clk_sys')
13 ControlSet(rs=None, ena='soc_I.cpu_I.decoder_pseudo_trigger_SB_LUT4_I2_O[0]', clk='clk_sys')
13 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys')
13 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_clk[1]', clk='clk_sys')
13 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_clk[0]', clk='clk_sys')
13 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_buf_I.buf_tx_ts_SB_DFFES_Q_E', clk='clk_sys')
14 ControlSet(rs=None, ena='soc_I.usb_I.ep_status_I.p_read_2', clk='clk_48m')
14 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.m0_addr_ce', clk='clk_sys')
15 ControlSet(rs=None, ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
15 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='tick_e1_tx[0]', clk='clk_sys')
16 ControlSet(rs='soc_I.wb_48m_xclk_I.s_cyc_SB_LUT4_I3_O', ena=None, clk='clk_sys')
16 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.crc_in_valid', clk='clk_48m')
16 ControlSet(rs='soc_I.usb_I.ep_status_I.s_zero_2', ena='soc_I.usb_I.ep_status_I.s_read_2', clk='clk_48m')
16 ControlSet(rs=None, ena='soc_I.ub_ack', clk='clk_48m')
16 ControlSet(rs=None, ena='soc_I.e1_buf_tx_re[0]', clk='clk_sys')
17 ControlSet(rs='soc_I.e1_I.bus_clr', ena=None, clk='clk_sys')
17 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I3_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_1_D_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_LUT4_I0_1_O', clk='clk_sys')
18 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.instr_or_SB_DFFESR_Q_E', clk='clk_sys')
19 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena=None, clk='clk_sys')
20 ControlSet(rs='soc_I.usb_I.oob_sof_SB_LUT4_I2_O', ena=None, clk='clk_48m')
20 ControlSet(rs='soc_I.usb_I.phy_I.rx_dn_SB_LUT4_I2_O', ena=None, clk='clk_48m')
20 ControlSet(rs=None, ena='soc_I.cpu_I.trap_SB_LUT4_I3_1_O', clk='clk_sys')
20 ControlSet(rs='misc_I.wb_ack_SB_LUT4_I2_O_SB_LUT4_I3_O', ena=None, clk='clk_sys')
24 ControlSet(rs=None, ena='soc_I.e1_buf_rx_we[0]', clk='clk_sys')
25 ControlSet(rs=None, ena='soc_I.e1_buf_I.t_busy_SB_LUT4_I3_O', clk='clk_sys')
26 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena=None, clk='clk_sys')
29 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.crc_in_valid', clk='clk_48m')
31 ControlSet(rs=None, ena='soc_I.cpu_I.instr_lbu_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_I2_O[3]', clk='clk_sys')
31 ControlSet(rs='soc_I.cpu_I.decoded_imm_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I2_1_O', ena='soc_I.cpu_I.decoder_pseudo_trigger_SB_LUT4_I2_O[0]', clk='clk_sys')
32 ControlSet(rs=None, ena='soc_I.pb_rst_n_SB_LUT4_I2_O', clk='clk_sys')
32 ControlSet(rs=None, ena='soc_I.cpu_I.trap_SB_LUT4_I2_O', clk='clk_sys')
32 ControlSet(rs='soc_I.bridge_I.wb_cyc_rst', ena=None, clk='clk_sys')
32 ControlSet(rs=None, ena='soc_I.cpu_I.instr_ecall_ebreak_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[3]', clk='clk_sys')
32 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.ack_rd', clk='clk_sys')
33 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena=None, clk='clk_sys')
33 ControlSet(rs=None, ena='soc_I.cpu_I.alu_ltu_SB_LUT4_I2_O[3]', clk='clk_sys')
45 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.epbam_arb_I.reselect', clk='clk_sys')
55 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.spram_arb_I.reselect', clk='clk_sys')
60 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.alu_wait_SB_LUT4_I3_O[0]', clk='clk_sys')
67 ControlSet(rs='rst_48m', ena=None, clk='clk_48m')
127 ControlSet(rs=None, ena=None, clk='clk_48m')
192 ControlSet(rs='rst_sys', ena=None, clk='clk_sys')
424 ControlSet(rs=None, ena=None, clk='clk_sys')
LUT replication: 0 new LUTs in 0 groups
Info: Packing constants..
Info: Packing IOs..
Info: clk_in feeds SB_IO sys_mgr_I.gb_in, removing $nextpnr_ibuf clk_in.
Info: clk_tune_hi feeds SB_IO misc_I.pdm_clk_I[1].io_reg_I, removing $nextpnr_obuf clk_tune_hi.
Info: clk_tune_lo feeds SB_IO misc_I.pdm_clk_I[0].io_reg_I, removing $nextpnr_obuf clk_tune_lo.
Info: e1A_rx_hi_p feeds SB_IO e1A_rx_hi_p_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_hi_p.
Info: e1A_rx_lo_p feeds SB_IO e1A_rx_lo_p_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_lo_p.
Info: e1A_tx_hi feeds SB_IO e1A_tx_hi_SB_IO_PACKAGE_PIN, removing $nextpnr_obuf e1A_tx_hi.
Info: e1A_tx_lo feeds SB_IO e1A_tx_lo_SB_IO_PACKAGE_PIN, removing $nextpnr_obuf e1A_tx_lo.
Info: e1B_rx_hi_p feeds SB_IO e1_dummy_rx_I[1], removing $nextpnr_ibuf e1B_rx_hi_p.
Info: e1B_rx_lo_p feeds SB_IO e1_dummy_rx_I[0], removing $nextpnr_ibuf e1B_rx_lo_p.
Info: e1B_tx_hi feeds SB_IO e1_dummy_tx_I[1], removing $nextpnr_obuf e1B_tx_hi.
Info: e1B_tx_lo feeds SB_IO e1_dummy_tx_I[0], removing $nextpnr_obuf e1B_tx_lo.
Info: e1_led_rclk feeds SB_IO spi_mux_I.iob_I[0], removing $nextpnr_iobuf e1_led_rclk.
Info: flash_clk feeds SB_IO spi_mux_I.iob_I[1], removing $nextpnr_iobuf flash_clk.
Info: flash_miso feeds SB_IO spi_mux_I.iob_I[2], removing $nextpnr_iobuf flash_miso.
Info: flash_mosi feeds SB_IO spi_mux_I.iob_I[3], removing $nextpnr_iobuf flash_mosi.
Info: gps_pps feeds SB_IO misc_I.pps_iob_I, removing $nextpnr_ibuf gps_pps.
Info: gps_reset_n feeds SB_IO misc_I.gpio_iob_I[3], removing $nextpnr_obuf gps_reset_n.
Info: i2c_scl feeds SB_IO i2c_iob_I[1], removing $nextpnr_iobuf i2c_scl.
Info: i2c_sda feeds SB_IO i2c_iob_I[0], removing $nextpnr_iobuf i2c_sda.
Info: usb_dn feeds SB_IO soc_I.usb_I.phy_I.io_dn_I, removing $nextpnr_iobuf usb_dn.
Info: usb_dp feeds SB_IO soc_I.usb_I.phy_I.io_dp_I, removing $nextpnr_iobuf usb_dp.
Info: gpio[0] feeds SB_IO misc_I.gpio_iob_I[0], removing $nextpnr_iobuf gpio[0].
Info: gpio[1] feeds SB_IO misc_I.gpio_iob_I[1], removing $nextpnr_iobuf gpio[1].
Info: gpio[2] feeds SB_IO misc_I.gpio_iob_I[2], removing $nextpnr_iobuf gpio[2].
Info: e1_rx_bias[0] feeds SB_IO misc_I.pdm_e1_I[0].io_reg_I, removing $nextpnr_obuf e1_rx_bias[0].
Info: e1_rx_bias[1] feeds SB_IO misc_I.pdm_e1_I[1].io_reg_I, removing $nextpnr_obuf e1_rx_bias[1].
Info: rgb[0] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO
Info: rgb[1] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO
Info: rgb[2] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO
Info: Packing LUT-FFs..
Info: 1791 LCs used as LUT4 only
Info: 1703 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info: 510 LCs used as DFF only
Info: Packing carries..
Info: 270 LCs used as CARRY only
Info: Packing RAMs..
Info: Placing PLLs..
Info: constrained PLL 'sys_mgr_I.pll_I' to X12/Y31/pll_3
Info: Packing special functions..
Info: constrained SB_LEDDA_IP 'soc_I.rgb_I.led_I' to X0/Y31/ledda_ip_2
Info: constrained SB_RGBA_DRV 'soc_I.rgb_I.rgb_drv_I' to X0/Y30/rgba_drv_0
Info: constrained SB_SPI 'soc_I.spi_I.spi_I' to X0/Y0/spi_0
Info: PLL 'sys_mgr_I.pll_I' has LOCK output, need to pass all outputs via LUT
Info: constrained 'sys_mgr_I.pll_lock_SB_LUT4_I3_LC' to X1/Y30/lc0
Info: Constraining chains...
Info: 216 LCs used to legalise carry chains.
Info: Checksum: 0xbd206b2f
Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0x290952ac
Info: Device utilisation:
Info: ICESTORM_LC: 4495/ 5280 85%
Info: ICESTORM_RAM: 20/ 30 66%
Info: SB_IO: 32/ 96 33%
Info: SB_GB: 4/ 8 50%
Info: ICESTORM_PLL: 1/ 1 100%
Info: SB_WARMBOOT: 1/ 1 100%
Info: ICESTORM_DSP: 6/ 8 75%
Info: ICESTORM_HFOSC: 0/ 1 0%
Info: ICESTORM_LFOSC: 0/ 1 0%
Info: SB_I2C: 0/ 2 0%
Info: SB_SPI: 1/ 2 50%
Info: IO_I3C: 0/ 2 0%
Info: SB_LEDDA_IP: 1/ 1 100%
Info: SB_RGBA_DRV: 1/ 1 100%
Info: ICESTORM_SPRAM: 4/ 4 100%
Info: Placed 39 cells based on constraints.
Info: Creating initial analytic placement for 3600 cells, random placement wirelen = 110077.
Info: at initial placer iter 0, wirelen = 3525
Info: at initial placer iter 1, wirelen = 3266
Info: at initial placer iter 2, wirelen = 3326
Info: at initial placer iter 3, wirelen = 3318
Info: Running main analytical placer.
Info: at iteration #1, type ALL: wirelen solved = 3253, spread = 38465, legal = 55181; time = 0.43s
Info: at iteration #2, type ALL: wirelen solved = 4546, spread = 30601, legal = 48931; time = 0.38s
Info: at iteration #3, type ALL: wirelen solved = 5816, spread = 28522, legal = 47169; time = 0.39s
Info: at iteration #4, type ALL: wirelen solved = 6568, spread = 27769, legal = 39876; time = 0.38s
Info: at iteration #5, type ALL: wirelen solved = 7865, spread = 26743, legal = 42812; time = 0.23s
Info: at iteration #6, type ALL: wirelen solved = 8347, spread = 26353, legal = 48459; time = 0.44s
Info: at iteration #7, type ALL: wirelen solved = 8919, spread = 26392, legal = 40823; time = 0.30s
Info: at iteration #8, type ALL: wirelen solved = 9364, spread = 26336, legal = 38573; time = 0.28s
Info: at iteration #9, type ALL: wirelen solved = 9686, spread = 26025, legal = 40567; time = 0.25s
Info: at iteration #10, type ALL: wirelen solved = 10169, spread = 25720, legal = 44681; time = 0.32s
Info: at iteration #11, type ALL: wirelen solved = 10572, spread = 26140, legal = 40978; time = 0.33s
Info: at iteration #12, type ALL: wirelen solved = 11019, spread = 26172, legal = 45327; time = 0.45s
Info: at iteration #13, type ALL: wirelen solved = 11243, spread = 25782, legal = 42859; time = 0.34s
Info: HeAP Placer Time: 5.44s
Info: of which solving equations: 1.32s
Info: of which spreading cells: 0.20s
Info: of which strict legalisation: 3.20s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 790, wirelen = 38573
Info: at iteration #5: temp = 0.000000, timing cost = 586, wirelen = 32008
Info: at iteration #10: temp = 0.000000, timing cost = 532, wirelen = 30292
Info: at iteration #15: temp = 0.000000, timing cost = 529, wirelen = 29339
Info: at iteration #20: temp = 0.000000, timing cost = 539, wirelen = 28590
Info: at iteration #25: temp = 0.000000, timing cost = 534, wirelen = 28403
Info: at iteration #30: temp = 0.000000, timing cost = 531, wirelen = 28356
Info: at iteration #32: temp = 0.000000, timing cost = 531, wirelen = 28351
Info: SA placement time 8.75s
Info: Max frequency for clock 'clk_sys': 32.81 MHz (PASS at 30.72 MHz)
Info: Max frequency for clock 'clk_48m': 51.22 MHz (PASS at 48.00 MHz)
Info: Max delay <async> -> posedge clk_sys: 7.02 ns
Info: Max delay posedge clk_48m -> <async> : 4.95 ns
Info: Max delay posedge clk_48m -> posedge clk_sys: 5.80 ns
Info: Max delay posedge clk_sys -> <async> : 12.72 ns
Info: Max delay posedge clk_sys -> posedge clk_48m: 14.54 ns
Info: Slack histogram:
Info: legend: * represents 55 endpoint(s)
Info: + represents [1,55) endpoint(s)
Info: [ 1310, 5254) |*+
Info: [ 5254, 9198) |*****+
Info: [ 9198, 13142) |*********+
Info: [ 13142, 17086) |*******************************+
Info: [ 17086, 21030) |***********************+
Info: [ 21030, 24974) |*******************************+
Info: [ 24974, 28918) |************************************************************
Info: [ 28918, 32862) |**+
Info: [ 32862, 36806) |
Info: [ 36806, 40750) |
Info: [ 40750, 44694) |
Info: [ 44694, 48638) |
Info: [ 48638, 52582) |
Info: [ 52582, 56526) |
Info: [ 56526, 60470) |
Info: [ 60470, 64414) |
Info: [ 64414, 68358) |
Info: [ 68358, 72302) |+
Info: [ 72302, 76246) |+
Info: [ 76246, 80190) |+
Info: Checksum: 0x373cc6b7
Info: Routing..
Info: Setting up routing queue.
Info: Routing 15492 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 41 958 | 41 958 | 14537| 0.10 0.10|
Info: 2000 | 63 1936 | 22 978 | 13562| 0.08 0.18|
Info: 3000 | 130 2869 | 67 933 | 12642| 0.20 0.37|
Info: 4000 | 243 3756 | 113 887 | 11794| 0.23 0.60|
Info: 5000 | 365 4634 | 122 878 | 10931| 0.22 0.82|
Info: 6000 | 539 5460 | 174 826 | 10183| 0.25 1.08|
Info: 7000 | 733 6266 | 194 806 | 9456| 0.32 1.39|
Info: 8000 | 957 7042 | 224 776 | 8753| 0.32 1.71|
Info: 9000 | 1162 7837 | 205 795 | 8013| 0.26 1.97|
Info: 10000 | 1502 8497 | 340 660 | 7527| 0.51 2.48|
Info: 11000 | 1990 9009 | 488 512 | 7303| 0.70 3.19|
Info: 12000 | 2504 9495 | 514 486 | 7152| 0.79 3.98|
Info: 13000 | 2989 10010 | 485 515 | 6901| 0.76 4.74|
Info: 14000 | 3491 10508 | 502 498 | 6739| 0.75 5.49|
Info: 15000 | 4048 10951 | 557 443 | 6588| 0.61 6.10|
Info: 16000 | 4484 11515 | 436 564 | 6265| 0.51 6.61|
Info: 17000 | 5019 11980 | 535 465 | 6102| 0.63 7.24|
Info: 18000 | 5460 12539 | 441 559 | 5769| 0.48 7.72|
Info: 19000 | 5757 13242 | 297 703 | 5217| 0.47 8.20|
Info: 20000 | 6170 13829 | 413 587 | 4842| 0.41 8.61|
Info: 21000 | 6613 14386 | 443 557 | 4452| 1.63 10.24|
Info: 22000 | 7149 14850 | 536 464 | 4314| 1.23 11.47|
Info: 23000 | 7735 15264 | 586 414 | 4258| 0.83 12.30|
Info: 24000 | 8300 15699 | 565 435 | 4195| 0.77 13.07|
Info: 25000 | 8867 16132 | 567 433 | 4128| 0.92 14.00|
Info: 26000 | 9471 16528 | 604 396 | 4064| 0.84 14.84|
Info: 27000 | 10046 16953 | 575 425 | 3955| 0.90 15.74|
Info: 28000 | 10617 17382 | 571 429 | 3858| 0.64 16.37|
Info: 29000 | 11110 17889 | 493 507 | 3734| 0.76 17.13|
Info: 30000 | 11706 18293 | 596 404 | 3682| 0.61 17.74|
Info: 31000 | 12274 18725 | 568 432 | 3602| 0.66 18.40|
Info: 32000 | 12782 19217 | 508 492 | 3451| 0.58 18.98|
Info: 33000 | 13354 19645 | 572 428 | 3381| 0.77 19.74|
Info: 34000 | 13880 20119 | 526 474 | 3260| 0.55 20.29|
Info: 35000 | 14391 20608 | 511 489 | 3180| 0.64 20.93|
Info: 36000 | 14965 21034 | 574 426 | 3102| 0.55 21.49|
Info: 37000 | 15533 21466 | 568 432 | 3015| 0.54 22.03|
Info: 38000 | 16126 21873 | 593 407 | 2915| 0.79 22.82|
Info: 39000 | 16701 22298 | 575 425 | 2853| 0.70 23.52|
Info: 40000 | 17260 22739 | 559 441 | 2781| 0.71 24.23|
Info: 41000 | 17803 23196 | 543 457 | 2688| 0.77 25.00|
Info: 42000 | 18205 23794 | 402 598 | 2277| 0.47 25.48|
Info: 43000 | 18579 24420 | 374 626 | 1826| 0.48 25.96|
Info: 44000 | 19020 24979 | 441 559 | 1438| 0.87 26.83|
Info: 45000 | 19564 25435 | 544 456 | 1335| 1.06 27.89|
Info: 46000 | 19932 26067 | 368 632 | 916| 1.40 29.29|
Info: 47000 | 20283 26716 | 351 649 | 507| 2.00 31.29|
Info: 48000 | 20767 27232 | 484 516 | 283| 1.47 32.76|
Info: 48415 | 20868 27547 | 101 315 | 0| 0.25 33.01|
Info: Routing complete.
Info: Router1 time 33.01s
Info: Checksum: 0x82d39c99
Info: Critical path report for clock 'clk_sys' (posedge -> posedge):
Info: curr total
Info: 1.4 1.4 Source soc_I.cpu_I.latched_is_lb_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_5_LC.O
Info: 3.6 5.0 Net soc_I.cpu_I.reg_out[1] budget 1.920000 ns (7,9) -> (3,11)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_O_LC.I1
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:160.52-160.59
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: 1.2 6.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_O_LC.O
Info: 1.8 8.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2[0] budget 1.947000 ns (3,11) -> (4,12)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_LC.I1
Info: Defined in:
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info: 1.2 9.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_LC.O
Info: 3.0 12.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O[0] budget 1.596000 ns (4,12) -> (4,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0$CARRY.I1
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:29.22-29.23
Info: 0.7 12.9 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0$CARRY.COUT
Info: 0.0 12.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[1] budget 0.000000 ns (4,17) -> (4,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_22_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 13.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_22_LC.COUT
Info: 0.0 13.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[2] budget 0.000000 ns (4,17) -> (4,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_11_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 13.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_11_LC.COUT
Info: 0.0 13.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[3] budget 0.000000 ns (4,17) -> (4,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_9_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 13.7 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_9_LC.COUT
Info: 0.0 13.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[4] budget 0.000000 ns (4,17) -> (4,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_8_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 14.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_8_LC.COUT
Info: 0.0 14.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[5] budget 0.000000 ns (4,17) -> (4,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_7_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 14.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_7_LC.COUT
Info: 0.0 14.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[6] budget 0.000000 ns (4,17) -> (4,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_6_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 14.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_6_LC.COUT
Info: 0.0 14.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[7] budget 0.000000 ns (4,17) -> (4,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_5_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 14.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_5_LC.COUT
Info: 0.6 15.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[8] budget 0.560000 ns (4,17) -> (4,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_4_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 15.7 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_4_LC.COUT
Info: 0.0 15.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[9] budget 0.000000 ns (4,18) -> (4,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_3_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 15.9 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_3_LC.COUT
Info: 0.0 15.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[10] budget 0.000000 ns (4,18) -> (4,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_2_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 16.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_2_LC.COUT
Info: 0.0 16.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[11] budget 0.000000 ns (4,18) -> (4,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_1_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 16.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_1_LC.COUT
Info: 0.0 16.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[12] budget 0.000000 ns (4,18) -> (4,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 16.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_LC.COUT
Info: 0.0 16.8 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[13] budget 0.000000 ns (4,18) -> (4,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_29_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 17.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_29_LC.COUT
Info: 0.0 17.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[14] budget 0.000000 ns (4,18) -> (4,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_28_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 17.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_28_LC.COUT
Info: 0.0 17.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[15] budget 0.000000 ns (4,18) -> (4,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_27_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 17.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_27_LC.COUT
Info: 0.6 18.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[16] budget 0.560000 ns (4,18) -> (4,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_26_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 18.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_26_LC.COUT
Info: 0.0 18.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[17] budget 0.000000 ns (4,19) -> (4,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_25_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 18.7 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_25_LC.COUT
Info: 0.0 18.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[18] budget 0.000000 ns (4,19) -> (4,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_24_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 19.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_24_LC.COUT
Info: 0.0 19.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[19] budget 0.000000 ns (4,19) -> (4,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_23_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 19.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_23_LC.COUT
Info: 0.0 19.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[20] budget 0.000000 ns (4,19) -> (4,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_21_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 19.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_21_LC.COUT
Info: 0.0 19.6 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[21] budget 0.000000 ns (4,19) -> (4,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_20_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 19.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_20_LC.COUT
Info: 0.0 19.8 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[22] budget 0.000000 ns (4,19) -> (4,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_19_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 20.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_19_LC.COUT
Info: 0.0 20.1 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[23] budget 0.000000 ns (4,19) -> (4,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_18_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 20.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_18_LC.COUT
Info: 0.6 20.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[24] budget 0.560000 ns (4,19) -> (4,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_17_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 21.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_17_LC.COUT
Info: 0.0 21.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[25] budget 0.000000 ns (4,20) -> (4,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_16_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 21.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_16_LC.COUT
Info: 0.0 21.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[26] budget 0.000000 ns (4,20) -> (4,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_15_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 21.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_15_LC.COUT
Info: 0.0 21.8 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[27] budget 0.000000 ns (4,20) -> (4,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_14_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 22.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_14_LC.COUT
Info: 0.0 22.1 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[28] budget 0.000000 ns (4,20) -> (4,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_13_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 22.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_13_LC.COUT
Info: 0.0 22.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[29] budget 0.000000 ns (4,20) -> (4,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_12_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 22.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_12_LC.COUT
Info: 0.7 23.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[30] budget 0.660000 ns (4,20) -> (4,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_10_LC.I3
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.9 24.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_10_LC.O
Info: 2.4 26.6 Net soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_29_D_SB_LUT4_O_I0[30] budget 2.501000 ns (4,20) -> (5,23)
Info: Sink soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_LC.I0
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:33.26-33.27
Info: 1.3 27.8 Source soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_LC.O
Info: 2.4 30.2 Net soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1[0] budget 2.736000 ns (5,23) -> (4,20)
Info: Sink soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_LC.I1
Info: Defined in:
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info: 1.2 31.4 Setup soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_LC.I1
Info: 15.9 ns logic, 15.5 ns routing
Info: Critical path report for clock 'clk_48m' (posedge -> posedge):
Info: curr total
Info: 1.4 1.4 Source soc_I.usb_I.tx_ll_I.ll_ack_SB_DFF_Q_D_SB_LUT4_O_LC.O
Info: 4.2 5.6 Net soc_I.usb_I.txll_ack budget 2.514000 ns (20,2) -> (20,16)
Info: Sink soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_LC.I2
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:72.7-72.15
Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info: 1.2 6.8 Source soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_LC.O
Info: 1.8 8.6 Net soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O[0] budget 1.615000 ns (20,16) -> (21,17)
Info: Sink soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_LC.I2
Info: Defined in:
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info: 1.2 9.8 Source soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_LC.O
Info: 1.8 11.5 Net soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O budget 1.694000 ns (21,17) -> (22,16)
Info: Sink soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_O_2_LC.I3
Info: Defined in:
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info: 0.9 12.4 Source soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_O_2_LC.O
Info: 1.8 14.2 Net soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O[0] budget 1.511000 ns (22,16) -> (22,16)
Info: Sink soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_I3_LC.I3
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:231.13-244.3
Info: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154.17-154.58
Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:33.26-33.27
Info: 0.9 15.1 Source soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_I3_LC.O
Info: 1.8 16.8 Net soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_I3[1] budget 1.511000 ns (22,16) -> (21,16)
Info: Sink $nextpnr_ICESTORM_LC_212.I1
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:231.13-244.3
Info: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154.17-154.58
Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:29.22-29.23
Info: 0.7 17.5 Source $nextpnr_ICESTORM_LC_212.COUT
Info: 0.0 17.5 Net $nextpnr_ICESTORM_LC_212$O budget 0.000000 ns (21,16) -> (21,16)
Info: Sink soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_O_1_LC.CIN
Info: 0.3 17.8 Source soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_O_1_LC.COUT
Info: 0.0 17.8 Net soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_I3[2] budget 0.000000 ns (21,16) -> (21,16)
Info: Sink soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_O_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:231.13-244.3
Info: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154.17-154.58
Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 18.0 Source soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_O_SB_LUT4_O_LC.COUT
Info: 0.7 18.7 Net soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_I3[3] budget 0.660000 ns (21,16) -> (21,16)
Info: Sink soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_LC.I3
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:231.13-244.3
Info: /build/gateware/cores/no2usb//rtl/usb_tx_pkt.v:154.17-154.58
Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.8 19.5 Setup soc_I.usb_I.tx_pkt_I.shift_last_bit_SB_LUT4_I1_LC.I3
Info: 7.6 ns logic, 11.9 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge clk_sys':
Info: curr total
Info: 0.0 0.0 Source spi_mux_I.iob_I[2].D_IN_0
Info: 8.2 8.2 Net flash_miso_i budget 31.052000 ns (23,0) -> (0,0)
Info: Sink soc_I.spi_I.spi_I.MI
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:374.4-400.3
Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:32.14-32.24
Info: 1.5 9.7 Setup soc_I.spi_I.spi_I.MI
Info: 1.5 ns logic, 8.2 ns routing
Info: Critical path report for cross-domain path 'posedge clk_48m' -> '<async>':
Info: curr total
Info: 1.4 1.4 Source soc_I.usb_I.pad_pu_SB_DFFSR_Q_DFFLC.O
Info: 3.6 5.0 Net usb_pu$SB_IO_OUT budget 81.943001 ns (15,7) -> (17,0)
Info: Sink usb_pu$sb_io.D_OUT_0
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:39.14-39.20
Info: 1.4 ns logic, 3.6 ns routing
Info: Critical path report for cross-domain path 'posedge clk_48m' -> 'posedge clk_sys':
Info: curr total
Info: 1.4 1.4 Source soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_15_LC.O
Info: 3.1 4.4 Net soc_I.wb_48m_xclk_I.m_rdata_i[0] budget 29.927999 ns (15,13) -> (15,8)
Info: Sink soc_I.wb_48m_xclk_I.s_rdata_SB_DFFSR_Q_15_DFFLC.I0
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/cores/no2misc//rtl/xclk_wb.v:53.15-53.24
Info: /build/gateware/common/rtl/soc_base.v:400.4-416.3
Info: 1.2 5.7 Setup soc_I.wb_48m_xclk_I.s_rdata_SB_DFFSR_Q_15_DFFLC.I0
Info: 2.6 ns logic, 3.1 ns routing
Info: Critical path report for cross-domain path 'posedge clk_sys' -> '<async>':
Info: curr total
Info: 1.5 1.5 Source soc_I.spi_I.spi_I.SCKO
Info: 8.3 9.8 Net flash_clk_o budget 40.313999 ns (0,0) -> (22,1)
Info: Sink spi_mux_I.sio_clk_o_SB_LUT4_O_LC.I2
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:374.4-400.3
Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:37.14-37.23
Info: 1.2 11.0 Source spi_mux_I.sio_clk_o_SB_LUT4_O_LC.O
Info: 4.4 15.4 Net spi_mux_I.sio_clk_o budget 38.433998 ns (22,1) -> (24,0)
Info: Sink spi_mux_I.iob_I[1].D_OUT_0
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:374.4-400.3
Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:89.7-89.16
Info: 2.7 ns logic, 12.7 ns routing
Info: Critical path report for cross-domain path 'posedge clk_sys' -> 'posedge clk_48m':
Info: curr total
Info: 1.4 1.4 Source soc_I.cpu_I.mem_la_addr_SB_LUT4_O_8_LC.O
Info: 3.6 5.0 Net wb_addr[11] budget 5.238000 ns (10,16) -> (15,14)
Info: Sink soc_I.wb_48m_xclk_I.m_cyc_i_SB_LUT4_I3_LC.I1
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:91.18-91.25
Info: 1.2 6.2 Source soc_I.wb_48m_xclk_I.m_cyc_i_SB_LUT4_I3_LC.O
Info: 3.0 9.2 Net soc_I.usb_I.csr_bus_req_SB_DFF_Q_D budget 3.731000 ns (15,14) -> (15,10)
Info: Sink soc_I.usb_I.csr_bus_clear_SB_LUT4_O_LC.I3
Info: Defined in:
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info: 0.9 10.0 Source soc_I.usb_I.csr_bus_clear_SB_LUT4_O_LC.O
Info: 3.0 13.0 Net soc_I.usb_I.csr_bus_clear budget 4.123000 ns (15,10) -> (16,13)
Info: Sink soc_I.usb_I.evt_rd_ack_SB_DFFSR_Q_D_SB_LUT4_O_LC.I0
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:151.7-151.20
Info: /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info: 1.2 14.2 Setup soc_I.usb_I.evt_rd_ack_SB_DFFSR_Q_D_SB_LUT4_O_LC.I0
Info: 4.7 ns logic, 9.5 ns routing
Info: Max frequency for clock 'clk_sys': 31.82 MHz (PASS at 30.72 MHz)
Info: Max frequency for clock 'clk_48m': 51.20 MHz (PASS at 48.00 MHz)
Info: Max delay <async> -> posedge clk_sys: 9.74 ns
Info: Max delay posedge clk_48m -> <async> : 4.99 ns
Info: Max delay posedge clk_48m -> posedge clk_sys: 5.68 ns
Info: Max delay posedge clk_sys -> <async> : 15.43 ns
Info: Max delay posedge clk_sys -> posedge clk_48m: 14.23 ns
Info: Slack histogram:
Info: legend: * represents 54 endpoint(s)
Info: + represents [1,54) endpoint(s)
Info: [ 1123, 5076) |*+
Info: [ 5076, 9029) |****+
Info: [ 9029, 12982) |**********+
Info: [ 12982, 16935) |****************************+
Info: [ 16935, 20888) |****************+
Info: [ 20888, 24841) |******************************************+
Info: [ 24841, 28794) |************************************************************
Info: [ 28794, 32747) |**+
Info: [ 32747, 36700) |
Info: [ 36700, 40653) |
Info: [ 40653, 44606) |
Info: [ 44606, 48559) |
Info: [ 48559, 52512) |
Info: [ 52512, 56465) |
Info: [ 56465, 60418) |
Info: [ 60418, 64371) |
Info: [ 64371, 68324) |+
Info: [ 68324, 72277) |+
Info: [ 72277, 76230) |+
Info: [ 76230, 80183) |+
4 warnings, 0 errors
icepack -s /build/gateware/icE1usb/build-tmp/icE1usb.asc /build/gateware/icE1usb/build-tmp/icE1usb.bin
make: Leaving directory '/build/gateware/icE1usb'
Finished: SUCCESS
![[Jenkins]](/jenkins/static/342c126a/images/svgs/logo.svg){kind=logo}
