Skipping 2,170 KB.. Full Log

    Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581:
      Old ports: A={ 3'000 $auto$wreduce.cc:454:run$24932 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.rd_empty 7'0000000 $auto$wreduce.cc:454:run$24932 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.stage[1].l_valid 8'00000000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.data[1] }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y
      New ports: A={ 1'0 $auto$wreduce.cc:454:run$24932 [12] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.rd_empty $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.stage[4].l_valid $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_in_I.rd_empty 6'000000 $auto$wreduce.cc:454:run$24932 [0] }, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.stage[1].l_valid 5'00000 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.bd_tx_out_I.data[1] }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [15] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [12:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [6:0] }
      New connections: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [14:13] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [7] } = 3'000
    Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4555:
      Old ports: A=5'00000, B=5'11001, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4555_Y
      New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4555_Y [0]
      New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4555_Y [4:1] = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4555_Y [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:167$4555_Y [0] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4556:
      Old ports: A=5'00000, B=5'11001, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4556_Y
      New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4556_Y [0]
      New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4556_Y [4:1] = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4556_Y [0] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_tx.v:168$4556_Y [0] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720:
      Old ports: A=8'00011011, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$shiftx$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:0$222_Y 1'1 $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.alarm 5'11111 }, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y
      New ports: A=3'000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$shiftx$/build/gateware/cores/no2e1//rtl/e1_tx_framer.v:0$222_Y $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.alarm 1'1 }, Y={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [7] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [5] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [2] }
      New connections: { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [6] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [4:3] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [1:0] } = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procmux$15720_Y [2] 4'1111 }
    Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.\crc_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_crc4.v:36$12:
      Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [1:0]
      New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [0]
      New connections: $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [1] = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.crc_I.state_upd_mux [0]
    Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_buf_I.$procmux$12431:
      Old ports: A=2'00, B=2'10, Y=\soc_I.e1_buf_I.t_nxt_chan
      New ports: A=1'0, B=1'1, Y=\soc_I.e1_buf_I.t_nxt_chan [1]
      New connections: \soc_I.e1_buf_I.t_nxt_chan [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:115$5010:
      Old ports: A=2'10, B=2'00, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5696_Y
      New ports: A=1'1, B=1'0, Y=$flatten\soc_I.\iobuf_I.\dma_I.$procmux$5696_Y [1]
      New connections: $flatten\soc_I.\iobuf_I.\dma_I.$procmux$5696_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\dma_I.$ternary$/build/gateware/common/rtl/wb_dma.v:205$5060:
      Old ports: A=16'0000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir 1'0 \soc_I.iobuf_I.dma_I.len }, Y=\soc_I.iobuf_I.wb_rdata_dma [15:0]
      New ports: A=15'000000000000000, B={ \soc_I.iobuf_I.dma_I.state [1] \soc_I.iobuf_I.dma_I.dir \soc_I.iobuf_I.dma_I.len }, Y={ \soc_I.iobuf_I.wb_rdata_dma [15:14] \soc_I.iobuf_I.wb_rdata_dma [12:0] }
      New connections: \soc_I.iobuf_I.wb_rdata_dma [13] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128:
      Old ports: A=0, B={ \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte \soc_I.e1_buf_I.wb_wdata_byte }, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128_Y
      New ports: A=8'00000000, B=\soc_I.e1_buf_I.wb_wdata_byte, Y=$flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128_Y [7:0]
      New connections: $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128_Y [31:8] = { $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128_Y [7:0] $flatten\soc_I.\iobuf_I.\spram_arb_I.$ternary$/build/gateware/common/rtl/wb_arbiter.v:75$5128_Y [7:0] }
    Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$procmux$12286:
      Old ports: A=2'00, B=2'11, Y=$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0]
      New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0]
      New connections: $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [1] = $flatten\soc_I.\uart_I.\uart_rx_I.\gf_I.$2\cnt_move[1:0] [0]
    Consolidated identical input bits for $mux cell $flatten\soc_I.\uart_I.\uart_tx_I.$procmux$12441:
      Old ports: A={ 1'1 \soc_I.uart_I.uart_tx_I.shift [9:1] }, B={ 1'1 \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0]
      New ports: A=\soc_I.uart_I.uart_tx_I.shift [9:1], B={ \soc_I.uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [8:0]
      New connections: $flatten\soc_I.\uart_I.\uart_tx_I.$0\shift[9:0] [9] = 1'1
    Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4947:
      Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux
      New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0]
      New connections: \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.rx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\rx_pkt_I.\crc_5_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4960:
      Old ports: A=3'000, B=3'101, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:0]
      New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0]
      New connections: \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [2:1] = { \soc_I.usb_I.rx_pkt_I.crc_5_I.state_upd_mux [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11887:
      Old ports: A=3'000, B=3'110, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [2:0]
      New ports: A=1'0, B=1'1, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [1]
      New connections: { $flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [2] $flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [0] } = { $flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [1] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11890:
      Old ports: A={ 1'0 $flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [2:0] }, B=4'0100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y
      New ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y [2:0]
      New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_trans.v:340$1445:
      Old ports: A={ 8'00000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup 2'00 \soc_I.usb_I.trans_I.xfer_length }, Y=\soc_I.usb_I.ep_status_I.p_din_0
      New ports: A={ 6'000000 \soc_I.usb_I.trans_I.ep_data_toggle \soc_I.usb_I.trans_I.ep_bd_idx_nxt \soc_I.usb_I.trans_I.ep_bd_ctrl \soc_I.usb_I.trans_I.ep_bd_dual 1'0 \soc_I.usb_I.trans_I.ep_type }, B={ \soc_I.usb_I.trans_I.bd_state \soc_I.usb_I.trans_I.trans_is_setup \soc_I.usb_I.trans_I.xfer_length }, Y={ \soc_I.usb_I.ep_status_I.p_din_0 [15:12] \soc_I.usb_I.ep_status_I.p_din_0 [9:0] }
      New connections: \soc_I.usb_I.ep_status_I.p_din_0 [11:10] = 2'00
    Consolidated identical input bits for $pmux cell $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11838:
      Old ports: A=3'000, B=6'110111, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11838_Y
      New ports: A=2'00, B=4'1011, Y=$flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11838_Y [1:0]
      New connections: $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11838_Y [2] = $flatten\soc_I.\usb_I.\tx_ll_I.$procmux$11838_Y [1]
    Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\tx_pkt_I.\crc_16_I.$ternary$/build/gateware/cores/no2usb//rtl/usb_crc.v:37$4947:
      Old ports: A=16'0000000000000000, B=16'1000000000000101, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux
      New ports: A=1'0, B=1'1, Y=\soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0]
      New connections: \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [15:1] = { \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 12'000000000000 \soc_I.usb_I.tx_pkt_I.crc_16_I.state_upd_mux [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\spi_mux_I.$ternary$/build/gateware/icE1usb/rtl/sr_btn_if.v:144$3201:
      Old ports: A=3'010, B=3'100, Y=$auto$wreduce.cc:454:run$24963 [2:0]
      New ports: A=2'01, B=2'10, Y=$auto$wreduce.cc:454:run$24963 [2:1]
      New connections: $auto$wreduce.cc:454:run$24963 [0] = 1'0
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\misc_I.\dfu_I.\btn_flt_I.$procmux$5637:
      Old ports: A=$flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0], B=4'0001, Y=\misc_I.dfu_I.btn_flt_I.cnt_move
      New ports: A={ $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] $flatten\misc_I.\dfu_I.\btn_flt_I.$2\cnt_move[3:0] [0] }, B=2'01, Y=\misc_I.dfu_I.btn_flt_I.cnt_move [1:0]
      New connections: \misc_I.dfu_I.btn_flt_I.cnt_move [3:2] = { \misc_I.dfu_I.btn_flt_I.cnt_move [1] \misc_I.dfu_I.btn_flt_I.cnt_move [1] }
    Consolidated identical input bits for $mux cell $flatten\soc_I.\cpu_I.$procmux$12910:
      Old ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 2'00 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4103_Y, Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$25091 [1:0] }
      New ports: A={ \soc_I.cpu_I.reg_next_pc [31:2] 1'0 }, B=$flatten\soc_I.\cpu_I.$ternary$/build/gateware/common/rtl/picorv32.v:1479$4103_Y [31:1], Y={ $flatten\soc_I.\cpu_I.$3\current_pc[31:0] [31:2] $auto$alumacc.cc:501:replace_alu$25091 [1] }
      New connections: $auto$alumacc.cc:501:replace_alu$25091 [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4622:
      Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4621_Y, Y=\soc_I.e1_I.bus_rdata_rx[0]
      New ports: A=15'000000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4621_Y [15:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_rx.v:158$4621_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_rx[0] [15:8] \soc_I.e1_I.bus_rdata_rx[0] [6:0] }
      New connections: \soc_I.e1_I.bus_rdata_rx[0] [7] = 1'0
    Consolidated identical input bits for $mux cell $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4582:
      Old ports: A=16'0000000000000000, B=$flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y, Y=\soc_I.e1_I.bus_rdata_tx[0]
      New ports: A=13'0000000000000, B={ $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [15] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [12:8] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.$ternary$/build/gateware/cores/no2e1//rtl/e1_wb_tx.v:167$4581_Y [6:0] }, Y={ \soc_I.e1_I.bus_rdata_tx[0] [15] \soc_I.e1_I.bus_rdata_tx[0] [12:8] \soc_I.e1_I.bus_rdata_tx[0] [6:0] }
      New connections: { \soc_I.e1_I.bus_rdata_tx[0] [14:13] \soc_I.e1_I.bus_rdata_tx[0] [7] } = 3'000
    Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11890:
      Old ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [2:0], B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y [2:0]
      New ports: A={ $flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [1] $flatten\soc_I.\usb_I.\trans_I.$procmux$11887_Y [1] }, B=2'10, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y [2:1]
      New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y [0] = 1'0
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\soc_I.\usb_I.\trans_I.$procmux$11893:
      Old ports: A=$flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y, B=4'1000, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y
      New ports: A={ 1'0 $flatten\soc_I.\usb_I.\trans_I.$procmux$11890_Y [2:1] }, B=3'100, Y=$flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [3:1]
      New connections: $flatten\soc_I.\usb_I.\trans_I.$procmux$11893_Y [0] = 1'0
  Optimizing cells in module \top.
Performed a total of 42 changes.

75.29.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

75.29.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\soc_I.\usb_I.\ep_status_I.$procdff$23167 ($dff) from module top (D = \soc_I.cpu_I.mem_wdata [11:10], Q = \soc_I.usb_I.ep_status_I.din_1 [11:10], rval = 2'00).
Adding SRST signal on $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.\framer_I.$procdff$23500 ($dff) from module top (D = { \soc_I.e1_buf_I.tx_data_reg[0] [4:3] \soc_I.e1_buf_I.tx_data_reg[0] [1:0] }, Q = { $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.shift_data_nxt [4:3] $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.framer_I.shift_data_nxt [1:0] }, rval = 4'1111).
Adding SRST signal on $auto$opt_dff.cc:702:run$24394 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4557_Y [2:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.pg_hi [2:1], rval = 2'00).
Adding SRST signal on $auto$opt_dff.cc:702:run$24393 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4558_Y [2:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\stx_I.tx_I.pg_lo [2:1], rval = 2'00).

75.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

75.29.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~37 debug messages>

75.29.9. Rerunning OPT passes. (Maybe there is more to do..)

75.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12397.
    dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12412.
Removed 2 multiplexer ports.
<suppressed ~185 debug messages>

75.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

75.29.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

75.29.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$opt_dff.cc:764:run$24840 ($dffe) from module top (D = $auto$wreduce.cc:454:run$24900 [2:0], Q = \i2c_I.core_I.bit_cnt [2:0], rval = 3'000).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24576 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$24576 ($dffe) from module top.
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24348 ($dffe) from module top.
Setting constant 1-bit at position 9 on $auto$opt_dff.cc:764:run$24296 ($adffe) from module top.

75.29.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 20 unused wires.
<suppressed ~2 debug messages>

75.29.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

75.29.16. Rerunning OPT passes. (Maybe there is more to do..)

75.29.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~185 debug messages>

75.29.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

75.29.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

75.29.20. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24359 ($sdff) from module top.
Adding SRST signal on $auto$opt_dff.cc:702:run$24359 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:139$5356[0].\srx_I.bd_rx_out_I.data[1] [8:7], Q = \soc_I.e1_I.wb_rdata [14:13], rval = 2'00).
Removing never-active SRST on $auto$opt_dff.cc:702:run$24354 ($sdffce) from module top.
Removing never-active SRST on $auto$opt_dff.cc:702:run$24352 ($sdffce) from module top.
Removing never-active SRST on $auto$opt_dff.cc:702:run$24350 ($sdffce) from module top.

75.29.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

75.29.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

75.29.23. Rerunning OPT passes. (Maybe there is more to do..)

75.29.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~185 debug messages>

75.29.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

75.29.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

75.29.27. Executing OPT_DFF pass (perform DFF optimizations).

75.29.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
<suppressed ~1 debug messages>

75.29.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

75.29.30. Rerunning OPT passes. (Maybe there is more to do..)

75.29.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~185 debug messages>

75.29.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

75.29.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

75.29.34. Executing OPT_DFF pass (perform DFF optimizations).

75.29.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

75.29.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

75.29.37. Finished OPT passes. (There is nothing left to do.)

75.30. Executing ICE40_WRAPCARRY pass (wrap carries).

75.31. Executing TECHMAP pass (map to technology primitives).

75.31.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

75.31.2. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.

75.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $sdffce.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $adffe.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $adff.
Using extmapper simplemap for cells of type $mux.
Using template $paramod$constmap:37b3cc4e06391b7a7ef418215dc52e2abb59f048$paramod$71443bc33ec938a4dea8c4b4bbb3a548919fd2a5\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod$constmap:f131a727070ba63172385ab8bc15babdfc05a11a$paramod$4d8c31a57f918e2cd1d0bc24d8284efd6d83f4a8\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=1\Y_WIDTH=7 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=1\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu.
Using template $paramod$constmap:98a2574d6790db88f29c592e698ccfc2583099ee$paramod$da4b7a069bab2d2cb126ab511d2c5f5d67aa4129\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=14\Y_WIDTH=14 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using template $paramod$constmap:2a578b20caa92a5095129d48a2f94bbad08a990f$paramod$5c10e52cdc159999f3945c97d8a1bfa2ca0de2dc\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=12 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=1\Y_WIDTH=13 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_xor.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=20\Y_WIDTH=20 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=16\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=5 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=6 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=8 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=6 for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_xnor.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=1\Y_WIDTH=9 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=3 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
Using template $paramod$constmap:66d421c313e4e958be776b99540ac2de3b59fdbc$paramod$9b74a473ccd678a23e1df4cc12019cbbece20051\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=31\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=30\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=16\Y_WIDTH=16 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=1\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=5 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=5 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=26\Y_WIDTH=26 for cells of type $alu.
Using template $paramod$constmap:684fca2758d270a6aba8ac07bc0dd26758fbc9a0$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx for cells of type $shiftx.
Analyzing pattern of constant bits for this cell:
  Constant input on bit 0 of port A: 1'0
  Constant input on bit 1 of port A: 1'0
  Constant input on bit 2 of port A: 1'0
  Constant input on bit 3 of port A: 1'0
  Constant input on bit 4 of port A: 1'1
  Constant input on bit 5 of port A: 1'1
  Constant input on bit 6 of port A: 1'1
  Constant input on bit 7 of port A: 1'1
  Constant input on bit 8 of port A: 1'0
  Constant input on bit 9 of port A: 1'0
  Constant input on bit 10 of port A: 1'0
  Constant input on bit 11 of port A: 1'0
  Constant input on bit 12 of port A: 1'1
  Constant input on bit 13 of port A: 1'1
  Constant input on bit 14 of port A: 1'1
  Constant input on bit 15 of port A: 1'1
Creating constmapped module `$paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx'.

75.31.141. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $procmux$36217.
    dead port 2/2 on $mux $procmux$36211.
    dead port 2/2 on $mux $procmux$36205.
    dead port 2/2 on $mux $procmux$36199.
Removed 4 multiplexer ports.
<suppressed ~4030 debug messages>

75.31.142. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx.
<suppressed ~3 debug messages>
Removed 0 unused cells and 11 unused wires.
Using template $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=7 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=13\Y_WIDTH=13 for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu.
No more expansions possible.
<suppressed ~1298 debug messages>

75.32. Executing OPT pass (performing simple optimizations).

75.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3439 debug messages>

75.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3939 debug messages>
Removed a total of 1313 cells.

75.32.3. Executing OPT_DFF pass (perform DFF optimizations).

75.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 989 unused cells and 4654 unused wires.
<suppressed ~1001 debug messages>

75.32.5. Finished fast OPT passes.

75.33. Executing ICE40_OPT pass (performing simple optimizations).

75.33.1. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24976.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24976.BB [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24985.slice[0].carry: CO=\blinker_I.tick_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24991.slice[0].carry: CO=\gps_uart_I.uart_div [1]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24991.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$24991.C [11]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24994.slice[0].carry: CO=\gps_uart_I.uart_rx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24997.slice[0].carry: CO=\gps_uart_I.uart_rx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25003.slice[0].carry: CO=\gps_uart_I.uart_rx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25009.slice[0].carry: CO=\gps_uart_I.uart_rx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25012.slice[0].carry: CO=\gps_uart_I.uart_tx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25015.slice[0].carry: CO=\gps_uart_I.uart_tx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25018.slice[0].carry: CO=\gps_uart_I.uart_tx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25024.slice[0].carry: CO=\gps_uart_I.uart_tx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25027.slice[0].carry: CO=\i2c_I.core_I.cyc_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25030.slice[0].carry: CO=\i2c_I.core_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25039.slice[0].carry: CO=\sys_mgr_I.rst_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25087.slice[0].carry: CO=\soc_I.cpu_I.reg_pc [2]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25090.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25090.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25105.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [2]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25108.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25111.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25111.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25114.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25114.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25117.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25117.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25120.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25120.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25135.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25135.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25159.slice[0].carry: CO=\soc_I.e1_buf_I.buf_tx_ts [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25162.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25162.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25165.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25165.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25171.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m0_addr_i [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25174.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m1_addr_i [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25177.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.len [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25180.slice[0].carry: CO=\soc_I.uart_I.uart_div [1]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25180.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$25180.C [11]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25183.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25186.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25192.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25198.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25201.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25204.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25207.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25213.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25225.slice[0].carry: CO=\soc_I.usb_I.rx_pkt_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25225.slice[3].carry: CO=$auto$alumacc.cc:485:replace_alu$25225.C [3]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25228.slice[0].carry: CO=\soc_I.usb_I.trans_I.mc_pc [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25243.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25243.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25243.slice[2].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25246.slice[0].carry: CO=\soc_I.usb_I.tx_ll_I.bs_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25249.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25249.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25252.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25252.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25255.slice[0].carry: CO=\spi_mux_I.tick_cnt [0]

75.33.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~41 debug messages>

75.33.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

75.33.4. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30615 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12173.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30614 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12173.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30613 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12173.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30611 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12190.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [3], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30610 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12190.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30609 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12190.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35219 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [31], Q = \misc_I.wb_rdata [31], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35218 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [30], Q = \misc_I.wb_rdata [30], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35217 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [29], Q = \misc_I.wb_rdata [29], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35216 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [28], Q = \misc_I.wb_rdata [28], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35215 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [27], Q = \misc_I.wb_rdata [27], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35214 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [26], Q = \misc_I.wb_rdata [26], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35213 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [25], Q = \misc_I.wb_rdata [25], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35212 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [24], Q = \misc_I.wb_rdata [24], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35211 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [23], Q = \misc_I.wb_rdata [23], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35210 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [22], Q = \misc_I.wb_rdata [22], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35209 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [21], Q = \misc_I.wb_rdata [21], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35208 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [20], Q = \misc_I.wb_rdata [20], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35203 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [15], Q = \misc_I.wb_rdata [15], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35202 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [14], Q = \misc_I.wb_rdata [14], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35201 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [13], Q = \misc_I.wb_rdata [13], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35200 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [12], Q = \misc_I.wb_rdata [12], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35195 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [7], Q = \misc_I.wb_rdata [7], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35194 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [6], Q = \misc_I.wb_rdata [6], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35193 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [5], Q = \misc_I.wb_rdata [5], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35192 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11702.Y_B [4], Q = \misc_I.wb_rdata [4], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$31223 ($_SDFF_PP0_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12216.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.samp_cnt [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34812 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [31], Q = \soc_I.cpu_I.decoded_imm [31], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34811 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [30], Q = \soc_I.cpu_I.decoded_imm [30], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34810 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [29], Q = \soc_I.cpu_I.decoded_imm [29], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34809 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [28], Q = \soc_I.cpu_I.decoded_imm [28], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34808 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [27], Q = \soc_I.cpu_I.decoded_imm [27], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34807 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [26], Q = \soc_I.cpu_I.decoded_imm [26], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34806 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [25], Q = \soc_I.cpu_I.decoded_imm [25], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34805 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [24], Q = \soc_I.cpu_I.decoded_imm [24], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34804 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [23], Q = \soc_I.cpu_I.decoded_imm [23], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34803 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [22], Q = \soc_I.cpu_I.decoded_imm [22], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34802 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [21], Q = \soc_I.cpu_I.decoded_imm [21], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34801 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [20], Q = \soc_I.cpu_I.decoded_imm [20], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34800 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [19], Q = \soc_I.cpu_I.decoded_imm [19], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34799 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [18], Q = \soc_I.cpu_I.decoded_imm [18], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34798 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [17], Q = \soc_I.cpu_I.decoded_imm [17], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34797 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [16], Q = \soc_I.cpu_I.decoded_imm [16], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34796 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [15], Q = \soc_I.cpu_I.decoded_imm [15], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34795 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [14], Q = \soc_I.cpu_I.decoded_imm [14], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34794 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [13], Q = \soc_I.cpu_I.decoded_imm [13], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34793 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [12], Q = \soc_I.cpu_I.decoded_imm [12], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34792 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [11], Q = \soc_I.cpu_I.decoded_imm [11], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34791 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [10], Q = \soc_I.cpu_I.decoded_imm [10], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34790 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [9], Q = \soc_I.cpu_I.decoded_imm [9], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34789 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [8], Q = \soc_I.cpu_I.decoded_imm [8], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34788 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [7], Q = \soc_I.cpu_I.decoded_imm [7], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34787 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [6], Q = \soc_I.cpu_I.decoded_imm [6], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34786 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [5], Q = \soc_I.cpu_I.decoded_imm [5], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34785 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [4], Q = \soc_I.cpu_I.decoded_imm [4], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34784 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [3], Q = \soc_I.cpu_I.decoded_imm [3], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34783 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [2], Q = \soc_I.cpu_I.decoded_imm [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34782 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14355.Y_B [1], Q = \soc_I.cpu_I.decoded_imm [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30605 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12205.B_AND_S [2], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30604 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12205.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30603 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12205.Y_B [0], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [0], rval = 1'0).

75.33.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 62 unused cells and 32 unused wires.
<suppressed ~63 debug messages>

75.33.6. Rerunning OPT passes. (Removed registers in this run.)

75.33.7. Running ICE40 specific optimizations.

75.33.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

75.33.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~132 debug messages>
Removed a total of 44 cells.

75.33.10. Executing OPT_DFF pass (perform DFF optimizations).

75.33.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 44 unused wires.
<suppressed ~1 debug messages>

75.33.12. Rerunning OPT passes. (Removed registers in this run.)

75.33.13. Running ICE40 specific optimizations.

75.33.14. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

75.33.15. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

75.33.16. Executing OPT_DFF pass (perform DFF optimizations).

75.33.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

75.33.18. Finished OPT passes. (There is nothing left to do.)

75.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

75.35. Executing TECHMAP pass (map to technology primitives).

75.35.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

75.35.2. Continuing TECHMAP pass.
Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_.
Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_.
Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_DFF_P_ for cells of type $_DFF_P_.
Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_.
Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_.
Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_.
Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
No more expansions possible.
<suppressed ~2235 debug messages>

75.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

75.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping top.$auto$alumacc.cc:485:replace_alu$24985.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$24991.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$24991.slice[11].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$24994.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$24997.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25003.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25009.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25012.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25015.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25018.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25024.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25027.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25030.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25039.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25087.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25090.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25105.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25108.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25111.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25114.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25117.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25120.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25135.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25159.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25162.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25165.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25171.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25174.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25177.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25180.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25180.slice[11].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25183.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25186.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25192.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25198.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25201.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25204.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25207.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25213.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25225.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25225.slice[3].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25228.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25243.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25243.slice[2].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25246.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25249.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25252.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25255.slice[0].carry ($lut).

75.38. Executing ICE40_OPT pass (performing simple optimizations).

75.38.1. Running ICE40 specific optimizations.

75.38.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~1263 debug messages>

75.38.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~1359 debug messages>
Removed a total of 453 cells.

75.38.4. Executing OPT_DFF pass (perform DFF optimizations).

75.38.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 12111 unused wires.
<suppressed ~1 debug messages>

75.38.6. Rerunning OPT passes. (Removed registers in this run.)

75.38.7. Running ICE40 specific optimizations.

75.38.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

75.38.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

75.38.10. Executing OPT_DFF pass (perform DFF optimizations).

75.38.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

75.38.12. Finished OPT passes. (There is nothing left to do.)

75.39. Executing TECHMAP pass (map to technology primitives).

75.39.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

75.39.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

75.40. Executing ABC pass (technology mapping using ABC).

75.40.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 6543 gates and 9005 wires to a netlist network with 2460 inputs and 1837 outputs.

75.40.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
ABC: + strash 
ABC: + ifraig 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + strash 
ABC: + dch -f 
ABC: + if 
ABC: + mfs2 
ABC: + lutpack -S 1 
ABC: + dress 
ABC: Total number of equiv classes                =    2230.
ABC: Participating nodes from both networks       =    4701.
ABC: Participating nodes from the first network   =    2247. (  79.01 % of nodes)
ABC: Participating nodes from the second network  =    2454. (  86.29 % of nodes)
ABC: Node pairs (any polarity)                    =    2247. (  79.01 % of names can be moved)
ABC: Node pairs (same polarity)                   =    1991. (  70.01 % of names can be moved)
ABC: Total runtime =     0.08 sec
ABC: + write_blif <abc-temp-dir>/output.blif 

75.40.1.2. Re-integrating ABC results.
ABC RESULTS:              $lut cells:     2843
ABC RESULTS:        internal signals:     4708
ABC RESULTS:           input signals:     2460
ABC RESULTS:          output signals:     1837
Removing temp directory.

75.41. Executing ICE40_WRAPCARRY pass (wrap carries).

75.42. Executing TECHMAP pass (map to technology primitives).

75.42.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

75.42.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~22 debug messages>
Removed 140 unused cells and 5952 unused wires.

75.43. Executing OPT_LUT pass (optimize LUTs).
Discovering LUTs.
Number of LUTs:     3520
  1-LUT              149
  2-LUT              948
  3-LUT             1252
  4-LUT             1171

Eliminating LUTs.
Number of LUTs:     3516
  1-LUT              149
  2-LUT              948
  3-LUT             1248
  4-LUT             1171

Combining LUTs.
Number of LUTs:     3261
  1-LUT              148
  2-LUT              629
  3-LUT             1133
  4-LUT             1351

Eliminated 4 LUTs.
Combined 255 LUTs.
<suppressed ~18947 debug messages>

75.44. Executing TECHMAP pass (map to technology primitives).

75.44.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

75.44.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000011101110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001001100111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11101111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101111111110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101110011001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100010000001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011101111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101110111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100010011110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001101011100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101110001010011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000101110111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010001111001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111001111110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10110010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011101100110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000110011001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111011111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011101110110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100111110100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100011101110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010101011000011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010101010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001010111111100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110010100011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100010111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110101100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000011111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011101100001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000000011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111110001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000100011110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111000001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001110111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001011001101001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011011100110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101010111000011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000000101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011100100001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111110000001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011110011111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101011111100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000110000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001010001000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111110110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110110000110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101010100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010101111101010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00011000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11100111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111110011111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100111000001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10111100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01000010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111011101110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0010001010001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010100000101010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000100000001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0010100000101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000101000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010001000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110101110111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001110010011100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010000000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100010100110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100001101100110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011110011001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0010000100010010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111001011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111011101000000 for cells of type $lut.
No more expansions possible.
<suppressed ~6189 debug messages>
Removed 0 unused cells and 6938 unused wires.

75.45. Executing AUTONAME pass.
Renamed 201871 objects in module top (129 iterations).
<suppressed ~8253 debug messages>

75.46. Executing HIERARCHY pass (managing design hierarchy).

75.46.1. Analyzing design hierarchy..
Top module:  \top

75.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

75.47. Printing statistics.

=== top ===

   Number of wires:               3770
   Number of wire bits:          18527
   Number of public wires:        3770
   Number of public wire bits:   18527
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               6294
     SB_CARRY                      719
     SB_DFF                        313
     SB_DFFE                       575
     SB_DFFER                      430
     SB_DFFES                       44
     SB_DFFESR                     220
     SB_DFFESS                      45
     SB_DFFR                       131
     SB_DFFS                        49
     SB_DFFSR                      374
     SB_DFFSS                       31
     SB_GB                           2
     SB_GB_IO                        1
     SB_IO                          25
     SB_LEDDA_IP                     1
     SB_LUT4                      3300
     SB_MAC16                        6
     SB_PLL40_CORE                   1
     SB_RAM40_4K                    16
     SB_RAM40_4KNR                   4
     SB_RGBA_DRV                     1
     SB_SPI                          1
     SB_SPRAM256KA                   4
     SB_WARMBOOT                     1

75.48. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.

75.49. Executing JSON backend.

Warnings: 9 unique messages, 17 total
End of script. Logfile hash: e10607c8fd, CPU: user 17.20s system 0.12s, MEM: 321.74 MB peak
Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os)
Time spent: 21% 38x opt_expr (3 sec), 16% 31x opt_clean (3 sec), ...
nextpnr-ice40 --pre-pack data/clocks.py --pre-pack data/opt.py --seed 15 --no-promote-globals --timing-allow-fail  \
	--up5k --package sg48  \
	-l /build/gateware/icE1usb/build-tmp/icE1usb.pnr.rpt \
	--json /build/gateware/icE1usb/build-tmp/icE1usb.json \
	--pcf /build/gateware/icE1usb/data/top-ice1usb.pcf \
	--asc /build/gateware/icE1usb/build-tmp/icE1usb.asc
Info: constrained 'e1A_rx_hi_p' to bel 'X8/Y31/io0'
Warning: unmatched constraint 'e1A_rx_hi_n' (on line 3)
Info: constrained 'e1A_rx_lo_p' to bel 'X16/Y31/io0'
Warning: unmatched constraint 'e1A_rx_lo_n' (on line 5)
Info: constrained 'e1A_tx_hi' to bel 'X9/Y31/io0'
Info: constrained 'e1A_tx_lo' to bel 'X9/Y31/io1'
Info: constrained 'e1B_rx_hi_p' to bel 'X19/Y31/io0'
Warning: unmatched constraint 'e1B_rx_hi_n' (on line 10)
Info: constrained 'e1B_rx_lo_p' to bel 'X18/Y31/io0'
Warning: unmatched constraint 'e1B_rx_lo_n' (on line 12)
Info: constrained 'e1B_tx_hi' to bel 'X13/Y31/io1'
Info: constrained 'e1B_tx_lo' to bel 'X13/Y31/io0'
Info: constrained 'e1_rx_bias[0]' to bel 'X17/Y31/io0'
Info: constrained 'e1_rx_bias[1]' to bel 'X12/Y31/io1'
Info: constrained 'usb_dp' to bel 'X16/Y0/io0'
Info: constrained 'usb_dn' to bel 'X15/Y0/io0'
Info: constrained 'usb_pu' to bel 'X17/Y0/io0'
Info: constrained 'flash_mosi' to bel 'X23/Y0/io0'
Info: constrained 'flash_miso' to bel 'X23/Y0/io1'
Info: constrained 'flash_clk' to bel 'X24/Y0/io0'
Info: constrained 'flash_cs_n' to bel 'X24/Y0/io1'
Info: constrained 'e1_led_rclk' to bel 'X22/Y0/io1'
Info: constrained 'gps_reset_n' to bel 'X13/Y0/io1'
Info: constrained 'gps_rx' to bel 'X6/Y0/io0'
Info: constrained 'gps_tx' to bel 'X5/Y0/io0'
Info: constrained 'gps_pps' to bel 'X8/Y0/io0'
Info: constrained 'i2c_sda' to bel 'X9/Y0/io1'
Info: constrained 'i2c_scl' to bel 'X9/Y0/io0'
Info: constrained 'gpio[0]' to bel 'X19/Y0/io0'
Info: constrained 'gpio[1]' to bel 'X19/Y0/io1'
Info: constrained 'gpio[2]' to bel 'X21/Y0/io1'
Info: constrained 'clk_in' to bel 'X6/Y0/io1'
Info: constrained 'clk_tune_hi' to bel 'X7/Y0/io0'
Info: constrained 'clk_tune_lo' to bel 'X7/Y0/io1'
Info: constrained 'dbg_rx' to bel 'X18/Y0/io1'
Info: constrained 'dbg_tx' to bel 'X18/Y0/io0'
Info: constrained 'rgb[0]' to bel 'X4/Y31/io0'
Info: constrained 'rgb[1]' to bel 'X5/Y31/io0'
Info: constrained 'rgb[2]' to bel 'X6/Y31/io0'
Info: constraining clock net 'clk_sys' to 30.72 MHz
Info: constraining clock net 'clk_48m' to 48.00 MHz
1 247 ControlSet(rs=None, ena=None, clk='clk_sys')
      5 ControlSet(rs='wb_ack[1]', ena=None, clk='clk_sys')
--------------
0 248 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='spi_mux_I.srio_dat_o_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
1 253 ControlSet(rs=None, ena=None, clk='clk_sys')
      5 ControlSet(rs='soc_I.wb_ack[1]', ena=None, clk='clk_sys')
--------------
0 72 ControlSet(rs=None, ena=None, clk='clk_48m')
      1 ControlSet(rs='soc_I.usb_I.tx_ll_I.lvl_prev_SB_DFFSS_Q_S', ena=None, clk='clk_48m')
--------------
0 12 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m')
      1 ControlSet(rs='soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O[1]', ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m')
1 73 ControlSet(rs=None, ena=None, clk='clk_48m')
      1 ControlSet(rs='soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O[1]', ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m')
--------------
2 74 ControlSet(rs=None, ena=None, clk='clk_48m')
      2 ControlSet(rs='soc_I.usb_I.rx_pkt_I.state[0]', ena='soc_I.usb_I.rx_pkt_I.crc5_ok_SB_DFFESR_Q_E', clk='clk_48m')
--------------
3 79 ControlSet(rs=None, ena=None, clk='clk_48m')
      5 ControlSet(rs='soc_I.usb_I.rx_pkt_I.state[0]', ena='soc_I.usb_I.rx_pkt_I.bit_cnt_SB_DFFESR_Q_E', clk='clk_48m')
--------------
0 81 ControlSet(rs=None, ena=None, clk='clk_48m')
      2 ControlSet(rs='soc_I.usb_I.rx_ll_I.samp_sync', ena=None, clk='clk_48m')
--------------
0 82 ControlSet(rs=None, ena=None, clk='clk_48m')
      1 ControlSet(rs='soc_I.usb_I.rx_ll_I.samp_cnt_SB_DFFSR_Q_R', ena=None, clk='clk_48m')
--------------
0 83 ControlSet(rs=None, ena=None, clk='clk_48m')
      1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_LUT4_I2_O[1]', ena='soc_I.usb_I.rx_pkt_I.crc_in_first_SB_DFFESS_Q_E', clk='clk_48m')
--------------
5 15 ControlSet(rs=None, ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
      3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
      3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_eop_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
      1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_rep_state_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
      3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sym_same_0_SB_LUT4_I3_1_O', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
      1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sym_se_0', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
3 86 ControlSet(rs=None, ena=None, clk='clk_48m')
      3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
--------------
0 85 ControlSet(rs=None, ena=None, clk='clk_48m')
      2 ControlSet(rs='soc_I.usb_I.eps_write_0', ena=None, clk='clk_48m')
--------------
0 88 ControlSet(rs=None, ena=None, clk='clk_48m')
      3 ControlSet(rs='soc_I.usb_I.eps_bus_clear', ena=None, clk='clk_48m')
--------------
0 93 ControlSet(rs=None, ena=None, clk='clk_48m')
      5 ControlSet(rs='soc_I.usb_I.csr_bus_clear', ena=None, clk='clk_48m')
--------------
0 260 ControlSet(rs=None, ena=None, clk='clk_sys')
      7 ControlSet(rs='soc_I.uart_I.ub_rdata_SB_DFFSR_Q_9_R', ena=None, clk='clk_sys')
--------------
0 261 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', ena=None, clk='clk_sys')
--------------
4 266 ControlSet(rs=None, ena=None, clk='clk_sys')
      5 ControlSet(rs='soc_I.uart_I.uart_tx_I.bit_cnt_SB_DFFESS_Q_S', ena='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', clk='clk_sys')
--------------
4 271 ControlSet(rs=None, ena=None, clk='clk_sys')
      5 ControlSet(rs='soc_I.uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_S', ena='soc_I.uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_E', clk='clk_sys')
--------------
1 272 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_store_SB_DFFESS_Q_E', clk='clk_sys')
--------------
5 277 ControlSet(rs=None, ena=None, clk='clk_sys')
      5 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_stalu_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O', clk='clk_sys')
--------------
0 278 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_stalu_SB_DFFESR_Q_E', clk='clk_sys')
--------------
2 280 ControlSet(rs=None, ena=None, clk='clk_sys')
      2 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_is_lb_SB_DFFESR_Q_E', clk='clk_sys')
--------------
1 281 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_branch_SB_DFFESR_Q_E[2]', clk='clk_sys')
--------------
1 282 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 13 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys')
      1 ControlSet(rs='soc_I.iobuf_I.dma_I.len_ld', ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys')
1 283 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.iobuf_I.dma_I.len_ld', ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys')
--------------
0 284 ControlSet(rs=None, ena=None, clk='clk_sys')
      2 ControlSet(rs='soc_I.e1_buf_I.buf_rx_frame_SB_LUT4_I0_I1_SB_LUT4_O_I2_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_DFFSR_D_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys')
--------------
0 286 ControlSet(rs=None, ena=None, clk='clk_sys')
      2 ControlSet(rs='soc_I.e1_I.wb_rdata_SB_DFFSR_Q_14_R', ena=None, clk='clk_sys')
--------------
0 288 ControlSet(rs=None, ena=None, clk='clk_sys')
      2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_O_SB_DFFSR_D_R_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFSR_R_1_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys')
--------------
0 292 ControlSet(rs=None, ena=None, clk='clk_sys')
      4 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_O_SB_DFFSR_D_R_SB_LUT4_O_I3_SB_LUT4_I3_O', ena=None, clk='clk_sys')
--------------
0 294 ControlSet(rs=None, ena=None, clk='clk_sys')
      2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_O_SB_DFFSR_D_R_SB_DFFSR_R_1_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys')
--------------
0 298 ControlSet(rs=None, ena=None, clk='clk_sys')
      4 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_O_SB_DFFSR_D_R', ena=None, clk='clk_sys')
--------------
0 300 ControlSet(rs=None, ena=None, clk='clk_sys')
      2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I2_O_SB_DFFSR_D_Q_SB_LUT4_I1_1_O', ena=None, clk='clk_sys')
--------------
6 307 ControlSet(rs=None, ena=None, clk='clk_sys')
      7 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_I3[2]', ena='soc_I.e1_buf_I.buf_rx_we_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O', clk='clk_sys')
--------------
5 314 ControlSet(rs=None, ena=None, clk='clk_sys')
      7 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_I3[2]', ena='soc_I.e1_buf_I.buf_rx_we_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I2_O', clk='clk_sys')
--------------
4 319 ControlSet(rs=None, ena=None, clk='clk_sys')
      5 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_I3[2]', ena='soc_I.e1_buf_I.buf_rx_we_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 320 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_I3[2]', ena=None, clk='clk_sys')
--------------
0 324 ControlSet(rs=None, ena=None, clk='clk_sys')
      4 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_I2_1_O_SB_LUT4_O_I3_SB_LUT4_I3_1_O', ena=None, clk='clk_sys')
--------------
0 328 ControlSet(rs=None, ena=None, clk='clk_sys')
      4 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_DFF_D_Q_SB_LUT4_I3_2_O', ena=None, clk='clk_sys')
--------------
0 329 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O', ena=None, clk='clk_sys')
--------------
1 331 ControlSet(rs=None, ena=None, clk='clk_sys')
      2 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_I2[0]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_DFFSR_R_Q_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 332 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_DFFESS_Q_S[2]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_DFFESS_Q_E', clk='clk_sys')
--------------
0 333 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_DFFESS_Q_S[2]', ena=None, clk='clk_sys')
--------------
0 334 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_S[2]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_DFFESS_Q_E', clk='clk_sys')
--------------
3 19 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_buf_I.buf_tx_re_SB_LUT4_O_I3', clk='clk_sys')
      1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_I2_1_O_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_DFFER_Q_E[1]', clk='clk_sys')
      4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_LUT4_I2_O', clk='clk_sys')
--------------
1 335 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 336 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I2_O', clk='clk_sys')
--------------
0 340 ControlSet(rs=None, ena=None, clk='clk_sys')
      4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I0_SB_DFFER_Q_E_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
0 341 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.cpu_I.mem_state_SB_DFFESR_Q_R', ena='soc_I.cpu_I.mem_valid_SB_DFFESR_Q_E', clk='clk_sys')
--------------
2 343 ControlSet(rs=None, ena=None, clk='clk_sys')
      2 ControlSet(rs='soc_I.cpu_I.mem_state_SB_DFFESR_Q_R', ena='soc_I.cpu_I.mem_state_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 344 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.cpu_I.mem_do_wdata_SB_DFFESS_Q_S[0]', ena='soc_I.cpu_I.mem_do_wdata_SB_DFFESS_Q_E', clk='clk_sys')
--------------
0 345 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.cpu_I.mem_do_rinst_SB_DFFESS_Q_S[2]', ena='soc_I.cpu_I.mem_do_prefetch_SB_DFFESR_Q_E', clk='clk_sys')
--------------
1 346 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.cpu_I.mem_do_rinst_SB_DFFESS_Q_S[0]', ena='soc_I.cpu_I.mem_do_rinst_SB_DFFESS_Q_E', clk='clk_sys')
--------------
0 347 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.cpu_I.instr_sh_SB_LUT4_I2_O[2]', ena='soc_I.cpu_I.mem_do_rdata_SB_DFFESS_Q_E', clk='clk_sys')
--------------
0 348 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.cpu_I.instr_or_SB_DFFESR_Q_E', ena=None, clk='clk_sys')
--------------
0 349 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.cpu_I.decoder_pseudo_trigger_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
0 350 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='soc_I.cpu_I.alu_wait_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
1 191 ControlSet(rs='rst_sys', ena=None, clk='clk_sys')
      1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys')
      1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys')
      1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys')
      3 ControlSet(rs='rst_sys', ena='misc_I.bus_we_boot', clk='clk_sys')
      3 ControlSet(rs='rst_sys', ena='misc_I.dfu_I.wb_sel_SB_DFFER_Q_E', clk='clk_sys')
      1 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I0_SB_DFFER_Q_E', clk='clk_sys')
      7 ControlSet(rs='rst_sys', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I3_SB_DFFER_Q_E', clk='clk_sys')
      2 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.dma_I.state_SB_DFFER_Q_E', clk='clk_sys')
      3 ControlSet(rs='rst_sys', ena='soc_I.rgb_I.led_ctrl_SB_DFFER_Q_E', clk='clk_sys')
      1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys')
--------------
0 351 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_I.gf_I.state_SB_DFFESS_Q_E', clk='clk_sys')
--------------
1 352 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='rst_sys', ena='i2c_I.core_I.sda_oe_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 353 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='rst_sys', ena='i2c_I.core_I.scl_oe_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 354 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_I.gf_I.state_SB_DFFESS_Q_E', clk='clk_sys')
--------------
5 67 ControlSet(rs='rst_48m', ena=None, clk='clk_48m')
      3 ControlSet(rs='rst_48m', ena='soc_I.usb_I.tx_ll_I.state_SB_DFFER_Q_E', clk='clk_48m')
      2 ControlSet(rs='rst_48m', ena='soc_I.usb_I.tx_ll_I.br_cnt[2]', clk='clk_48m')
--------------
0 355 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='misc_I.pps_flt_I.state_SB_LUT4_I1_O[1]', ena='misc_I.pps_flt_I.state_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 356 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='misc_I.dfu_I.btn_flt_I.fall_SB_DFF_Q_D', ena='misc_I.dfu_I.btn_flt_I.state_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 363 ControlSet(rs=None, ena=None, clk='clk_sys')
      7 ControlSet(rs='misc_I.bus_we_led_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
0 368 ControlSet(rs=None, ena=None, clk='clk_sys')
      5 ControlSet(rs='i2c_I.core_I.cyc_cnt_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
2 371 ControlSet(rs=None, ena=None, clk='clk_sys')
      3 ControlSet(rs='i2c_I.core_I.bit_cnt_SB_DFFESR_Q_R[1]', ena='i2c_I.core_I.bit_last_SB_DFFE_Q_E', clk='clk_sys')
--------------
0 378 ControlSet(rs=None, ena=None, clk='clk_sys')
      7 ControlSet(rs='gps_uart_I.ub_rdata_SB_DFFSR_Q_9_R', ena=None, clk='clk_sys')
--------------
0 379 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='gps_uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', ena=None, clk='clk_sys')
--------------
4 384 ControlSet(rs=None, ena=None, clk='clk_sys')
      5 ControlSet(rs='gps_uart_I.uart_tx_I.bit_cnt_SB_DFFESS_Q_S', ena='gps_uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', clk='clk_sys')
--------------
4 389 ControlSet(rs=None, ena=None, clk='clk_sys')
      5 ControlSet(rs='gps_uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_S', ena='gps_uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_E', clk='clk_sys')
--------------
3 392 ControlSet(rs=None, ena=None, clk='clk_sys')
      3 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_DFFSR_R_Q_SB_DFFESR_Q_E', clk='clk_sys')
--------------
3 396 ControlSet(rs=None, ena=None, clk='clk_sys')
      4 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E[0]', clk='clk_sys')
--------------
0 397 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_DFFESR_Q_E', clk='clk_sys')
--------------
1 399 ControlSet(rs=None, ena=None, clk='clk_sys')
      2 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='e1A_rx_lo_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O_SB_LUT4_I2_O', clk='clk_sys')
--------------
1 401 ControlSet(rs=None, ena=None, clk='clk_sys')
      2 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O_SB_LUT4_I2_O', clk='clk_sys')
--------------
1 405 ControlSet(rs=None, ena=None, clk='clk_sys')
      4 ControlSet(rs=None, ena='tick_e1_tx[0]', clk='clk_sys')
--------------
0 95 ControlSet(rs=None, ena=None, clk='clk_48m')
      2 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_data_crc_SB_DFFE_Q_E', clk='clk_48m')
--------------
1 99 ControlSet(rs=None, ena=None, clk='clk_48m')
      4 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.mc_op_tx', clk='clk_48m')
--------------
4 103 ControlSet(rs=None, ena=None, clk='clk_48m')
      4 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.mc_op_ld', clk='clk_48m')
--------------
2 110 ControlSet(rs=None, ena=None, clk='clk_48m')
      7 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.epfw_issue_wb_SB_LUT4_I1_O[0]', clk='clk_48m')
--------------
1 116 ControlSet(rs=None, ena=None, clk='clk_48m')
      6 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.ep_bd_dual_SB_LUT4_I2_O[2]', clk='clk_48m')
--------------
3 119 ControlSet(rs=None, ena=None, clk='clk_48m')
      3 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.bd_state_SB_DFFE_Q_E', clk='clk_48m')
--------------
0 123 ControlSet(rs=None, ena=None, clk='clk_48m')
      4 ControlSet(rs=None, ena='soc_I.usb_I.rxpkt_done_ok', clk='clk_48m')
--------------
0 126 ControlSet(rs=None, ena=None, clk='clk_48m')
      3 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.token_data_SB_DFFE_Q_E[1]', clk='clk_48m')
--------------
0 406 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ld', clk='clk_sys')
--------------
0 410 ControlSet(rs=None, ena=None, clk='clk_sys')
      4 ControlSet(rs=None, ena='soc_I.e1_buf_I.buf_rx_frame_SB_LUT4_I0_I1_SB_LUT4_O_I2_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_LUT4_I0_O[0]', clk='clk_sys')
--------------
1 414 ControlSet(rs=None, ena=None, clk='clk_sys')
      4 ControlSet(rs=None, ena='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_I1', clk='clk_sys')
--------------
1 415 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs=None, ena='soc_I.cpu_I.reg_op1_SB_DFFE_Q_31_E', clk='clk_sys')
--------------
2 417 ControlSet(rs=None, ena=None, clk='clk_sys')
      2 ControlSet(rs=None, ena='soc_I.cpu_I.instr_sra_SB_LUT4_I2_O[3]', clk='clk_sys')
--------------
4 421 ControlSet(rs=None, ena=None, clk='clk_sys')
      4 ControlSet(rs=None, ena='soc_I.bridge_I.ram_rdy_SB_LUT4_I0_O[1]', clk='clk_sys')
--------------
0 423 ControlSet(rs=None, ena=None, clk='clk_sys')
      2 ControlSet(rs=None, ena='i2c_I.stb', clk='clk_sys')
--------------
1 424 ControlSet(rs=None, ena=None, clk='clk_sys')
      1 ControlSet(rs=None, ena='i2c_I.core_I.bit_last_SB_DFFE_Q_E', clk='clk_sys')
--------------
Control Set Optimizer: cost 99 to reduce control sets from 208 to 99
Total control sets: 99
1 2
3 1
4 1
6 1
8 13
9 21
10 12
11 2
12 4
13 5
14 2
15 2
16 5
17 2
18 1
19 1
20 4
24 1
25 1
26 1
29 1
31 2
32 5
33 2
45 1
55 1
60 1
67 1
126 1
191 1
424 1
1 ControlSet(rs='sys_mgr_I.pll_lock_SB_LUT4_I3_O', ena=None, clk='clk_sys')
1 ControlSet(rs='sys_mgr_I.rst_30m72_i', ena=None, clk='clk_48m')
3 ControlSet(rs='sys_mgr_I.pll_lock_SB_LUT4_I3_O', ena='sys_mgr_I.rst_30m72_i', clk='clk_sys')
4 ControlSet(rs='soc_I.usb_I.txll_start', ena='soc_I.usb_I.tx_ll_I.br_cnt[2]', clk='clk_48m')
6 ControlSet(rs='rst_sys', ena=None, clk='clk_48m')
8 ControlSet(rs=None, ena='spi_mux_I.shift_ce', clk='clk_sys')
8 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.token_data_SB_DFFE_Q_9_E[1]', clk='clk_48m')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[2]', clk='clk_sys')
8 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_DFF_D_Q[2]', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_1_I0_SB_DFFR_Q_D_SB_LUT4_O_I3_SB_DFF_Q_D_SB_LUT4_O_I3_SB_LUT4_I2_I0_SB_LUT4_I1_I3_SB_DFFSR_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[1]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[1]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[4]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[3]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[4]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='misc_I.bus_we_gpio', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[2]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[3]', clk='clk_sys')
8 ControlSet(rs=None, ena='soc_I.e1_buf_I.t_done[2]', clk='clk_sys')
9 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.pid_cap', clk='clk_48m')
9 ControlSet(rs='soc_I.uart_I.ub_rdata_rst', ena=None, clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.ub_wr_data', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_fifo_I.ram_rd_ena', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='dbg_tx_SB_DFFES_Q_E', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.urf_wren', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_fifo_I.ram_rd_ena', clk='clk_sys')
9 ControlSet(rs=None, ena='soc_I.uart_I.uart_rx_I.ce', clk='clk_sys')
9 ControlSet(rs=None, ena='i2c_I.ack_out_SB_DFFE_Q_E', clk='clk_sys')
9 ControlSet(rs=None, ena='tick_e1_rx[0]', clk='clk_sys')
9 ControlSet(rs='gps_uart_I.ub_rdata_rst', ena=None, clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_fifo_I.ram_rd_ena', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_fifo_I.ram_rd_ena', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_e1[0]', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_e1[1]', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_uart_I.ub_wr_data', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_tx_SB_DFFES_Q_E', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_uart_I.urf_wren', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_led', clk='clk_sys')
9 ControlSet(rs=None, ena='gps_uart_I.uart_rx_I.ce', clk='clk_sys')
9 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.m1_addr_ce', clk='clk_sys')
10 ControlSet(rs='soc_I.usb_I.trans_I.len_ld', ena=None, clk='clk_48m')
10 ControlSet(rs='rst_48m', ena='soc_I.usb_I.cr_bus_we', clk='clk_48m')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[3]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[2]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[3]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[4]', clk='clk_sys')
10 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I3_O[2]', clk='clk_sys')
10 ControlSet(rs='i2c_I.bus_clr', ena=None, clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[1]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[1]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[2]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[4]', clk='clk_sys')
11 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.len_dec', clk='clk_48m')
11 ControlSet(rs='soc_I.usb_I.trans_I.mc_op_zlen', ena=None, clk='clk_48m')
12 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m')
12 ControlSet(rs=None, ena='soc_I.uart_I.ub_wr_div', clk='clk_sys')
Info: Packing constants..

12 ControlSet(rs=None, ena='gps_uart_I.ub_wr_div', clk='clk_sys')
12 ControlSet(rs='misc_I.bus_clr', ena=None, clk='clk_sys')
13 ControlSet(rs=None, ena='soc_I.cpu_I.decoder_pseudo_trigger_SB_LUT4_I2_O[0]', clk='clk_sys')
13 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_clk[1]', clk='clk_sys')
13 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_clk[0]', clk='clk_sys')
13 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys')
13 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_buf_I.buf_tx_ts_SB_DFFES_Q_E', clk='clk_sys')
14 ControlSet(rs=None, ena='soc_I.usb_I.ep_status_I.p_read_2', clk='clk_48m')
14 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.m0_addr_ce', clk='clk_sys')
15 ControlSet(rs=None, ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
15 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='tick_e1_tx[0]', clk='clk_sys')
16 ControlSet(rs='soc_I.wb_48m_xclk_I.s_cyc_SB_LUT4_I3_O', ena=None, clk='clk_sys')
16 ControlSet(rs=None, ena='soc_I.ub_ack', clk='clk_48m')
16 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.crc_in_valid', clk='clk_48m')
16 ControlSet(rs='soc_I.usb_I.ep_status_I.s_zero_2', ena='soc_I.usb_I.ep_status_I.s_read_2', clk='clk_48m')
16 ControlSet(rs=None, ena='soc_I.e1_buf_tx_re[0]', clk='clk_sys')
17 ControlSet(rs='soc_I.e1_I.bus_clr', ena=None, clk='clk_sys')
17 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I3_O_SB_DFFE_D_Q_SB_LUT4_I0_I3[2]', ena='soc_I.e1_buf_I.buf_rx_frame_SB_LUT4_I0_I1_SB_LUT4_O_I2_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_LUT4_I0_1_O', clk='clk_sys')
18 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.instr_or_SB_DFFESR_Q_E', clk='clk_sys')
19 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_DFFS_D_Q', ena=None, clk='clk_sys')
20 ControlSet(rs='soc_I.usb_I.oob_sof_SB_LUT4_I2_O', ena=None, clk='clk_48m')
20 ControlSet(rs='soc_I.usb_I.phy_I.rx_dn_SB_LUT4_I2_O', ena=None, clk='clk_48m')
20 ControlSet(rs='misc_I.wb_ack_SB_LUT4_I2_O_SB_LUT4_I3_O', ena=None, clk='clk_sys')
20 ControlSet(rs=None, ena='soc_I.cpu_I.trap_SB_LUT4_I3_1_O', clk='clk_sys')
24 ControlSet(rs=None, ena='soc_I.e1_buf_rx_we[0]', clk='clk_sys')
25 ControlSet(rs=None, ena='soc_I.e1_buf_I.t_busy_SB_LUT4_I3_O', clk='clk_sys')
26 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena=None, clk='clk_sys')
29 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.crc_in_valid', clk='clk_48m')
31 ControlSet(rs='soc_I.cpu_I.is_lui_auipc_jal_SB_DFF_Q_D_SB_LUT4_I2_1_O', ena='soc_I.cpu_I.decoder_pseudo_trigger_SB_LUT4_I2_O[0]', clk='clk_sys')
31 ControlSet(rs=None, ena='soc_I.cpu_I.alu_wait_SB_LUT4_I1_O_SB_LUT4_I1_O[3]', clk='clk_sys')
32 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.ack_rd', clk='clk_sys')
32 ControlSet(rs='soc_I.bridge_I.wb_cyc_rst', ena=None, clk='clk_sys')
32 ControlSet(rs=None, ena='soc_I.cpu_I.instr_ecall_ebreak_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[3]', clk='clk_sys')
32 ControlSet(rs=None, ena='soc_I.pb_rst_n_SB_LUT4_I2_O', clk='clk_sys')
32 ControlSet(rs=None, ena='soc_I.cpu_I.trap_SB_LUT4_I2_O', clk='clk_sys')
33 ControlSet(rs=None, ena='soc_I.cpu_I.cpu_state_SB_DFF_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_I0[3]', clk='clk_sys')
33 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena=None, clk='clk_sys')
45 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.epbam_arb_I.reselect', clk='clk_sys')
55 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.spram_arb_I.reselect', clk='clk_sys')
60 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.pb_rst_n_SB_LUT4_I3_1_O[0]', clk='clk_sys')
67 ControlSet(rs='rst_48m', ena=None, clk='clk_48m')
126 ControlSet(rs=None, ena=None, clk='clk_48m')
191 ControlSet(rs='rst_sys', ena=None, clk='clk_sys')
424 ControlSet(rs=None, ena=None, clk='clk_sys')
LUT replication: 0 new LUTs in 0 groups
Info: Packing IOs..
Info: clk_in feeds SB_IO sys_mgr_I.gb_in, removing $nextpnr_ibuf clk_in.
Info: clk_tune_hi feeds SB_IO misc_I.pdm_clk_I[1].io_reg_I, removing $nextpnr_obuf clk_tune_hi.
Info: clk_tune_lo feeds SB_IO misc_I.pdm_clk_I[0].io_reg_I, removing $nextpnr_obuf clk_tune_lo.
Info: e1A_rx_hi_p feeds SB_IO e1A_rx_hi_p_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_hi_p.
Info: e1A_rx_lo_p feeds SB_IO e1A_rx_lo_p_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_lo_p.
Info: e1A_tx_hi feeds SB_IO e1A_tx_hi_SB_IO_PACKAGE_PIN, removing $nextpnr_obuf e1A_tx_hi.
Info: e1A_tx_lo feeds SB_IO e1A_tx_lo_SB_IO_PACKAGE_PIN, removing $nextpnr_obuf e1A_tx_lo.
Info: e1B_rx_hi_p feeds SB_IO e1_dummy_rx_I[1], removing $nextpnr_ibuf e1B_rx_hi_p.
Info: e1B_rx_lo_p feeds SB_IO e1_dummy_rx_I[0], removing $nextpnr_ibuf e1B_rx_lo_p.
Info: e1B_tx_hi feeds SB_IO e1_dummy_tx_I[1], removing $nextpnr_obuf e1B_tx_hi.
Info: e1B_tx_lo feeds SB_IO e1_dummy_tx_I[0], removing $nextpnr_obuf e1B_tx_lo.
Info: e1_led_rclk feeds SB_IO spi_mux_I.iob_I[0], removing $nextpnr_iobuf e1_led_rclk.
Info: flash_clk feeds SB_IO spi_mux_I.iob_I[1], removing $nextpnr_iobuf flash_clk.
Info: flash_miso feeds SB_IO spi_mux_I.iob_I[2], removing $nextpnr_iobuf flash_miso.
Info: flash_mosi feeds SB_IO spi_mux_I.iob_I[3], removing $nextpnr_iobuf flash_mosi.
Info: gps_pps feeds SB_IO misc_I.pps_iob_I, removing $nextpnr_ibuf gps_pps.
Info: gps_reset_n feeds SB_IO misc_I.gpio_iob_I[3], removing $nextpnr_obuf gps_reset_n.
Info: i2c_scl feeds SB_IO i2c_iob_I[1], removing $nextpnr_iobuf i2c_scl.
Info: i2c_sda feeds SB_IO i2c_iob_I[0], removing $nextpnr_iobuf i2c_sda.
Info: usb_dn feeds SB_IO soc_I.usb_I.phy_I.io_dn_I, removing $nextpnr_iobuf usb_dn.
Info: usb_dp feeds SB_IO soc_I.usb_I.phy_I.io_dp_I, removing $nextpnr_iobuf usb_dp.
Info: gpio[0] feeds SB_IO misc_I.gpio_iob_I[0], removing $nextpnr_iobuf gpio[0].
Info: gpio[1] feeds SB_IO misc_I.gpio_iob_I[1], removing $nextpnr_iobuf gpio[1].
Info: gpio[2] feeds SB_IO misc_I.gpio_iob_I[2], removing $nextpnr_iobuf gpio[2].
Info: e1_rx_bias[0] feeds SB_IO misc_I.pdm_e1_I[0].io_reg_I, removing $nextpnr_obuf e1_rx_bias[0].
Info: e1_rx_bias[1] feeds SB_IO misc_I.pdm_e1_I[1].io_reg_I, removing $nextpnr_obuf e1_rx_bias[1].
Info: rgb[0] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO
Info: rgb[1] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO
Info: rgb[2] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO
Info: Packing LUT-FFs..
Info:     1786 LCs used as LUT4 only
Info:     1701 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info:      511 LCs used as DFF only
Info: Packing carries..
Info:      264 LCs used as CARRY only
Info: Packing RAMs..
Info: Placing PLLs..
Info:   constrained PLL 'sys_mgr_I.pll_I' to X12/Y31/pll_3
Info: Packing special functions..
Info:   constrained SB_LEDDA_IP 'soc_I.rgb_I.led_I' to X0/Y31/ledda_ip_2
Info:   constrained SB_RGBA_DRV 'soc_I.rgb_I.rgb_drv_I' to X0/Y30/rgba_drv_0
Info:   constrained SB_SPI 'soc_I.spi_I.spi_I' to X0/Y0/spi_0
Info:   PLL 'sys_mgr_I.pll_I' has LOCK output, need to pass all outputs via LUT
Info:   constrained 'sys_mgr_I.pll_lock_SB_LUT4_I3_LC' to X1/Y30/lc0
Info: Constraining chains...
Info:      210 LCs used to legalise carry chains.
Info: Checksum: 0x9f5b8fb2

Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0xe8e3c358

Info: Device utilisation:
Info: 	         ICESTORM_LC:  4477/ 5280    84%
Info: 	        ICESTORM_RAM:    20/   30    66%
Info: 	               SB_IO:    32/   96    33%
Info: 	               SB_GB:     4/    8    50%
Info: 	        ICESTORM_PLL:     1/    1   100%
Info: 	         SB_WARMBOOT:     1/    1   100%
Info: 	        ICESTORM_DSP:     6/    8    75%
Info: 	      ICESTORM_HFOSC:     0/    1     0%
Info: 	      ICESTORM_LFOSC:     0/    1     0%
Info: 	              SB_I2C:     0/    2     0%
Info: 	              SB_SPI:     1/    2    50%
Info: 	              IO_I3C:     0/    2     0%
Info: 	         SB_LEDDA_IP:     1/    1   100%
Info: 	         SB_RGBA_DRV:     1/    1   100%
Info: 	      ICESTORM_SPRAM:     4/    4   100%

Info: Placed 39 cells based on constraints.
Info: Creating initial analytic placement for 3588 cells, random placement wirelen = 111896.
Info:     at initial placer iter 0, wirelen = 3713
Info:     at initial placer iter 1, wirelen = 3246
Info:     at initial placer iter 2, wirelen = 3248
Info:     at initial placer iter 3, wirelen = 3211
Info: Running main analytical placer.
Info:     at iteration #1, type ALL: wirelen solved = 3243, spread = 38315, legal = 56125; time = 0.44s
Info:     at iteration #2, type ALL: wirelen solved = 4375, spread = 29810, legal = 49270; time = 0.36s
Info:     at iteration #3, type ALL: wirelen solved = 5639, spread = 28919, legal = 48764; time = 0.36s
Info:     at iteration #4, type ALL: wirelen solved = 6869, spread = 28448, legal = 37942; time = 0.24s
Info:     at iteration #5, type ALL: wirelen solved = 7693, spread = 26840, legal = 39426; time = 0.19s
Info:     at iteration #6, type ALL: wirelen solved = 8475, spread = 26429, legal = 41359; time = 0.26s
Info:     at iteration #7, type ALL: wirelen solved = 8859, spread = 26231, legal = 44945; time = 0.28s
Info:     at iteration #8, type ALL: wirelen solved = 9080, spread = 26159, legal = 45238; time = 0.27s
Info:     at iteration #9, type ALL: wirelen solved = 9623, spread = 26346, legal = 45346; time = 0.26s
Info: HeAP Placer Time: 3.17s
Info:   of which solving equations: 0.71s
Info:   of which spreading cells: 0.12s
Info:   of which strict legalisation: 1.99s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 832, wirelen = 37942
Info:   at iteration #5: temp = 0.000000, timing cost = 689, wirelen = 30498
Info:   at iteration #10: temp = 0.000000, timing cost = 614, wirelen = 28933
Info:   at iteration #15: temp = 0.000000, timing cost = 553, wirelen = 27931
Info:   at iteration #20: temp = 0.000000, timing cost = 538, wirelen = 27235
Info:   at iteration #25: temp = 0.000000, timing cost = 531, wirelen = 27009
Info:   at iteration #30: temp = 0.000000, timing cost = 528, wirelen = 26956
Info:   at iteration #35: temp = 0.000000, timing cost = 528, wirelen = 26923
Info:   at iteration #35: temp = 0.000000, timing cost = 528, wirelen = 26923 
Info: SA placement time 6.16s

Info: Max frequency for clock 'clk_sys': 32.09 MHz (PASS at 30.72 MHz)
Info: Max frequency for clock 'clk_48m': 52.63 MHz (PASS at 48.00 MHz)

Info: Max delay <async>         -> posedge clk_sys: 7.02 ns
Info: Max delay posedge clk_48m -> <async>        : 4.04 ns
Info: Max delay posedge clk_48m -> posedge clk_sys: 6.84 ns
Info: Max delay posedge clk_sys -> <async>        : 10.88 ns
Info: Max delay posedge clk_sys -> posedge clk_48m: 14.67 ns

Info: Slack histogram:
Info:  legend: * represents 54 endpoint(s)
Info:          + represents [1,54) endpoint(s)
Info: [  1388,   5328) |+
Info: [  5328,   9268) |*****+
Info: [  9268,  13208) |***********+
Info: [ 13208,  17148) |******************************+
Info: [ 17148,  21088) |***********************+
Info: [ 21088,  25028) |*******************************+
Info: [ 25028,  28968) |************************************************************ 
Info: [ 28968,  32908) |**+
Info: [ 32908,  36848) | 
Info: [ 36848,  40788) | 
Info: [ 40788,  44728) | 
Info: [ 44728,  48668) | 
Info: [ 48668,  52608) | 
Info: [ 52608,  56548) | 
Info: [ 56548,  60488) | 
Info: [ 60488,  64428) | 
Info: [ 64428,  68368) | 
Info: [ 68368,  72308) | 
Info: [ 72308,  76248) |+
Info: [ 76248,  80188) |+
Info: Checksum: 0xfdcf52fe

Info: Routing..
Info: Setting up routing queue.
Info: Routing 15482 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |       20        979 |   20   979 |     14510|       0.11       0.11|
Info:       2000 |       36       1963 |   16   984 |     13529|       0.07       0.18|
Info:       3000 |      115       2884 |   79   921 |     12630|       0.21       0.39|
Info:       4000 |      265       3734 |  150   850 |     11817|       0.17       0.56|
Info:       5000 |      403       4596 |  138   862 |     10996|       0.18       0.74|
Info:       6000 |      600       5399 |  197   803 |     10283|       0.24       0.98|
Info:       7000 |      777       6222 |  177   823 |      9548|       0.23       1.21|
Info:       8000 |     1060       6939 |  283   717 |      8990|       0.24       1.44|
Info:       9000 |     1368       7631 |  308   692 |      8441|       0.26       1.70|
Info:      10000 |     1629       8370 |  261   739 |      7807|       0.24       1.94|
Info:      11000 |     2056       8943 |  427   573 |      7520|       0.37       2.31|
Info:      12000 |     2483       9516 |  427   573 |      7165|       0.37       2.68|
Info:      13000 |     2985      10014 |  502   498 |      6934|       0.37       3.05|
Info:      14000 |     3449      10550 |  464   536 |      6726|       0.48       3.53|
Info:      15000 |     3997      11002 |  548   452 |      6609|       0.52       4.05|
Info:      16000 |     4544      11455 |  547   453 |      6415|       0.56       4.61|
Info:      17000 |     5053      11946 |  509   491 |      6256|       0.43       5.04|
Info:      18000 |     5634      12365 |  581   419 |      6108|       0.43       5.46|
Info:      19000 |     5936      13063 |  302   698 |      5569|       0.32       5.79|
Info:      20000 |     6446      13553 |  510   490 |      5368|       0.50       6.29|
Info:      21000 |     6739      14260 |  293   707 |      4785|       0.26       6.55|
Info:      22000 |     7232      14767 |  493   507 |      4517|       0.61       7.16|
Info:      23000 |     7751      15248 |  519   481 |      4399|       0.92       8.08|
Info:      24000 |     8329      15670 |  578   422 |      4295|       0.64       8.72|
Info:      25000 |     8925      16074 |  596   404 |      4305|       0.59       9.31|
Info:      26000 |     9558      16441 |  633   367 |      4242|       0.79      10.10|
Info:      27000 |    10152      16847 |  594   406 |      4169|       0.85      10.95|
Info:      28000 |    10739      17260 |  587   413 |      4069|       0.63      11.59|
Info:      29000 |    11330      17669 |  591   409 |      3950|       0.65      12.23|
Info:      30000 |    11907      18092 |  577   423 |      3909|       0.65      12.89|
Info:      31000 |    12504      18495 |  597   403 |      3842|       0.58      13.47|
Info:      32000 |    13114      18885 |  610   390 |      3776|       0.80      14.27|
Info:      33000 |    13750      19249 |  636   364 |      3783|       0.67      14.93|
Info:      34000 |    14330      19669 |  580   420 |      3728|       0.71      15.64|
Info:      35000 |    14913      20086 |  583   417 |      3640|       1.05      16.70|
Info:      36000 |    15511      20488 |  598   402 |      3526|       0.73      17.43|
Info:      37000 |    16054      20945 |  543   457 |      3408|       0.65      18.07|
Info:      38000 |    16688      21311 |  634   366 |      3402|       0.79      18.87|
Info:      39000 |    17312      21687 |  624   376 |      3376|       0.78      19.64|
Info:      40000 |    17846      22153 |  534   466 |      3276|       0.80      20.45|
Info:      41000 |    18444      22555 |  598   402 |      3232|       0.88      21.32|
Info:      42000 |    19031      22968 |  587   413 |      3159|       0.63      21.96|
Info:      43000 |    19574      23425 |  543   457 |      3064|       0.83      22.79|
Info:      44000 |    20183      23816 |  609   391 |      2986|       0.87      23.65|
Info:      45000 |    20760      24239 |  577   423 |      2915|       0.68      24.34|
Info:      46000 |    21338      24661 |  578   422 |      2827|       0.80      25.14|
Info:      47000 |    21995      25004 |  657   343 |      2813|       0.83      25.97|
Info:      48000 |    22564      25435 |  569   431 |      2710|       0.71      26.68|
Info:      49000 |    23153      25846 |  589   411 |      2600|       0.76      27.44|
Info:      50000 |    23503      26496 |  350   650 |      2089|       0.39      27.83|
Info:      51000 |    23889      27110 |  386   614 |      1581|       0.34      28.17|
Info:      52000 |    24447      27552 |  558   442 |      1434|       0.74      28.91|
Info:      53000 |    25049      27950 |  602   398 |      1393|       0.64      29.55|
Info:      54000 |    25491      28508 |  442   558 |      1070|       0.95      30.50|
Info:      55000 |    26053      28946 |  562   438 |       906|       2.02      32.53|
Info:      56000 |    26554      29445 |  501   499 |       645|       3.17      35.69|
Info:      57000 |    27152      29847 |  598   402 |       531|       1.95      37.64|
Info:      58000 |    27604      30395 |  452   548 |       210|       1.22      38.86|
Info:      58217 |    27611      30606 |    7   211 |         0|       0.05      38.91|
Info: Routing complete.
Info: Router1 time 38.91s
Info: Checksum: 0x0fc9cf3f

Info: Critical path report for clock 'clk_sys' (posedge -> posedge):
Info: curr total
Info:  1.4  1.4  Source soc_I.cpu_I.mem_do_rinst_SB_DFFESS_Q_conv_LC.O
Info:  4.8  6.2    Net soc_I.cpu_I.mem_do_rinst budget 1.349000 ns (3,13) -> (12,18)
Info:                Sink soc_I.cpu_I.mem_do_rinst_SB_LUT4_I3_LC.I3
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info:                  /build/gateware/common/rtl/picorv32.v:340.6-340.18
Info:                  /build/gateware/common/rtl/soc_base.v:211.4-221.3
Info:  0.9  7.1  Source soc_I.cpu_I.mem_do_rinst_SB_LUT4_I3_LC.O
Info:  4.2 11.3    Net soc_I.cpu_I.mem_do_rinst_SB_LUT4_I3_O[3] budget 1.256000 ns (12,18) -> (5,12)
Info:                Sink soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_O_I1_SB_LUT4_O_LC.I3
Info:                Defined in:
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.9 12.2  Source soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_O_I1_SB_LUT4_O_LC.O
Info:  1.8 13.9    Net soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_O_I1[0] budget 1.833000 ns (5,12) -> (4,11)
Info:                Sink soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_O_LC.I1
Info:                Defined in:
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  1.2 15.1  Source soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_O_LC.O
Info:  1.8 16.9    Net soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3[2] budget 1.350000 ns (4,11) -> (4,12)
Info:                Sink soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_I0_LC.I0
Info:                Defined in:
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  1.3 18.2  Source soc_I.cpu_I.instr_sb_SB_LUT4_I2_I3_SB_LUT4_I0_LC.O
Info:  3.7 21.9    Net soc_I.cpu_I.instr_lhu_SB_LUT4_I1_O_SB_LUT4_O_I1[1] budget 3.140000 ns (4,12) -> (4,20)
Info:                Sink soc_I.cpu_I.alu_wait_SB_LUT4_I1_O_SB_LUT4_I1_LC.I2
Info:                Defined in:
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  1.2 23.1  Source soc_I.cpu_I.alu_wait_SB_LUT4_I1_O_SB_LUT4_I1_LC.O
Info:  1.8 24.9    Net soc_I.cpu_I.alu_wait_SB_LUT4_I1_O_SB_LUT4_I1_O[3] budget 1.687000 ns (4,20) -> (5,19)
Info:                Sink soc_I.cpu_I.instr_sra_SB_LUT4_I0_LC.I3
Info:                Defined in:
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.9 25.7  Source soc_I.cpu_I.instr_sra_SB_LUT4_I0_LC.O
Info:  5.2 31.0    Net soc_I.cpu_I.reg_op1_SB_DFFE_Q_31_E budget 1.885000 ns (5,19) -> (22,14)
Info:                Sink soc_I.cpu_I.reg_op1_SB_DFFE_Q_31_conv_LC.I2
Info:  1.2 32.1  Setup soc_I.cpu_I.reg_op1_SB_DFFE_Q_31_conv_LC.I2
Info: 8.9 ns logic, 23.2 ns routing

Info: Critical path report for clock 'clk_48m' (posedge -> posedge):
Info: curr total
Info:  1.2  1.2  Source soc_I.usb_I.trans_I.mc_rom_I_RAM.RDATA_6
Info:  3.1  4.2    Net soc_I.usb_I.trans_I.mc_opcode[6] budget 1.961000 ns (19,11) -> (20,10)
Info:                Sink soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_1_LC.I1
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info:                  /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info:                  /build/gateware/cores/no2usb//rtl/usb_trans.v:91.14-91.23
Info:                  /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info:  1.2  5.5  Source soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_1_LC.O
Info:  1.8  7.2    Net soc_I.usb_I.trans_I.mc_match_bits[2] budget 1.305000 ns (20,10) -> (20,10)
Info:                Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.I2
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info:                  /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info:                  /build/gateware/cores/no2usb//rtl/usb_trans.v:85.32-85.45
Info:                  /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info:  1.2  8.4  Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.O
Info:  1.8 10.2    Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0[0] budget 1.371000 ns (20,10) -> (20,11)
Info:                Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.I0
Info:                Defined in:
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  1.3 11.5  Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.O
Info:  1.8 13.2    Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_O[2] budget 1.305000 ns (20,11) -> (21,12)
Info:                Sink soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.I2
Info:                Defined in:
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  1.2 14.4  Source soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.O
Info:  1.8 16.2    Net soc_I.usb_I.trans_I.mc_pc[0] budget 1.306000 ns (21,12) -> (22,11)
Info:                Sink $nextpnr_ICESTORM_LC_196.I1
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info:                  /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info:                  /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info:                  /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.7 16.9  Source $nextpnr_ICESTORM_LC_196.COUT
Info:  0.0 16.9    Net $nextpnr_ICESTORM_LC_196$O budget 0.000000 ns (22,11) -> (22,11)
Info:                Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.CIN
Info:  0.3 17.2  Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.COUT
Info:  0.0 17.2    Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[2] budget 0.000000 ns (22,11) -> (22,11)
Info:                Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.CIN
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info:                  /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info:                  /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info:                  /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.3 17.4  Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.COUT
Info:  0.0 17.4    Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[3] budget 0.000000 ns (22,11) -> (22,11)
Info:                Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.CIN
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info:                  /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info:                  /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info:                  /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.3 17.7  Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.COUT
Info:  0.0 17.7    Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[4] budget 0.000000 ns (22,11) -> (22,11)
Info:                Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.CIN
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info:                  /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info:                  /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info:                  /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.3 18.0  Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.COUT
Info:  0.0 18.0    Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[5] budget 0.000000 ns (22,11) -> (22,11)
Info:                Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.CIN
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info:                  /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info:                  /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info:                  /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.3 18.3  Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.COUT
Info:  0.0 18.3    Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[6] budget 0.000000 ns (22,11) -> (22,11)
Info:                Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.CIN
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info:                  /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info:                  /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info:                  /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.3 18.5  Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.COUT
Info:  0.7 19.2    Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[7] budget 0.660000 ns (22,11) -> (22,11)
Info:                Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info:                  /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info:                  /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info:                  /build/gateware/common/rtl/soc_base.v:374.4-394.3
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info:  0.8 20.0  Setup soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3
Info: 9.3 ns logic, 10.8 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge clk_sys':
Info: curr total
Info:  0.0  0.0  Source spi_mux_I.iob_I[3].D_IN_0
Info:  8.2  8.2    Net flash_mosi_i budget 31.052000 ns (23,0) -> (0,0)
Info:                Sink soc_I.spi_I.spi_I.SI
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:374.4-400.3
Info:                  /build/gateware/icE1usb/rtl/sr_btn_if.v:28.14-28.24
Info:  1.5  9.7  Setup soc_I.spi_I.spi_I.SI
Info: 1.5 ns logic, 8.2 ns routing

Info: Critical path report for cross-domain path 'posedge clk_48m' -> '<async>':
Info: curr total
Info:  1.4  1.4  Source soc_I.usb_I.pad_pu_SB_DFFSR_Q_DFFLC.O
Info:  2.4  3.8    Net usb_pu$SB_IO_OUT budget 81.943001 ns (17,2) -> (17,0)
Info:                Sink usb_pu$sb_io.D_OUT_0
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:39.14-39.20
Info: 1.4 ns logic, 2.4 ns routing

Info: Critical path report for cross-domain path 'posedge clk_48m' -> 'posedge clk_sys':
Info: curr total
Info:  1.4  1.4  Source soc_I.usb_I.sof_ind_SB_LUT4_I3_LC.O
Info:  4.2  5.6    Net soc_I.sof_xclk_I.src budget 29.927999 ns (16,13) -> (14,1)
Info:                Sink soc_I.sof_xclk_I.dst_SB_DFFR_Q_1_DFFLC.I0
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:151.4-192.3
Info:                  /build/gateware/cores/no2misc//rtl/xclk_strobe.v:25.6-25.9
Info:                  /build/gateware/common/rtl/soc_base.v:421.14-427.3
Info:  1.2  6.9  Setup soc_I.sof_xclk_I.dst_SB_DFFR_Q_1_DFFLC.I0
Info: 2.6 ns logic, 4.2 ns routing

Info: Critical path report for cross-domain path 'posedge clk_sys' -> '<async>':
Info: curr total
Info:  1.5  1.5  Source soc_I.spi_I.spi_I.MCSNO0
Info:  8.7 10.2    Net flash_csn_o budget 40.313999 ns (0,0) -> (22,1)
Info:                Sink flash_cs_n_SB_LUT4_O_LC.I2
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:374.4-400.3
Info:                  /build/gateware/icE1usb/rtl/sr_btn_if.v:40.14-40.23
Info:  1.2 11.4  Source flash_cs_n_SB_LUT4_O_LC.O
Info:  3.0 14.3    Net flash_cs_n$SB_IO_OUT budget 38.368999 ns (22,1) -> (24,0)
Info:                Sink flash_cs_n$sb_io.D_OUT_0
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:374.4-400.3
Info:                  /build/gateware/icE1usb/rtl/sr_btn_if.v:90.7-90.16
Info: 2.7 ns logic, 11.6 ns routing

Info: Critical path report for cross-domain path 'posedge clk_sys' -> 'posedge clk_48m':
Info: curr total
Info:  1.4  1.4  Source soc_I.cpu_I.mem_wstrb_SB_DFFE_Q_conv_LC.O
Info:  4.2  5.6    Net wb_wmsk[3] budget 3.604000 ns (13,26) -> (16,15)
Info:                Sink gps_uart_I.wb_we_SB_LUT4_O_LC.I3
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:94.18-94.25
Info:  0.9  6.5  Source gps_uart_I.wb_we_SB_LUT4_O_LC.O
Info:  3.1  9.6    Net wb_we budget 5.229000 ns (16,15) -> (16,10)
Info:                Sink soc_I.usb_I.cr_bus_we_SB_DFFSR_Q_D_SB_LUT4_O_LC.I2
Info:                Defined in:
Info:                  /build/gateware/icE1usb/rtl/top.v:95.18-95.23
Info:  1.2 10.8  Source soc_I.usb_I.cr_bus_we_SB_DFFSR_Q_D_SB_LUT4_O_LC.O
Info:  1.8 12.5    Net soc_I.usb_I.cr_bus_we_SB_DFFSR_Q_D[1] budget 3.679000 ns (16,10) -> (16,9)
Info:                Sink soc_I.usb_I.cr_bus_we_SB_DFFSR_Q_conv_LC.I3
Info:                Defined in:
Info:                  /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.8 13.4  Setup soc_I.usb_I.cr_bus_we_SB_DFFSR_Q_conv_LC.I3
Info: 4.3 ns logic, 9.1 ns routing

Info: Max frequency for clock 'clk_sys': 31.14 MHz (PASS at 30.72 MHz)
Info: Max frequency for clock 'clk_48m': 49.92 MHz (PASS at 48.00 MHz)

Info: Max delay <async>         -> posedge clk_sys: 9.68 ns
Info: Max delay posedge clk_48m -> <async>        : 3.80 ns
Info: Max delay posedge clk_48m -> posedge clk_sys: 6.87 ns
Info: Max delay posedge clk_sys -> <async>        : 14.34 ns
Info: Max delay posedge clk_sys -> posedge clk_48m: 13.36 ns

Info: Slack histogram:
Info:  legend: * represents 56 endpoint(s)
Info:          + represents [1,56) endpoint(s)
Info: [   361,   4353) |+
Info: [  4353,   8345) |***+
Info: [  8345,  12337) |********+
Info: [ 12337,  16329) |*********************+
Info: [ 16329,  20321) |***********************+
Info: [ 20321,  24313) |************************************+
Info: [ 24313,  28305) |************************************************************ 
Info: [ 28305,  32297) |*****+
Info: [ 32297,  36289) | 
Info: [ 36289,  40281) | 
Info: [ 40281,  44273) | 
Info: [ 44273,  48265) | 
Info: [ 48265,  52257) | 
Info: [ 52257,  56249) | 
Info: [ 56249,  60241) | 
Info: [ 60241,  64233) | 
Info: [ 64233,  68225) | 
Info: [ 68225,  72217) |+
Info: [ 72217,  76209) |+
Info: [ 76209,  80201) |+
4 warnings, 0 errors
icepack -s /build/gateware/icE1usb/build-tmp/icE1usb.asc /build/gateware/icE1usb/build-tmp/icE1usb.bin
make: Leaving directory '/build/gateware/icE1usb'
$ ssh-agent -k
unset SSH_AUTH_SOCK;
unset SSH_AGENT_PID;
echo Agent pid 2081475 killed;
[ssh-agent] Stopped.
Archiving artifacts
‘**/core’ doesn’t match anything: ‘**’ exists but not ‘**/core’
No artifacts found that match the file pattern "**/core, **/testsuite.log, **/workspace.tar.xz". Configuration error?
Finished: SUCCESS