Skipping 2,187 KB..
Full LogAdding SRST signal on $auto$opt_dff.cc:702:run$24411 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:170$4567_Y [2:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.pg_hi [2:1], rval = 2'00).
Adding SRST signal on $auto$opt_dff.cc:702:run$24410 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.\tx_I.$sub$/build/gateware/cores/no2e1//rtl/e1_tx.v:171$4568_Y [2:1], Q = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\stx_I.tx_I.pg_lo [2:1], rval = 2'00).
75.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
75.29.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~37 debug messages>
75.29.9. Rerunning OPT passes. (Maybe there is more to do..)
75.29.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12413.
dead port 1/2 on $mux $flatten\soc_I.\e1_buf_I.$procmux$12428.
Removed 2 multiplexer ports.
<suppressed ~186 debug messages>
75.29.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
75.29.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.
75.29.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$opt_dff.cc:764:run$24851 ($dffe) from module top (D = $auto$wreduce.cc:454:run$24917 [2:0], Q = \i2c_I.core_I.bit_cnt [2:0], rval = 3'000).
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24584 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$opt_dff.cc:764:run$24584 ($dffe) from module top.
Setting constant 0-bit at position 0 on $auto$opt_dff.cc:764:run$24365 ($dffe) from module top.
Setting constant 1-bit at position 9 on $auto$opt_dff.cc:764:run$24313 ($adffe) from module top.
75.29.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 20 unused wires.
<suppressed ~2 debug messages>
75.29.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.29.16. Rerunning OPT passes. (Maybe there is more to do..)
75.29.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~186 debug messages>
75.29.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
75.29.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
75.29.20. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 7 on $auto$opt_dff.cc:702:run$24376 ($sdff) from module top.
Adding SRST signal on $auto$opt_dff.cc:702:run$24376 ($sdff) from module top (D = $flatten\soc_I.\e1_I.$genblock$/build/gateware/cores/no2e1//rtl/e1_wb.v:138$5366[0].\srx_I.bd_rx_out_I.data[1] [8:7], Q = \soc_I.e1_I.wb_rdata [14:13], rval = 2'00).
Removing never-active SRST on $auto$opt_dff.cc:702:run$24371 ($sdffce) from module top.
Removing never-active SRST on $auto$opt_dff.cc:702:run$24369 ($sdffce) from module top.
Removing never-active SRST on $auto$opt_dff.cc:702:run$24367 ($sdffce) from module top.
75.29.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
75.29.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>
75.29.23. Rerunning OPT passes. (Maybe there is more to do..)
75.29.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~186 debug messages>
75.29.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
75.29.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.
75.29.27. Executing OPT_DFF pass (perform DFF optimizations).
75.29.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
<suppressed ~1 debug messages>
75.29.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.29.30. Rerunning OPT passes. (Maybe there is more to do..)
75.29.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~186 debug messages>
75.29.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
75.29.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
75.29.34. Executing OPT_DFF pass (perform DFF optimizations).
75.29.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
75.29.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.29.37. Finished OPT passes. (There is nothing left to do.)
75.30. Executing ICE40_WRAPCARRY pass (wrap carries).
75.31. Executing TECHMAP pass (map to technology primitives).
75.31.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
75.31.2. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.
75.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $sdffce.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $dffe.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using extmapper simplemap for cells of type $adffe.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $adff.
Using extmapper simplemap for cells of type $mux.
Using template $paramod$constmap:37b3cc4e06391b7a7ef418215dc52e2abb59f048$paramod$71443bc33ec938a4dea8c4b4bbb3a548919fd2a5\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod$constmap:f131a727070ba63172385ab8bc15babdfc05a11a$paramod$4d8c31a57f918e2cd1d0bc24d8284efd6d83f4a8\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=3\Y_WIDTH=3 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=7\B_WIDTH=1\Y_WIDTH=7 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=5\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=1\Y_WIDTH=5 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=1\Y_WIDTH=2 for cells of type $alu.
Using template $paramod$constmap:98a2574d6790db88f29c592e698ccfc2583099ee$paramod$da4b7a069bab2d2cb126ab511d2c5f5d67aa4129\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=14\Y_WIDTH=14 for cells of type $alu.
Using template $paramod$constmap:2a578b20caa92a5095129d48a2f94bbad08a990f$paramod$5c10e52cdc159999f3945c97d8a1bfa2ca0de2dc\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=12 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=1\Y_WIDTH=13 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_xor.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=20\Y_WIDTH=20 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=4 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=16\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=5 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=2\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=11\B_WIDTH=1\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=6 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=8 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=6 for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_xnor.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=1\Y_WIDTH=9 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=2\Y_WIDTH=3 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=11\Y_WIDTH=11 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=10\B_WIDTH=10\Y_WIDTH=10 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu.
Using template $paramod$constmap:66d421c313e4e958be776b99540ac2de3b59fdbc$paramod$9b74a473ccd678a23e1df4cc12019cbbece20051\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=31\B_WIDTH=31\Y_WIDTH=31 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=30\B_WIDTH=30\Y_WIDTH=30 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=16\Y_WIDTH=16 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=6\B_WIDTH=1\Y_WIDTH=6 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=1\B_SIGNED=1\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=1\Y_WIDTH=3 for cells of type $alu.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=8\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=24\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=5 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=4 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=5 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=4\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=9\B_WIDTH=9\Y_WIDTH=9 for cells of type $alu.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=4\B_WIDTH=4\Y_WIDTH=4 for cells of type $alu.
Using template $paramod$constmap:87e158a1e7f9a65bc3daafa14cddbc2f2a62b0f9$paramod$00673b792be9df78f478ac12e847ffbbf69ec54f\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod$constmap:97d3e8470f71c97b2a3f4cc7d3b643b1fee5fa20$paramod$46cd3b166c849b74a0d50b3191f97ef695044070\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=26\Y_WIDTH=26 for cells of type $alu.
Using template $paramod$constmap:684fca2758d270a6aba8ac07bc0dd26758fbc9a0$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx for cells of type $shiftx.
Analyzing pattern of constant bits for this cell:
Constant input on bit 0 of port A: 1'0
Constant input on bit 1 of port A: 1'0
Constant input on bit 2 of port A: 1'0
Constant input on bit 3 of port A: 1'0
Constant input on bit 4 of port A: 1'1
Constant input on bit 5 of port A: 1'1
Constant input on bit 6 of port A: 1'1
Constant input on bit 7 of port A: 1'1
Constant input on bit 8 of port A: 1'0
Constant input on bit 9 of port A: 1'0
Constant input on bit 10 of port A: 1'0
Constant input on bit 11 of port A: 1'0
Constant input on bit 12 of port A: 1'1
Constant input on bit 13 of port A: 1'1
Constant input on bit 14 of port A: 1'1
Constant input on bit 15 of port A: 1'1
Creating constmapped module `$paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx'.
75.31.151. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 2/2 on $mux $procmux$36256.
dead port 2/2 on $mux $procmux$36250.
dead port 2/2 on $mux $procmux$36244.
dead port 2/2 on $mux $procmux$36238.
Removed 4 multiplexer ports.
<suppressed ~4260 debug messages>
75.31.152. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx.
<suppressed ~3 debug messages>
Removed 0 unused cells and 11 unused wires.
Using template $paramod$constmap:8b3644844662a5df890757b6e744f94687338ba9$paramod$ce139bdae4db109c6875842b953e3d257bf611b7\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod\_90_pmux\WIDTH=3\S_WIDTH=7 for cells of type $pmux.
Using template $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=13\B_WIDTH=13\Y_WIDTH=13 for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu.
No more expansions possible.
<suppressed ~1296 debug messages>
75.32. Executing OPT pass (performing simple optimizations).
75.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3427 debug messages>
75.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3765 debug messages>
Removed a total of 1255 cells.
75.32.3. Executing OPT_DFF pass (perform DFF optimizations).
75.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1003 unused cells and 4623 unused wires.
<suppressed ~1016 debug messages>
75.32.5. Finished fast OPT passes.
75.33. Executing ICE40_OPT pass (performing simple optimizations).
75.33.1. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24989.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$24989.BB [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$24998.slice[0].carry: CO=\blinker_I.tick_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25004.slice[0].carry: CO=\gps_uart_I.uart_div [1]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25004.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$25004.C [11]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25007.slice[0].carry: CO=\gps_uart_I.uart_rx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25010.slice[0].carry: CO=\gps_uart_I.uart_rx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25016.slice[0].carry: CO=\gps_uart_I.uart_rx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25022.slice[0].carry: CO=\gps_uart_I.uart_rx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25025.slice[0].carry: CO=\gps_uart_I.uart_tx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25028.slice[0].carry: CO=\gps_uart_I.uart_tx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25031.slice[0].carry: CO=\gps_uart_I.uart_tx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25037.slice[0].carry: CO=\gps_uart_I.uart_tx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25040.slice[0].carry: CO=\i2c_I.core_I.cyc_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25043.slice[0].carry: CO=\i2c_I.core_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25052.slice[0].carry: CO=\sys_mgr_I.rst_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25073.slice[0].carry: CO=\soc_I.cpu_I.reg_pc [2]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25076.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25076.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25105.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [2]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25108.slice[0].carry: CO=\soc_I.cpu_I.reg_sh [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25111.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25111.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25114.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25114.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25117.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25117.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25120.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25120.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25135.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25135.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25159.slice[0].carry: CO=\soc_I.e1_buf_I.buf_tx_ts [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25162.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25162.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25165.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25165.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25171.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m0_addr_i [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25174.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.m1_addr_i [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25177.slice[0].carry: CO=\soc_I.iobuf_I.dma_I.len [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25180.slice[0].carry: CO=\soc_I.uart_I.uart_div [1]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25180.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$25180.C [11]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25183.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25186.slice[0].carry: CO=\soc_I.uart_I.uart_rx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25192.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25198.slice[0].carry: CO=\soc_I.uart_I.uart_rx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25201.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25204.slice[0].carry: CO=\soc_I.uart_I.uart_tx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25207.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25213.slice[0].carry: CO=\soc_I.uart_I.uart_tx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25225.slice[0].carry: CO=\soc_I.usb_I.rx_pkt_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25225.slice[3].carry: CO=$auto$alumacc.cc:485:replace_alu$25225.C [3]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25228.slice[0].carry: CO=\soc_I.usb_I.trans_I.mc_pc [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25243.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25243.B [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25243.slice[2].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25246.slice[0].carry: CO=\soc_I.usb_I.tx_ll_I.bs_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25249.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25249.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25252.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$25252.A [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$25255.slice[0].carry: CO=\spi_mux_I.tick_cnt [0]
75.33.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~41 debug messages>
75.33.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
75.33.4. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30618 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12189.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [3], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30617 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12189.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30616 ($_SDFFCE_PP0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12189.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_rep_state_1 [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30614 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12206.B_AND_S [3], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [3], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30613 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12206.Y_B [2], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:559:simplemap_adffe_sdffe_sdffce$30612 ($_SDFFCE_PN0P_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12206.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_sync_state_1 [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35192 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [31], Q = \misc_I.wb_rdata [31], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35191 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [30], Q = \misc_I.wb_rdata [30], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35190 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [29], Q = \misc_I.wb_rdata [29], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35189 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [28], Q = \misc_I.wb_rdata [28], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35188 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [27], Q = \misc_I.wb_rdata [27], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35187 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [26], Q = \misc_I.wb_rdata [26], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35186 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [25], Q = \misc_I.wb_rdata [25], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35185 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [24], Q = \misc_I.wb_rdata [24], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35184 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [23], Q = \misc_I.wb_rdata [23], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35183 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [22], Q = \misc_I.wb_rdata [22], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35182 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [21], Q = \misc_I.wb_rdata [21], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35181 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [20], Q = \misc_I.wb_rdata [20], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35176 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [15], Q = \misc_I.wb_rdata [15], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35175 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [14], Q = \misc_I.wb_rdata [14], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35174 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [13], Q = \misc_I.wb_rdata [13], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35173 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [12], Q = \misc_I.wb_rdata [12], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35168 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [7], Q = \misc_I.wb_rdata [7], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35167 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [6], Q = \misc_I.wb_rdata [6], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35166 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [5], Q = \misc_I.wb_rdata [5], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$35165 ($_SDFF_PP0_) from module top (D = $flatten\misc_I.$procmux$11716.Y_B [4], Q = \misc_I.wb_rdata [4], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:527:simplemap_adff_sdff$31214 ($_SDFF_PP0_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12232.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.samp_cnt [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34791 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [31], Q = \soc_I.cpu_I.decoded_imm [31], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34790 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [30], Q = \soc_I.cpu_I.decoded_imm [30], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34789 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [29], Q = \soc_I.cpu_I.decoded_imm [29], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34788 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [28], Q = \soc_I.cpu_I.decoded_imm [28], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34787 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [27], Q = \soc_I.cpu_I.decoded_imm [27], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34786 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [26], Q = \soc_I.cpu_I.decoded_imm [26], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34785 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [25], Q = \soc_I.cpu_I.decoded_imm [25], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34784 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [24], Q = \soc_I.cpu_I.decoded_imm [24], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34783 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [23], Q = \soc_I.cpu_I.decoded_imm [23], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34782 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [22], Q = \soc_I.cpu_I.decoded_imm [22], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34781 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [21], Q = \soc_I.cpu_I.decoded_imm [21], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34780 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [20], Q = \soc_I.cpu_I.decoded_imm [20], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34779 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [19], Q = \soc_I.cpu_I.decoded_imm [19], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34778 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [18], Q = \soc_I.cpu_I.decoded_imm [18], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34777 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [17], Q = \soc_I.cpu_I.decoded_imm [17], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34776 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [16], Q = \soc_I.cpu_I.decoded_imm [16], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34775 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [15], Q = \soc_I.cpu_I.decoded_imm [15], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34774 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [14], Q = \soc_I.cpu_I.decoded_imm [14], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34773 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [13], Q = \soc_I.cpu_I.decoded_imm [13], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34772 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [12], Q = \soc_I.cpu_I.decoded_imm [12], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34771 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [11], Q = \soc_I.cpu_I.decoded_imm [11], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34770 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [10], Q = \soc_I.cpu_I.decoded_imm [10], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34769 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [9], Q = \soc_I.cpu_I.decoded_imm [9], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34768 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [8], Q = \soc_I.cpu_I.decoded_imm [8], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34767 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [7], Q = \soc_I.cpu_I.decoded_imm [7], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34766 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [6], Q = \soc_I.cpu_I.decoded_imm [6], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34765 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [5], Q = \soc_I.cpu_I.decoded_imm [5], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34764 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [4], Q = \soc_I.cpu_I.decoded_imm [4], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34763 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [3], Q = \soc_I.cpu_I.decoded_imm [3], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34762 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [2], Q = \soc_I.cpu_I.decoded_imm [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$34761 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\cpu_I.$procmux$14371.Y_B [1], Q = \soc_I.cpu_I.decoded_imm [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30608 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12221.B_AND_S [2], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [2], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30607 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12221.Y_B [1], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [1], rval = 1'0).
Adding SRST signal on $auto$simplemap.cc:442:simplemap_dffe$30606 ($_DFFE_PP_) from module top (D = $flatten\soc_I.\usb_I.\rx_ll_I.$procmux$12221.Y_B [0], Q = \soc_I.usb_I.rx_ll_I.dec_eop_state_1 [0], rval = 1'0).
75.33.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 62 unused cells and 32 unused wires.
<suppressed ~63 debug messages>
75.33.6. Rerunning OPT passes. (Removed registers in this run.)
75.33.7. Running ICE40 specific optimizations.
75.33.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.33.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~132 debug messages>
Removed a total of 44 cells.
75.33.10. Executing OPT_DFF pass (perform DFF optimizations).
75.33.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 44 unused wires.
<suppressed ~1 debug messages>
75.33.12. Rerunning OPT passes. (Removed registers in this run.)
75.33.13. Running ICE40 specific optimizations.
75.33.14. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.33.15. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
75.33.16. Executing OPT_DFF pass (perform DFF optimizations).
75.33.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
75.33.18. Finished OPT passes. (There is nothing left to do.)
75.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
75.35. Executing TECHMAP pass (map to technology primitives).
75.35.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.
75.35.2. Continuing TECHMAP pass.
Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_.
Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_.
Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_DFF_P_ for cells of type $_DFF_P_.
Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_.
Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_.
Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_.
Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
No more expansions possible.
<suppressed ~2238 debug messages>
75.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping top.$auto$alumacc.cc:485:replace_alu$24998.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25004.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25004.slice[11].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25007.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25010.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25016.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25022.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25025.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25028.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25031.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25037.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25040.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25043.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25052.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25073.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25076.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25105.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25108.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25111.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25114.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25117.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25120.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25135.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25159.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25162.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25165.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25171.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25174.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25177.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25180.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25180.slice[11].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25183.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25186.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25192.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25198.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25201.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25204.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25207.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25213.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25225.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25225.slice[3].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25228.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25243.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25243.slice[2].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25246.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25249.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25252.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$25255.slice[0].carry ($lut).
75.38. Executing ICE40_OPT pass (performing simple optimizations).
75.38.1. Running ICE40 specific optimizations.
75.38.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~1263 debug messages>
75.38.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~1350 debug messages>
Removed a total of 450 cells.
75.38.4. Executing OPT_DFF pass (perform DFF optimizations).
75.38.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 12116 unused wires.
<suppressed ~1 debug messages>
75.38.6. Rerunning OPT passes. (Removed registers in this run.)
75.38.7. Running ICE40 specific optimizations.
75.38.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
75.38.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
75.38.10. Executing OPT_DFF pass (perform DFF optimizations).
75.38.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
75.38.12. Finished OPT passes. (There is nothing left to do.)
75.39. Executing TECHMAP pass (map to technology primitives).
75.39.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.
75.39.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
75.40. Executing ABC pass (technology mapping using ABC).
75.40.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 6464 gates and 8900 wires to a netlist network with 2434 inputs and 1805 outputs.
75.40.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC:
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
ABC: + strash
ABC: + ifraig
ABC: + scorr
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2
ABC: + dretime
ABC: + strash
ABC: + dch -f
ABC: + if
ABC: + mfs2
ABC: + lutpack -S 1
ABC: + dress
ABC: Total number of equiv classes = 2241.
ABC: Participating nodes from both networks = 4743.
ABC: Participating nodes from the first network = 2257. ( 79.95 % of nodes)
ABC: Participating nodes from the second network = 2486. ( 88.06 % of nodes)
ABC: Node pairs (any polarity) = 2257. ( 79.95 % of names can be moved)
ABC: Node pairs (same polarity) = 1975. ( 69.96 % of names can be moved)
ABC: Total runtime = 0.08 sec
ABC: + write_blif <abc-temp-dir>/output.blif
75.40.1.2. Re-integrating ABC results.
ABC RESULTS: $lut cells: 2822
ABC RESULTS: internal signals: 4661
ABC RESULTS: input signals: 2434
ABC RESULTS: output signals: 1805
Removing temp directory.
75.41. Executing ICE40_WRAPCARRY pass (wrap carries).
75.42. Executing TECHMAP pass (map to technology primitives).
75.42.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.
75.42.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~22 debug messages>
Removed 107 unused cells and 5884 unused wires.
75.43. Executing OPT_LUT pass (optimize LUTs).
Discovering LUTs.
Number of LUTs: 3500
1-LUT 116
2-LUT 980
3-LUT 1278
4-LUT 1126
Eliminating LUTs.
Number of LUTs: 3496
1-LUT 116
2-LUT 980
3-LUT 1274
4-LUT 1126
Combining LUTs.
Number of LUTs: 3235
1-LUT 116
2-LUT 655
3-LUT 1151
4-LUT 1313
Eliminated 4 LUTs.
Combined 261 LUTs.
<suppressed ~18820 debug messages>
75.44. Executing TECHMAP pass (map to technology primitives).
75.44.1. Executing Verilog-2005 frontend: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
75.44.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=3\LUT=8'01010011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101110011001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110100110010110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111010001000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001100110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000011101110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01011100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101010111000011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11000101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011101110111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100101011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000001001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10110010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100011101110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11101111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111001111110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000010111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011101111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111011111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'0111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011101110110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100111110100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011100100001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101110111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00011111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111101000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000010001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=2\LUT=4'1001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100010001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100101000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111101000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000000000010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110110000110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111110111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111010111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111100000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010101111101010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'01000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101110011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000110011001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000001111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000001110111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011101100001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011110011001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111110001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000011111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10111100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011100001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110011001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000100011110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1101000000110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111110110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000101010100010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'10101100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000100000001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100010011110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111011101000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000001110111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000000101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000010111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0010001010001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010101010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100111110110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111111110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111110000001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111100110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010000011001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111111100001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'00011000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001010111111100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000011111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=3\LUT=8'11100111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111110011111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001100100111100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001011010010110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011101000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000000001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100010111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100111000001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101000000011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111000111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000011110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011111111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101011111100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111001011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1011000000110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101111111110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010001111001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000110000001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001001100111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111001100000101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000000000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0110000000001100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000111111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001010000101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111011101110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000000011111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0111111110000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110111111111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111000001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1100010100110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010000000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000000100110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0010100000101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110010100011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000101010100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101001101011100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0101110001010011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010101011000011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010001000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0001000101000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100101110110100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1001110010011100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000010100110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1110101110111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000111100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0000001100001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1000101110111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0100000100010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0010000100010010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011010100000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'0011101100110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1010110000000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=4\LUT=16'1111010001001011 for cells of type $lut.
No more expansions possible.
<suppressed ~6202 debug messages>
Removed 0 unused cells and 6881 unused wires.
75.45. Executing AUTONAME pass.
Renamed 177025 objects in module top (114 iterations).
<suppressed ~8212 debug messages>
75.46. Executing HIERARCHY pass (managing design hierarchy).
75.46.1. Analyzing design hierarchy..
Top module: \top
75.46.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
75.47. Printing statistics.
=== top ===
Number of wires: 3754
Number of wire bits: 18322
Number of public wires: 3754
Number of public wire bits: 18322
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 6238
SB_CARRY 688
SB_DFF 317
SB_DFFE 577
SB_DFFER 431
SB_DFFES 44
SB_DFFESR 219
SB_DFFESS 41
SB_DFFR 131
SB_DFFS 49
SB_DFFSR 375
SB_DFFSS 31
SB_GB 2
SB_GB_IO 1
SB_IO 25
SB_LEDDA_IP 1
SB_LUT4 3274
SB_MAC16 4
SB_PLL40_CORE 1
SB_RAM40_4K 16
SB_RAM40_4KNR 4
SB_RGBA_DRV 1
SB_SPI 1
SB_SPRAM256KA 4
SB_WARMBOOT 1
75.48. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.
75.49. Executing JSON backend.
Warnings: 10 unique messages, 18 total
End of script. Logfile hash: 0db8e0128d, CPU: user 17.19s system 0.14s, MEM: 289.07 MB peak
Yosys 0.9+3568 (open-tool-forge build) (git sha1 859e52af, gcc 9.3.0-10ubuntu2 -Os)
Time spent: 21% 40x opt_expr (3 sec), 17% 31x opt_clean (3 sec), ...
nextpnr-ice40 --pre-pack data/clocks.py --pre-pack data/opt.py --seed 15 --no-promote-globals --timing-allow-fail \
--up5k --package sg48 \
-l /build/gateware/icE1usb/build-tmp/icE1usb.pnr.rpt \
--json /build/gateware/icE1usb/build-tmp/icE1usb.json \
--pcf /build/gateware/icE1usb/data/top-ice1usb.pcf \
--asc /build/gateware/icE1usb/build-tmp/icE1usb.asc
Info: constrained 'e1A_rx_hi_p' to bel 'X8/Y31/io0'
Warning: unmatched constraint 'e1A_rx_hi_n' (on line 3)
Info: constrained 'e1A_rx_lo_p' to bel 'X16/Y31/io0'
Warning: unmatched constraint 'e1A_rx_lo_n' (on line 5)
Info: constrained 'e1A_tx_hi' to bel 'X9/Y31/io0'
Info: constrained 'e1A_tx_lo' to bel 'X9/Y31/io1'
Info: constrained 'e1B_rx_hi_p' to bel 'X19/Y31/io0'
Warning: unmatched constraint 'e1B_rx_hi_n' (on line 10)
Info: constrained 'e1B_rx_lo_p' to bel 'X18/Y31/io0'
Warning: unmatched constraint 'e1B_rx_lo_n' (on line 12)
Info: constrained 'e1B_tx_hi' to bel 'X13/Y31/io1'
Info: constrained 'e1B_tx_lo' to bel 'X13/Y31/io0'
Info: constrained 'e1_rx_bias[0]' to bel 'X17/Y31/io0'
Info: constrained 'e1_rx_bias[1]' to bel 'X12/Y31/io1'
Info: constrained 'usb_dp' to bel 'X16/Y0/io0'
Info: constrained 'usb_dn' to bel 'X15/Y0/io0'
Info: constrained 'usb_pu' to bel 'X17/Y0/io0'
Info: constrained 'flash_mosi' to bel 'X23/Y0/io0'
Info: constrained 'flash_miso' to bel 'X23/Y0/io1'
Info: constrained 'flash_clk' to bel 'X24/Y0/io0'
Info: constrained 'flash_cs_n' to bel 'X24/Y0/io1'
Info: constrained 'e1_led_rclk' to bel 'X22/Y0/io1'
Info: constrained 'gps_reset_n' to bel 'X13/Y0/io1'
Info: constrained 'gps_rx' to bel 'X6/Y0/io0'
Info: constrained 'gps_tx' to bel 'X5/Y0/io0'
Info: constrained 'gps_pps' to bel 'X8/Y0/io0'
Info: constrained 'i2c_sda' to bel 'X9/Y0/io1'
Info: constrained 'i2c_scl' to bel 'X9/Y0/io0'
Info: constrained 'gpio[0]' to bel 'X19/Y0/io0'
Info: constrained 'gpio[1]' to bel 'X19/Y0/io1'
Info: constrained 'gpio[2]' to bel 'X21/Y0/io1'
Info: constrained 'clk_in' to bel 'X6/Y0/io1'
Info: constrained 'clk_tune_hi' to bel 'X7/Y0/io0'
Info: constrained 'clk_tune_lo' to bel 'X7/Y0/io1'
Info: constrained 'dbg_rx' to bel 'X18/Y0/io1'
Info: constrained 'dbg_tx' to bel 'X18/Y0/io0'
Info: constrained 'rgb[0]' to bel 'X4/Y31/io0'
Info: constrained 'rgb[1]' to bel 'X5/Y31/io0'
Info: constrained 'rgb[2]' to bel 'X6/Y31/io0'
Info: constraining clock net 'clk_sys' to 30.72 MHz
Info: constraining clock net 'clk_48m' to 48.00 MHz
1 251 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='wb_ack[1]', ena=None, clk='clk_sys')
--------------
0 252 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='spi_mux_I.srio_dat_o_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
1 257 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='soc_I.wb_ack[1]', ena=None, clk='clk_sys')
--------------
0 72 ControlSet(rs=None, ena=None, clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.tx_ll_I.lvl_prev_SB_DFFSS_Q_S', ena=None, clk='clk_48m')
--------------
1 73 ControlSet(rs=None, ena=None, clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O[1]', ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m')
1 12 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.tx_ll_I.ll_ack_SB_LUT4_I2_O_SB_LUT4_I2_O[1]', ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m')
--------------
2 75 ControlSet(rs=None, ena=None, clk='clk_48m')
2 ControlSet(rs='soc_I.usb_I.rx_pkt_I.state[0]', ena='soc_I.usb_I.rx_pkt_I.crc5_ok_SB_DFFESR_Q_E', clk='clk_48m')
--------------
3 80 ControlSet(rs=None, ena=None, clk='clk_48m')
5 ControlSet(rs='soc_I.usb_I.rx_pkt_I.state[0]', ena='soc_I.usb_I.rx_pkt_I.bit_cnt_SB_DFFESR_Q_E', clk='clk_48m')
--------------
0 82 ControlSet(rs=None, ena=None, clk='clk_48m')
2 ControlSet(rs='soc_I.usb_I.rx_ll_I.samp_sync', ena=None, clk='clk_48m')
--------------
0 83 ControlSet(rs=None, ena=None, clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.rx_ll_I.samp_cnt_SB_DFFSR_Q_R', ena=None, clk='clk_48m')
--------------
0 84 ControlSet(rs=None, ena=None, clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_LUT4_I2_O[1]', ena='soc_I.usb_I.rx_pkt_I.crc_in_first_SB_DFFESS_Q_E', clk='clk_48m')
--------------
5 15 ControlSet(rs=None, ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_eop_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_rep_state_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sym_same_0_SB_LUT4_I3_1_O', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
1 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sym_se_0', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
3 87 ControlSet(rs=None, ena=None, clk='clk_48m')
3 ControlSet(rs='soc_I.usb_I.rx_ll_I.dec_sync_1_SB_DFFESR_Q_R', ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
--------------
0 86 ControlSet(rs=None, ena=None, clk='clk_48m')
2 ControlSet(rs='soc_I.usb_I.eps_write_0', ena=None, clk='clk_48m')
--------------
0 89 ControlSet(rs=None, ena=None, clk='clk_48m')
3 ControlSet(rs='soc_I.usb_I.eps_bus_clear', ena=None, clk='clk_48m')
--------------
0 94 ControlSet(rs=None, ena=None, clk='clk_48m')
5 ControlSet(rs='soc_I.usb_I.csr_bus_clear', ena=None, clk='clk_48m')
--------------
0 264 ControlSet(rs=None, ena=None, clk='clk_sys')
7 ControlSet(rs='soc_I.uart_I.ub_rdata_SB_DFFSR_Q_9_R', ena=None, clk='clk_sys')
--------------
0 265 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', ena=None, clk='clk_sys')
--------------
4 270 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='soc_I.uart_I.uart_tx_I.bit_cnt_SB_DFFESS_Q_S', ena='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', clk='clk_sys')
--------------
4 275 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='soc_I.uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_S', ena='soc_I.uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_E', clk='clk_sys')
--------------
1 276 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_store_SB_DFFESS_Q_E', clk='clk_sys')
--------------
0 277 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_stalu_SB_DFFESR_Q_E', clk='clk_sys')
--------------
5 282 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_rd_SB_DFFESS_Q_E', clk='clk_sys')
--------------
2 284 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_is_lh_SB_DFFESR_Q_E', clk='clk_sys')
--------------
1 285 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.latched_branch_SB_DFFESR_Q_E', clk='clk_sys')
--------------
1 286 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.is_beq_bne_blt_bge_bltu_bgeu_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 13 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys')
1 ControlSet(rs='soc_I.iobuf_I.dma_I.len_ld', ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys')
1 287 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.iobuf_I.dma_I.len_ld', ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys')
--------------
0 288 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.e1_I.wb_rdata_SB_DFFSR_Q_14_R', ena=None, clk='clk_sys')
--------------
0 292 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_DFF_D_Q_SB_LUT4_I3_2_O', ena=None, clk='clk_sys')
--------------
0 295 ControlSet(rs=None, ena=None, clk='clk_sys')
3 ControlSet(rs='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E_SB_LUT4_I2_O', ena=None, clk='clk_sys')
--------------
0 299 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
0 301 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_3_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys')
--------------
0 303 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_1_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys')
--------------
0 307 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O', ena=None, clk='clk_sys')
--------------
0 309 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_I2_SB_LUT4_I3_O_SB_DFFSR_R_3_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys')
--------------
0 311 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_I2_SB_LUT4_I3_O_SB_DFFSR_R_1_Q_SB_LUT4_I2_O', ena=None, clk='clk_sys')
--------------
0 315 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_I2_SB_LUT4_I3_O', ena=None, clk='clk_sys')
--------------
4 320 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_1_D_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_DFFESS_Q_E', clk='clk_sys')
--------------
6 327 ControlSet(rs=None, ena=None, clk='clk_sys')
7 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I0_O_SB_LUT4_I3_I0_SB_DFFESS_Q_D_SB_LUT4_I3_I2_SB_DFFESR_D_Q_SB_LUT4_I2_O_SB_LUT4_I2_O', clk='clk_sys')
--------------
5 334 ControlSet(rs=None, ena=None, clk='clk_sys')
7 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I0_O_SB_LUT4_I3_I0_SB_DFFESS_Q_D_SB_LUT4_I3_I2_SB_DFFESR_D_E', clk='clk_sys')
--------------
0 335 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_DFF_D_Q[0]', ena=None, clk='clk_sys')
--------------
3 19 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I1_SB_LUT4_I3_O_SB_DFFS_D_Q', ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I1_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_buf_I.buf_tx_re_SB_LUT4_O_I3', clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I1_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_1_I3_SB_DFFR_Q_D_SB_LUT4_O_I3_SB_DFF_Q_D_SB_LUT4_O_I3[1]', clk='clk_sys')
4 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I1_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I2_SB_LUT4_O_I3_SB_LUT4_I2_O', clk='clk_sys')
--------------
0 336 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I1_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I2_O', clk='clk_sys')
--------------
1 337 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I1_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I2_I1_SB_LUT4_I2_O', clk='clk_sys')
--------------
0 338 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.mem_state_SB_DFFESR_Q_R', ena='soc_I.cpu_I.mem_valid_SB_DFFESR_Q_E', clk='clk_sys')
--------------
2 340 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='soc_I.cpu_I.mem_state_SB_DFFESR_Q_R', ena='soc_I.cpu_I.mem_state_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 341 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.mem_do_wdata_SB_DFFESS_Q_S[1]', ena='soc_I.cpu_I.mem_do_wdata_SB_DFFESS_Q_E', clk='clk_sys')
--------------
1 342 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.is_sll_srl_sra_SB_LUT4_I1_I2_SB_LUT4_I1_O[3]', ena='soc_I.cpu_I.mem_do_rinst_SB_DFFESS_Q_E', clk='clk_sys')
--------------
0 343 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.instr_sb_SB_LUT4_I1_I3[0]', ena='soc_I.cpu_I.mem_do_prefetch_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 344 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.instr_or_SB_DFFESR_Q_E', ena=None, clk='clk_sys')
--------------
0 345 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.instr_lbu_SB_LUT4_I3_O[3]', ena='soc_I.cpu_I.mem_do_rdata_SB_DFFESS_Q_E', clk='clk_sys')
--------------
0 346 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.decoder_pseudo_trigger_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
0 347 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='soc_I.cpu_I.alu_wait_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
1 192 ControlSet(rs='rst_sys', ena=None, clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys')
3 ControlSet(rs='rst_sys', ena='misc_I.bus_we_boot', clk='clk_sys')
3 ControlSet(rs='rst_sys', ena='misc_I.dfu_I.wb_sel_SB_DFFER_Q_E', clk='clk_sys')
7 ControlSet(rs='rst_sys', ena='misc_I.tick_e1_SB_DFF_Q_D_SB_LUT4_O_I3_SB_DFFER_Q_E', clk='clk_sys')
2 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E', clk='clk_sys')
2 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.dma_I.state_SB_DFFER_Q_E', clk='clk_sys')
3 ControlSet(rs='rst_sys', ena='soc_I.rgb_I.led_ctrl_SB_DFFER_Q_E', clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_fifo_I.rd_valid_SB_DFFER_Q_E[1]', clk='clk_sys')
--------------
0 348 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_I.gf_I.state_SB_DFFESS_Q_E', clk='clk_sys')
--------------
1 349 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='i2c_I.core_I.sda_oe_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 350 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='i2c_I.core_I.scl_oe_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 351 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_I.gf_I.state_SB_DFFESS_Q_E', clk='clk_sys')
--------------
5 67 ControlSet(rs='rst_48m', ena=None, clk='clk_48m')
3 ControlSet(rs='rst_48m', ena='soc_I.usb_I.tx_ll_I.state_SB_DFFER_Q_E', clk='clk_48m')
2 ControlSet(rs='rst_48m', ena='soc_I.usb_I.tx_ll_I.br_cnt[2]', clk='clk_48m')
--------------
0 352 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='misc_I.tick_e1_SB_DFFSS_Q_S[2]', ena='misc_I.tick_e1_SB_DFFSS_Q_S_SB_LUT4_I3_O', clk='clk_sys')
--------------
0 353 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='misc_I.tick_e1_SB_DFFSS_Q_S[2]', ena=None, clk='clk_sys')
--------------
0 354 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='misc_I.tick_e1_SB_DFFSS_Q_D[2]', ena='misc_I.tick_e1_SB_DFFSS_Q_D_SB_LUT4_I3_O', clk='clk_sys')
--------------
0 355 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='misc_I.pps_flt_I.state_SB_LUT4_I1_O[1]', ena='misc_I.pps_flt_I.state_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 356 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='misc_I.dfu_I.btn_flt_I.fall_SB_DFF_Q_D', ena='misc_I.dfu_I.btn_flt_I.state_SB_DFFESR_Q_E', clk='clk_sys')
--------------
0 361 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='i2c_I.core_I.cyc_cnt_SB_DFFSR_Q_R', ena=None, clk='clk_sys')
--------------
2 364 ControlSet(rs=None, ena=None, clk='clk_sys')
3 ControlSet(rs='i2c_I.core_I.bit_cnt_SB_DFFESR_Q_R[1]', ena='i2c_I.core_I.bit_last_SB_DFFE_Q_E', clk='clk_sys')
--------------
0 371 ControlSet(rs=None, ena=None, clk='clk_sys')
7 ControlSet(rs='gps_uart_I.ub_rdata_SB_DFFSR_Q_9_R', ena=None, clk='clk_sys')
--------------
0 372 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='gps_uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', ena=None, clk='clk_sys')
--------------
4 377 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='gps_uart_I.uart_tx_I.bit_cnt_SB_DFFESS_Q_S', ena='gps_uart_I.uart_tx_I.ce_SB_LUT4_I2_O[2]', clk='clk_sys')
--------------
4 382 ControlSet(rs=None, ena=None, clk='clk_sys')
5 ControlSet(rs='gps_uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_S', ena='gps_uart_I.uart_rx_I.bit_cnt_SB_DFFESS_Q_E', clk='clk_sys')
--------------
3 386 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_E[0]', clk='clk_sys')
--------------
0 387 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='soc_I.e1_I.lb_bit_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_DFFESR_Q_E', clk='clk_sys')
--------------
1 389 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='e1A_rx_lo_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O_SB_LUT4_I2_O', clk='clk_sys')
--------------
1 391 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O_SB_LUT4_I2_O', clk='clk_sys')
--------------
1 395 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs=None, ena='tick_e1[0]', clk='clk_sys')
--------------
0 96 ControlSet(rs=None, ena=None, clk='clk_48m')
2 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_data_crc_SB_DFFE_Q_E', clk='clk_48m')
--------------
1 100 ControlSet(rs=None, ena=None, clk='clk_48m')
4 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.mc_op_tx', clk='clk_48m')
--------------
4 104 ControlSet(rs=None, ena=None, clk='clk_48m')
4 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.mc_op_ld', clk='clk_48m')
--------------
2 111 ControlSet(rs=None, ena=None, clk='clk_48m')
7 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.epfw_issue_wb_SB_LUT4_I0_O_SB_LUT4_O_1_I3[0]', clk='clk_48m')
--------------
1 117 ControlSet(rs=None, ena=None, clk='clk_48m')
6 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.ep_bd_dual_SB_LUT4_I2_O[2]', clk='clk_48m')
--------------
3 120 ControlSet(rs=None, ena=None, clk='clk_48m')
3 ControlSet(rs=None, ena='soc_I.usb_I.trans_I.bd_state_SB_DFFE_Q_E', clk='clk_48m')
--------------
0 124 ControlSet(rs=None, ena=None, clk='clk_48m')
4 ControlSet(rs=None, ena='soc_I.usb_I.rxpkt_done_ok', clk='clk_48m')
--------------
0 127 ControlSet(rs=None, ena=None, clk='clk_48m')
3 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.llu_byte_stb_SB_LUT4_I2_2_O[1]', clk='clk_48m')
--------------
0 396 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ld', clk='clk_sys')
--------------
1 400 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs=None, ena='soc_I.e1_buf_I.buf_rx_we_SB_LUT4_O_I3_SB_DFFSR_Q_D_SB_LUT4_O_I1', clk='clk_sys')
--------------
0 404 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs=None, ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_1_D_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_LUT4_I0_O[0]', clk='clk_sys')
--------------
1 405 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs=None, ena='soc_I.cpu_I.reg_op1_SB_DFFE_Q_31_E', clk='clk_sys')
--------------
2 407 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs=None, ena='soc_I.cpu_I.instr_sra_SB_LUT4_I2_O_SB_LUT4_I0_1_O[1]', clk='clk_sys')
--------------
4 411 ControlSet(rs=None, ena=None, clk='clk_sys')
4 ControlSet(rs=None, ena='soc_I.bridge_I.ram_rdy_SB_LUT4_I0_O[1]', clk='clk_sys')
--------------
0 413 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs=None, ena='misc_I.bus_we_tick_sel', clk='clk_sys')
--------------
0 415 ControlSet(rs=None, ena=None, clk='clk_sys')
2 ControlSet(rs=None, ena='i2c_I.stb', clk='clk_sys')
--------------
1 416 ControlSet(rs=None, ena=None, clk='clk_sys')
1 ControlSet(rs=None, ena='i2c_I.core_I.bit_last_SB_DFFE_Q_E', clk='clk_sys')
--------------
Control Set Optimizer: cost 96 to reduce control sets from 206 to 100
Total control sets: 100
1 2
3 1
4 1
6 1
8 14
9 21
10 12
11 3
12 3
13 5
14 2
15 2
16 5
17 2
18 1
19 1
20 4
24 1
25 1
28 1
29 1
31 2
32 5
33 2
45 1
55 1
60 1
67 1
127 1
192 1
416 1
1 ControlSet(rs='sys_mgr_I.pll_lock_SB_LUT4_I3_O', ena=None, clk='clk_sys')
1 ControlSet(rs='sys_mgr_I.rst_30m72_i', ena=None, clk='clk_48m')
3 ControlSet(rs='sys_mgr_I.pll_lock_SB_LUT4_I3_O', ena='sys_mgr_I.rst_30m72_i', clk='clk_sys')
4 ControlSet(rs='soc_I.usb_I.txll_start', ena='soc_I.usb_I.tx_ll_I.br_cnt[2]', clk='clk_48m')
6 ControlSet(rs='rst_sys', ena=None, clk='clk_48m')
8 ControlSet(rs=None, ena='spi_mux_I.shift_ce', clk='clk_sys')
8 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.llu_byte_stb_SB_LUT4_I2_O[1]', clk='clk_48m')
8 ControlSet(rs=None, ena='soc_I.e1_buf_I.t_done[2]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[2]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[4]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[3]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[4]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[3]', clk='clk_sys')
8 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_I1', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I0_O_SB_LUT4_I3_I0_SB_DFFESS_Q_D_SB_LUT4_I3_I2_SB_LUT4_I2_O', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I0_SB_LUT4_I1_O[1]', clk='clk_sys')
8 ControlSet(rs='misc_I.wb_ack_SB_LUT4_I2_O_SB_LUT4_I2_O', ena=None, clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[2]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I1_SB_LUT4_I1_O[1]', clk='clk_sys')
8 ControlSet(rs='rst_sys', ena='misc_I.bus_we_gpio', clk='clk_sys')
9 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.pid_cap', clk='clk_48m')
9 ControlSet(rs='soc_I.uart_I.ub_rdata_rst', ena=None, clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.ub_wr_data', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_fifo_I.ram_rd_ena', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_tx_I.ce_SB_LUT4_I3_O', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.urf_wren', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='soc_I.uart_I.uart_rx_fifo_I.ram_rd_ena', clk='clk_sys')
9 ControlSet(rs=None, ena='soc_I.uart_I.uart_rx_I.ce', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_e1[0]', clk='clk_sys')
9 ControlSet(rs='gps_uart_I.ub_rdata_rst', ena=None, clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_uart_I.ub_wr_data', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_I.ce_SB_LUT4_I3_O', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_tx_fifo_I.ram_rd_ena', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_e1[1]', clk='clk_sys')
9 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.m1_addr_ce', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_uart_I.uart_rx_fifo_I.ram_rd_ena', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='gps_uart_I.urf_wren', clk='clk_sys')
9 ControlSet(rs='rst_sys', ena='misc_I.bus_we_led', clk='clk_sys')
9 ControlSet(rs=None, ena='gps_uart_I.uart_rx_I.ce', clk='clk_sys')
9 ControlSet(rs=None, ena='tick_e1[2]', clk='clk_sys')
9 ControlSet(rs=None, ena='i2c_I.core_I.stb_SB_LUT4_I2_1_O', clk='clk_sys')
10 ControlSet(rs='soc_I.usb_I.trans_I.len_ld', ena=None, clk='clk_48m')
10 ControlSet(rs='rst_48m', ena='soc_I.usb_I.cr_bus_we', clk='clk_48m')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[2]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[1]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[2]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[1]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[4]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_5_I2_SB_LUT4_I1_O[3]', clk='clk_sys')
10 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I1_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_I.lb_bit_SB_LUT4_I1_I0_SB_LUT4_I0_O_SB_DFFR_D_Q_SB_LUT4_I3_O[2]', clk='clk_sys')
10 ControlSet(rs='i2c_I.bus_clr', ena=None, clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[3]', clk='clk_sys')
10 ControlSet(rs='rst_sys', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_I3_SB_LUT4_I1_O[4]', clk='clk_sys')
11 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.shift_now', clk='clk_48m')
11 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.len_dec', clk='clk_48m')
11 ControlSet(rs='soc_I.usb_I.trans_I.mc_op_zlen', ena=None, clk='clk_48m')
12 ControlSet(rs=None, ena='soc_I.uart_I.ub_wr_div', clk='clk_sys')
12 ControlSet(rs='misc_I.bus_clr', ena=None, clk='clk_sys')
12 ControlSet(rs=None, ena='gps_uart_I.ub_wr_div', clk='clk_sys')
13 ControlSet(rs=None, ena='soc_I.cpu_I.decoder_pseudo_trigger_SB_LUT4_I2_O[0]', clk='clk_sys')
13 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_clk[1]', clk='clk_sys')
13 ControlSet(rs='rst_sys', ena='misc_I.bus_we_pdm_clk[0]', clk='clk_sys')
13 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I1_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='soc_I.e1_buf_I.buf_tx_ts_SB_DFFES_Q_E', clk='clk_sys')
13 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.len_ce', clk='clk_sys')
14 ControlSet(rs=None, ena='soc_I.usb_I.ep_status_I.p_read_2', clk='clk_48m')
14 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.m0_addr_ce', clk='clk_sys')
15 ControlSet(rs=None, ena='soc_I.usb_I.rx_ll_I.samp_valid_0', clk='clk_48m')
15 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I1_SB_LUT4_I3_O_SB_DFFS_D_Q', ena='tick_e1[0]', clk='clk_sys')
16 ControlSet(rs='soc_I.wb_48m_xclk_I.s_cyc_SB_LUT4_I3_O', ena=None, clk='clk_sys')
16 ControlSet(rs=None, ena='soc_I.ub_ack', clk='clk_48m')
16 ControlSet(rs=None, ena='soc_I.usb_I.tx_pkt_I.crc_in_valid', clk='clk_48m')
16 ControlSet(rs='soc_I.usb_I.ep_status_I.s_zero_2', ena='soc_I.usb_I.ep_status_I.s_read_2', clk='clk_48m')
16 ControlSet(rs=None, ena='soc_I.e1_buf_tx_re[0]', clk='clk_sys')
17 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_DFF_D_Q[0]', ena='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_I0_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I3_O_SB_DFFSR_R_1_D_SB_LUT4_O_I3_SB_DFFESS_D_Q_SB_LUT4_I2_I3_SB_LUT4_I0_1_O', clk='clk_sys')
17 ControlSet(rs='soc_I.e1_I.bus_clr', ena=None, clk='clk_sys')
18 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.cpu_I.instr_or_SB_DFFESR_Q_E', clk='clk_sys')
19 ControlSet(rs='soc_I.e1_I.bus_rdata_SB_LUT4_O_12_I2_SB_LUT4_O_1_I1_SB_LUT4_I3_O_SB_DFFS_D_Q', ena=None, clk='clk_sys')
20 ControlSet(rs='soc_I.usb_I.oob_sof_SB_LUT4_I2_O', ena=None, clk='clk_48m')
20 ControlSet(rs='soc_I.usb_I.phy_I.rx_dn_SB_LUT4_I3_O', ena=None, clk='clk_48m')
20 ControlSet(rs='misc_I.wb_ack_SB_LUT4_I2_O_SB_LUT4_I3_O', ena=None, clk='clk_sys')
20 ControlSet(rs=None, ena='soc_I.cpu_I.trap_SB_LUT4_I3_O', clk='clk_sys')
24 ControlSet(rs=None, ena='soc_I.e1_buf_rx_we[0]', clk='clk_sys')
25 ControlSet(rs=None, ena='soc_I.e1_buf_I.t_busy_SB_LUT4_I3_O', clk='clk_sys')
28 ControlSet(rs='e1A_rx_hi_p_SB_IO_PACKAGE_PIN_D_IN_0_SB_DFF_D_Q_SB_LUT4_I0_1_O[1]', ena=None, clk='clk_sys')
29 ControlSet(rs=None, ena='soc_I.usb_I.rx_pkt_I.crc_in_valid', clk='clk_48m')
31 ControlSet(rs='soc_I.cpu_I.is_lui_auipc_jal_SB_DFF_Q_D_SB_LUT4_I2_O', ena='soc_I.cpu_I.decoder_pseudo_trigger_SB_LUT4_I2_O[0]', clk='clk_sys')
31 ControlSet(rs=None, ena='soc_I.cpu_I.latched_is_lh_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_I2_O', clk='clk_sys')
32 ControlSet(rs=None, ena='soc_I.iobuf_I.dma_I.ack_rd', clk='clk_sys')
32 ControlSet(rs=None, ena='soc_I.pb_rst_n_SB_LUT4_I2_O', clk='clk_sys')
32 ControlSet(rs='soc_I.bridge_I.wb_cyc_rst', ena=None, clk='clk_sys')
32 ControlSet(rs=None, ena='soc_I.cpu_I.trap_SB_LUT4_I2_O', clk='clk_sys')
32 ControlSet(rs=None, ena='soc_I.cpu_I.instr_ecall_ebreak_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[3]', clk='clk_sys')
33 ControlSet(rs=None, ena='soc_I.cpu_I.mem_do_rinst_SB_LUT4_I3_O', clk='clk_sys')
33 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena=None, clk='clk_sys')
45 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.epbam_arb_I.reselect', clk='clk_sys')
55 ControlSet(rs='rst_sys', ena='soc_I.iobuf_I.spram_arb_I.reselect', clk='clk_sys')
60 ControlSet(rs='soc_I.pb_rst_n_SB_LUT4_I3_O', ena='soc_I.pb_rst_n_SB_LUT4_I3_1_O', clk='clk_sys')
67 ControlSet(rs='rst_48m', ena=None, clk='clk_48m')
127 ControlSet(rs=None, ena=None, clk='clk_48m')
192 ControlSet(rs='rst_sys', ena=None, clk='clk_sys')
416 ControlSet(rs=None, ena=None, clk='clk_sys')
LUT replication: 0 new LUTs in 0 groups
Info: Packing constants..
Info: Packing IOs..
Info: clk_in feeds SB_IO sys_mgr_I.gb_in, removing $nextpnr_ibuf clk_in.
Info: clk_tune_hi feeds SB_IO misc_I.pdm_clk_I[1].io_reg_I, removing $nextpnr_obuf clk_tune_hi.
Info: clk_tune_lo feeds SB_IO misc_I.pdm_clk_I[0].io_reg_I, removing $nextpnr_obuf clk_tune_lo.
Info: e1A_rx_hi_p feeds SB_IO e1A_rx_hi_p_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_hi_p.
Info: e1A_rx_lo_p feeds SB_IO e1A_rx_lo_p_SB_IO_PACKAGE_PIN, removing $nextpnr_ibuf e1A_rx_lo_p.
Info: e1A_tx_hi feeds SB_IO e1A_tx_hi_SB_IO_PACKAGE_PIN, removing $nextpnr_obuf e1A_tx_hi.
Info: e1A_tx_lo feeds SB_IO e1A_tx_lo_SB_IO_PACKAGE_PIN, removing $nextpnr_obuf e1A_tx_lo.
Info: e1B_rx_hi_p feeds SB_IO e1_dummy_rx_I[1], removing $nextpnr_ibuf e1B_rx_hi_p.
Info: e1B_rx_lo_p feeds SB_IO e1_dummy_rx_I[0], removing $nextpnr_ibuf e1B_rx_lo_p.
Info: e1B_tx_hi feeds SB_IO e1_dummy_tx_I[1], removing $nextpnr_obuf e1B_tx_hi.
Info: e1B_tx_lo feeds SB_IO e1_dummy_tx_I[0], removing $nextpnr_obuf e1B_tx_lo.
Info: e1_led_rclk feeds SB_IO spi_mux_I.iob_I[0], removing $nextpnr_iobuf e1_led_rclk.
Info: flash_clk feeds SB_IO spi_mux_I.iob_I[1], removing $nextpnr_iobuf flash_clk.
Info: flash_miso feeds SB_IO spi_mux_I.iob_I[2], removing $nextpnr_iobuf flash_miso.
Info: flash_mosi feeds SB_IO spi_mux_I.iob_I[3], removing $nextpnr_iobuf flash_mosi.
Info: gps_pps feeds SB_IO misc_I.pps_iob_I, removing $nextpnr_ibuf gps_pps.
Info: gps_reset_n feeds SB_IO misc_I.gpio_iob_I[3], removing $nextpnr_obuf gps_reset_n.
Info: i2c_scl feeds SB_IO i2c_iob_I[1], removing $nextpnr_iobuf i2c_scl.
Info: i2c_sda feeds SB_IO i2c_iob_I[0], removing $nextpnr_iobuf i2c_sda.
Info: usb_dn feeds SB_IO soc_I.usb_I.phy_I.io_dn_I, removing $nextpnr_iobuf usb_dn.
Info: usb_dp feeds SB_IO soc_I.usb_I.phy_I.io_dp_I, removing $nextpnr_iobuf usb_dp.
Info: gpio[0] feeds SB_IO misc_I.gpio_iob_I[0], removing $nextpnr_iobuf gpio[0].
Info: gpio[1] feeds SB_IO misc_I.gpio_iob_I[1], removing $nextpnr_iobuf gpio[1].
Info: gpio[2] feeds SB_IO misc_I.gpio_iob_I[2], removing $nextpnr_iobuf gpio[2].
Info: e1_rx_bias[0] feeds SB_IO misc_I.pdm_e1_I[0].io_reg_I, removing $nextpnr_obuf e1_rx_bias[0].
Info: e1_rx_bias[1] feeds SB_IO misc_I.pdm_e1_I[1].io_reg_I, removing $nextpnr_obuf e1_rx_bias[1].
Info: rgb[0] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO
Info: rgb[1] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO
Info: rgb[2] use by SB_RGBA_DRV/SB_RGB_DRV soc_I.rgb_I.rgb_drv_I, not creating SB_IO
Info: Packing LUT-FFs..
Info: 1753 LCs used as LUT4 only
Info: 1706 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info: 509 LCs used as DFF only
Info: Packing carries..
Info: 238 LCs used as CARRY only
Info: Packing RAMs..
Info: Placing PLLs..
Info: constrained PLL 'sys_mgr_I.pll_I' to X12/Y31/pll_3
Info: Packing special functions..
Info: constrained SB_LEDDA_IP 'soc_I.rgb_I.led_I' to X0/Y31/ledda_ip_2
Info: constrained SB_RGBA_DRV 'soc_I.rgb_I.rgb_drv_I' to X0/Y30/rgba_drv_0
Info: constrained SB_SPI 'soc_I.spi_I.spi_I' to X0/Y0/spi_0
Info: PLL 'sys_mgr_I.pll_I' has LOCK output, need to pass all outputs via LUT
Info: constrained 'sys_mgr_I.pll_lock_SB_LUT4_I3_LC' to X1/Y30/lc0
Info: Constraining chains...
Info: 215 LCs used to legalise carry chains.
Info: Checksum: 0xd938666b
Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0x0f7a1cae
Info: Device utilisation:
Info: ICESTORM_LC: 4426/ 5280 83%
Info: ICESTORM_RAM: 20/ 30 66%
Info: SB_IO: 32/ 96 33%
Info: SB_GB: 4/ 8 50%
Info: ICESTORM_PLL: 1/ 1 100%
Info: SB_WARMBOOT: 1/ 1 100%
Info: ICESTORM_DSP: 4/ 8 50%
Info: ICESTORM_HFOSC: 0/ 1 0%
Info: ICESTORM_LFOSC: 0/ 1 0%
Info: SB_I2C: 0/ 2 0%
Info: SB_SPI: 1/ 2 50%
Info: IO_I3C: 0/ 2 0%
Info: SB_LEDDA_IP: 1/ 1 100%
Info: SB_RGBA_DRV: 1/ 1 100%
Info: ICESTORM_SPRAM: 4/ 4 100%
Info: Placed 39 cells based on constraints.
Info: Creating initial analytic placement for 3561 cells, random placement wirelen = 108112.
Info: at initial placer iter 0, wirelen = 3359
Info: at initial placer iter 1, wirelen = 3187
Info: at initial placer iter 2, wirelen = 3218
Info: at initial placer iter 3, wirelen = 3174
Info: Running main analytical placer.
Info: at iteration #1, type ALL: wirelen solved = 3225, spread = 36302, legal = 45997; time = 0.29s
Info: at iteration #2, type ALL: wirelen solved = 4731, spread = 29183, legal = 42303; time = 0.19s
Info: at iteration #3, type ALL: wirelen solved = 5986, spread = 28573, legal = 38881; time = 0.23s
Info: at iteration #4, type ALL: wirelen solved = 7185, spread = 27170, legal = 41047; time = 0.23s
Info: at iteration #5, type ALL: wirelen solved = 7838, spread = 26131, legal = 38521; time = 0.16s
Info: at iteration #6, type ALL: wirelen solved = 8327, spread = 25977, legal = 38273; time = 0.15s
Info: at iteration #7, type ALL: wirelen solved = 9064, spread = 25667, legal = 35890; time = 0.16s
Info: at iteration #8, type ALL: wirelen solved = 9582, spread = 25329, legal = 36513; time = 0.15s
Info: at iteration #9, type ALL: wirelen solved = 9855, spread = 25451, legal = 34606; time = 0.13s
Info: at iteration #10, type ALL: wirelen solved = 10500, spread = 25934, legal = 37785; time = 0.14s
Info: at iteration #11, type ALL: wirelen solved = 10839, spread = 25905, legal = 42770; time = 0.21s
Info: at iteration #12, type ALL: wirelen solved = 10731, spread = 25810, legal = 42510; time = 0.27s
Info: at iteration #13, type ALL: wirelen solved = 11513, spread = 25742, legal = 47012; time = 0.23s
Info: at iteration #14, type ALL: wirelen solved = 11435, spread = 25901, legal = 36842; time = 0.12s
Info: HeAP Placer Time: 3.22s
Info: of which solving equations: 0.86s
Info: of which spreading cells: 0.16s
Info: of which strict legalisation: 1.75s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 664, wirelen = 34606
Info: at iteration #5: temp = 0.000000, timing cost = 512, wirelen = 28896
Info: at iteration #10: temp = 0.000000, timing cost = 557, wirelen = 27672
Info: at iteration #15: temp = 0.000000, timing cost = 517, wirelen = 26810
Info: at iteration #20: temp = 0.000000, timing cost = 503, wirelen = 26370
Info: at iteration #25: temp = 0.000000, timing cost = 517, wirelen = 26268
Info: at iteration #30: temp = 0.000000, timing cost = 517, wirelen = 26199
Info: at iteration #35: temp = 0.000000, timing cost = 515, wirelen = 26182
Info: at iteration #38: temp = 0.000000, timing cost = 516, wirelen = 26163
Info: SA placement time 6.82s
Info: Max frequency for clock 'clk_sys': 33.75 MHz (PASS at 30.72 MHz)
Info: Max frequency for clock 'clk_48m': 52.63 MHz (PASS at 48.00 MHz)
Info: Max delay <async> -> posedge clk_sys: 7.02 ns
Info: Max delay posedge clk_48m -> <async> : 4.69 ns
Info: Max delay posedge clk_48m -> posedge clk_sys: 6.45 ns
Info: Max delay posedge clk_sys -> <async> : 10.88 ns
Info: Max delay posedge clk_sys -> posedge clk_48m: 15.97 ns
Info: Slack histogram:
Info: legend: * represents 51 endpoint(s)
Info: + represents [1,51) endpoint(s)
Info: [ 1833, 5751) |+
Info: [ 5751, 9669) |*****+
Info: [ 9669, 13587) |***********+
Info: [ 13587, 17505) |**********************************+
Info: [ 17505, 21423) |*************************+
Info: [ 21423, 25341) |***********************************+
Info: [ 25341, 29259) |************************************************************
Info: [ 29259, 33177) |*+
Info: [ 33177, 37095) |
Info: [ 37095, 41013) |
Info: [ 41013, 44931) |
Info: [ 44931, 48849) |
Info: [ 48849, 52767) |
Info: [ 52767, 56685) |
Info: [ 56685, 60603) |
Info: [ 60603, 64521) |
Info: [ 64521, 68439) |
Info: [ 68439, 72357) |
Info: [ 72357, 76275) |+
Info: [ 76275, 80193) |+
Info: Checksum: 0xad23747b
Info: Routing..
Info: Setting up routing queue.
Info: Routing 15233 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 38 961 | 38 961 | 14273| 0.14 0.14|
Info: 2000 | 53 1946 | 15 985 | 13291| 0.07 0.22|
Info: 3000 | 135 2864 | 82 918 | 12383| 0.18 0.40|
Info: 4000 | 245 3754 | 110 890 | 11502| 0.21 0.61|
Info: 5000 | 396 4603 | 151 849 | 10699| 0.22 0.83|
Info: 6000 | 561 5438 | 165 835 | 9920| 0.26 1.09|
Info: 7000 | 784 6215 | 223 777 | 9227| 0.29 1.39|
Info: 8000 | 995 7004 | 211 789 | 8514| 0.20 1.59|
Info: 9000 | 1228 7771 | 233 767 | 7864| 0.25 1.84|
Info: 10000 | 1678 8321 | 450 550 | 7472| 0.38 2.22|
Info: 11000 | 2090 8909 | 412 588 | 7101| 0.41 2.63|
Info: 12000 | 2535 9464 | 445 555 | 6848| 0.48 3.11|
Info: 13000 | 2982 10017 | 447 553 | 6548| 0.46 3.57|
Info: 14000 | 3430 10569 | 448 552 | 6227| 0.46 4.03|
Info: 15000 | 4023 10976 | 593 407 | 6105| 0.50 4.52|
Info: 16000 | 4367 11632 | 344 656 | 5633| 0.38 4.91|
Info: 17000 | 4714 12285 | 347 653 | 5157| 0.41 5.31|
Info: 18000 | 5048 12951 | 334 666 | 4613| 0.54 5.85|
Info: 19000 | 5557 13442 | 509 491 | 4425| 0.98 6.84|
Info: 20000 | 6024 13975 | 467 533 | 4234| 0.98 7.81|
Info: 21000 | 6580 14419 | 556 444 | 4106| 0.72 8.53|
Info: 22000 | 7091 14908 | 511 489 | 3948| 0.74 9.28|
Info: 23000 | 7654 15345 | 563 437 | 3899| 0.56 9.83|
Info: 24000 | 8236 15763 | 582 418 | 3845| 0.72 10.56|
Info: 25000 | 8809 16190 | 573 427 | 3821| 0.63 11.18|
Info: 26000 | 9343 16656 | 534 466 | 3713| 0.50 11.69|
Info: 27000 | 9908 17091 | 565 435 | 3674| 0.67 12.35|
Info: 28000 | 10421 17578 | 513 487 | 3587| 0.50 12.85|
Info: 29000 | 11005 17994 | 584 416 | 3556| 0.66 13.51|
Info: 30000 | 11505 18494 | 500 500 | 3407| 0.56 14.07|
Info: 31000 | 12012 18987 | 507 493 | 3215| 0.67 14.74|
Info: 32000 | 12555 19444 | 543 457 | 3110| 0.66 15.40|
Info: 33000 | 13059 19940 | 504 496 | 2866| 0.78 16.18|
Info: 34000 | 13672 20327 | 613 387 | 2840| 0.63 16.80|
Info: 35000 | 14213 20786 | 541 459 | 2666| 0.66 17.46|
Info: 36000 | 14790 21209 | 577 423 | 2566| 0.81 18.27|
Info: 37000 | 15151 21848 | 361 639 | 2084| 0.34 18.61|
Info: 38000 | 15439 22560 | 288 712 | 1439| 0.29 18.90|
Info: 39000 | 15884 23115 | 445 555 | 1055| 2.21 21.11|
Info: 40000 | 16258 23741 | 374 626 | 714| 0.95 22.06|
Info: 41000 | 16653 24346 | 395 605 | 331| 0.74 22.80|
Info: 41769 | 16898 24871 | 245 525 | 0| 0.40 23.20|
Info: Routing complete.
Info: Router1 time 23.20s
Info: Checksum: 0xd528f9e4
Info: Critical path report for clock 'clk_sys' (posedge -> posedge):
Info: curr total
Info: 1.4 1.4 Source soc_I.cpu_I.latched_stalu_SB_DFFESR_Q_conv_LC.O
Info: 3.0 4.3 Net soc_I.cpu_I.latched_stalu budget 0.000000 ns (8,17) -> (5,15)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_29_I2_SB_LUT4_O_LC.I3
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1182.6-1182.19
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: 0.9 5.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_29_I2_SB_LUT4_O_LC.O
Info: 3.0 8.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_29_I2[0] budget 0.000000 ns (5,15) -> (7,16)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_29_I2_SB_LUT4_I0_LC.I0
Info: Defined in:
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info: 1.3 9.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_29_I2_SB_LUT4_I0_LC.O
Info: 1.8 11.2 Net soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1] budget 1.496000 ns (7,16) -> (7,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_19_LC.I1
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1539.21-1539.60
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.7 11.9 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_19_LC.COUT
Info: 0.0 11.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[2] budget 0.000000 ns (7,17) -> (7,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_8_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 12.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_8_LC.COUT
Info: 0.0 12.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[3] budget 0.000000 ns (7,17) -> (7,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_6_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 12.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_6_LC.COUT
Info: 0.0 12.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[4] budget 0.000000 ns (7,17) -> (7,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_5_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 12.7 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_5_LC.COUT
Info: 0.0 12.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[5] budget 0.000000 ns (7,17) -> (7,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_4_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 13.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_4_LC.COUT
Info: 0.0 13.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[6] budget 0.000000 ns (7,17) -> (7,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_3_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 13.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_3_LC.COUT
Info: 0.0 13.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[7] budget 0.000000 ns (7,17) -> (7,17)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_2_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 13.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_2_LC.COUT
Info: 0.6 14.1 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[8] budget 0.560000 ns (7,17) -> (7,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_1_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 14.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_1_LC.COUT
Info: 0.0 14.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[9] budget 0.000000 ns (7,18) -> (7,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 14.7 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_LC.COUT
Info: 0.0 14.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[10] budget 0.000000 ns (7,18) -> (7,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_29_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 14.9 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_29_LC.COUT
Info: 0.0 14.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[11] budget 0.000000 ns (7,18) -> (7,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_28_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 15.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_28_LC.COUT
Info: 0.0 15.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[12] budget 0.000000 ns (7,18) -> (7,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_27_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 15.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_27_LC.COUT
Info: 0.0 15.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[13] budget 0.000000 ns (7,18) -> (7,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_26_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 15.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_26_LC.COUT
Info: 0.0 15.8 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[14] budget 0.000000 ns (7,18) -> (7,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_25_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 16.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_25_LC.COUT
Info: 0.0 16.1 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[15] budget 0.000000 ns (7,18) -> (7,18)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_24_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 16.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_24_LC.COUT
Info: 0.6 16.9 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[16] budget 0.560000 ns (7,18) -> (7,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_23_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 17.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_23_LC.COUT
Info: 0.0 17.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[17] budget 0.000000 ns (7,19) -> (7,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_22_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 17.4 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_22_LC.COUT
Info: 0.0 17.4 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[18] budget 0.000000 ns (7,19) -> (7,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_21_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 17.7 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_21_LC.COUT
Info: 0.0 17.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[19] budget 0.000000 ns (7,19) -> (7,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_20_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 18.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_20_LC.COUT
Info: 0.0 18.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[20] budget 0.000000 ns (7,19) -> (7,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_18_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 18.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_18_LC.COUT
Info: 0.0 18.3 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[21] budget 0.000000 ns (7,19) -> (7,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_17_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 18.6 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_17_LC.COUT
Info: 0.0 18.6 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[22] budget 0.000000 ns (7,19) -> (7,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_16_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 18.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_16_LC.COUT
Info: 0.0 18.8 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[23] budget 0.000000 ns (7,19) -> (7,19)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_15_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 19.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_15_LC.COUT
Info: 0.6 19.7 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[24] budget 0.560000 ns (7,19) -> (7,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_14_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 20.0 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_14_LC.COUT
Info: 0.0 20.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[25] budget 0.000000 ns (7,20) -> (7,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_13_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 20.2 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_13_LC.COUT
Info: 0.0 20.2 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[26] budget 0.000000 ns (7,20) -> (7,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_12_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 20.5 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_12_LC.COUT
Info: 0.0 20.5 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[27] budget 0.000000 ns (7,20) -> (7,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_11_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 20.8 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_11_LC.COUT
Info: 0.0 20.8 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[28] budget 0.000000 ns (7,20) -> (7,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_10_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 21.1 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_10_LC.COUT
Info: 0.0 21.1 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[29] budget 0.000000 ns (7,20) -> (7,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_9_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 21.3 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_9_LC.COUT
Info: 0.7 22.0 Net soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO[30] budget 0.660000 ns (7,20) -> (7,20)
Info: Sink soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_7_LC.I3
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.9 22.9 Source soc_I.cpu_I.cpuregs.wdata_SB_LUT4_O_30_I2_SB_LUT4_I1_O_SB_CARRY_I0_CO_SB_LUT4_I3_7_LC.O
Info: 3.0 25.8 Net soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_29_D_SB_LUT4_O_I0[30] budget 2.470000 ns (7,20) -> (10,23)
Info: Sink soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_LC.I0
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/common/rtl/picorv32.v:1548.22-1548.49
Info: /build/gateware/common/rtl/soc_base.v:210.4-220.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:33.26-33.27
Info: 1.3 27.1 Source soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_LC.O
Info: 3.0 30.1 Net soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_I1[0] budget 3.260000 ns (10,23) -> (8,22)
Info: Sink soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_LC.I1
Info: Defined in:
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info: 1.2 31.2 Setup soc_I.cpu_I.reg_next_pc_SB_DFFESR_Q_D_SB_LUT4_O_LC.I1
Info: 15.3 ns logic, 15.9 ns routing
Info: Critical path report for clock 'clk_48m' (posedge -> posedge):
Info: curr total
Info: 1.2 1.2 Source soc_I.usb_I.trans_I.mc_rom_I_RAM.RDATA_6
Info: 3.1 4.2 Net soc_I.usb_I.trans_I.mc_opcode[6] budget 1.996000 ns (19,11) -> (18,10)
Info: Sink soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_1_LC.I1
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:91.14-91.23
Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3
Info: 1.2 5.5 Source soc_I.usb_I.trans_I.mc_match_bits_SB_LUT4_O_1_LC.O
Info: 1.8 7.2 Net soc_I.usb_I.trans_I.mc_match_bits[2] budget 0.884000 ns (18,10) -> (18,10)
Info: Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.I2
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:85.32-85.45
Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3
Info: 1.2 8.4 Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0_SB_LUT4_O_LC.O
Info: 1.8 10.2 Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_I0[0] budget 1.089000 ns (18,10) -> (18,11)
Info: Sink soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.I0
Info: Defined in:
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info: 1.3 11.5 Source soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_LC.O
Info: 1.8 13.2 Net soc_I.usb_I.trans_I.mc_rst_n_SB_LUT4_I3_O[0] budget 1.273000 ns (18,11) -> (17,12)
Info: Sink soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.I2
Info: Defined in:
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info: 1.2 14.4 Source soc_I.usb_I.trans_I.mc_pc_SB_LUT4_O_7_LC.O
Info: 1.8 16.2 Net soc_I.usb_I.trans_I.mc_pc[0] budget 1.089000 ns (17,12) -> (17,11)
Info: Sink $nextpnr_ICESTORM_LC_201.I1
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.7 16.9 Source $nextpnr_ICESTORM_LC_201.COUT
Info: 0.0 16.9 Net $nextpnr_ICESTORM_LC_201$O budget 0.000000 ns (17,11) -> (17,11)
Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.CIN
Info: 0.3 17.2 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_6_LC.COUT
Info: 0.0 17.2 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[2] budget 0.000000 ns (17,11) -> (17,11)
Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 17.4 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_5_LC.COUT
Info: 0.0 17.4 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[3] budget 0.000000 ns (17,11) -> (17,11)
Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 17.7 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_4_LC.COUT
Info: 0.0 17.7 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[4] budget 0.000000 ns (17,11) -> (17,11)
Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 18.0 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_3_LC.COUT
Info: 0.0 18.0 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[5] budget 0.000000 ns (17,11) -> (17,11)
Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 18.3 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_2_LC.COUT
Info: 0.0 18.3 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[6] budget 0.000000 ns (17,11) -> (17,11)
Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.CIN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.3 18.5 Source soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_1_LC.COUT
Info: 0.7 19.2 Net soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_I3[7] budget 0.660000 ns (17,11) -> (17,11)
Info: Sink soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/cores/no2usb//rtl/usb.v:295.12-336.3
Info: /build/gateware/cores/no2usb//rtl/usb_trans.v:179.17-179.26
Info: /build/gateware/common/rtl/soc_base.v:373.4-393.3
Info: /opt/fpga-toolchain/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
Info: 0.8 20.0 Setup soc_I.usb_I.trans_I.mc_pc_nxt_SB_DFFR_Q_D_SB_LUT4_O_LC.I3
Info: 9.3 ns logic, 10.8 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge clk_sys':
Info: curr total
Info: 0.0 0.0 Source spi_mux_I.iob_I[2].D_IN_0
Info: 8.2 8.2 Net flash_miso_i budget 31.052000 ns (23,0) -> (0,0)
Info: Sink soc_I.spi_I.spi_I.MI
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:371.4-397.3
Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:32.14-32.24
Info: 1.5 9.7 Setup soc_I.spi_I.spi_I.MI
Info: 1.5 ns logic, 8.2 ns routing
Info: Critical path report for cross-domain path 'posedge clk_48m' -> '<async>':
Info: curr total
Info: 1.4 1.4 Source soc_I.usb_I.pad_pu_SB_DFFSR_Q_DFFLC.O
Info: 3.1 4.4 Net usb_pu$SB_IO_OUT budget 81.943001 ns (17,7) -> (17,0)
Info: Sink usb_pu$sb_io.D_OUT_0
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:39.14-39.20
Info: 1.4 ns logic, 3.1 ns routing
Info: Critical path report for cross-domain path 'posedge clk_48m' -> 'posedge clk_sys':
Info: curr total
Info: 1.4 1.4 Source soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_11_LC.O
Info: 4.1 5.5 Net soc_I.wb_48m_xclk_I.m_rdata_i[4] budget 29.927999 ns (18,2) -> (12,7)
Info: Sink soc_I.wb_48m_xclk_I.s_rdata_SB_DFFSR_Q_11_DFFLC.I0
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/cores/no2misc//rtl/xclk_wb.v:53.15-53.24
Info: /build/gateware/common/rtl/soc_base.v:399.4-415.3
Info: 1.2 6.8 Setup soc_I.wb_48m_xclk_I.s_rdata_SB_DFFSR_Q_11_DFFLC.I0
Info: 2.6 ns logic, 4.1 ns routing
Info: Critical path report for cross-domain path 'posedge clk_sys' -> '<async>':
Info: curr total
Info: 1.5 1.5 Source soc_I.spi_I.spi_I.MOE
Info: 8.3 9.8 Net flash_mosi_oe budget 40.313999 ns (0,0) -> (21,1)
Info: Sink spi_mux_I.sio_mosi_oe_SB_LUT4_O_LC.I2
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:371.4-397.3
Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:30.14-30.25
Info: 1.2 11.0 Source spi_mux_I.sio_mosi_oe_SB_LUT4_O_LC.O
Info: 3.0 13.9 Net spi_mux_I.sio_mosi_oe budget 38.368999 ns (21,1) -> (23,0)
Info: Sink spi_mux_I.iob_I[3].OUTPUT_ENABLE
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:371.4-397.3
Info: /build/gateware/icE1usb/rtl/sr_btn_if.v:88.19-88.30
Info: 2.7 ns logic, 11.2 ns routing
Info: Critical path report for cross-domain path 'posedge clk_sys' -> 'posedge clk_48m':
Info: curr total
Info: 1.4 1.4 Source soc_I.cpu_I.mem_wstrb_SB_DFFE_Q_3_conv_LC.O
Info: 1.8 3.2 Net wb_wmsk[0] budget 2.711000 ns (10,10) -> (10,9)
Info: Sink gps_uart_I.wb_we_SB_LUT4_O_LC.I0
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:94.18-94.25
Info: 1.3 4.4 Source gps_uart_I.wb_we_SB_LUT4_O_LC.O
Info: 3.6 8.0 Net wb_we budget 5.258000 ns (10,9) -> (13,4)
Info: Sink soc_I.wb_48m_xclk_I.m_ack_SB_LUT4_O_LC.I1
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:95.18-95.23
Info: 1.2 9.3 Source soc_I.wb_48m_xclk_I.m_ack_SB_LUT4_O_LC.O
Info: 3.7 13.0 Net soc_I.ub_ack budget 4.016000 ns (13,4) -> (13,11)
Info: Sink soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_3_LC.CEN
Info: Defined in:
Info: /build/gateware/icE1usb/rtl/top.v:150.4-190.3
Info: /build/gateware/cores/no2misc//rtl/xclk_wb.v:107.14-113.3
Info: /build/gateware/cores/no2misc//rtl/xclk_strobe.v:18.14-18.20
Info: /build/gateware/common/rtl/soc_base.v:399.4-415.3
Info: 0.1 13.1 Setup soc_I.wb_48m_xclk_I.m_rdata_SB_LUT4_O_3_LC.CEN
Info: 4.0 ns logic, 9.1 ns routing
Info: Max frequency for clock 'clk_sys': 32.01 MHz (PASS at 30.72 MHz)
Info: Max frequency for clock 'clk_48m': 49.92 MHz (PASS at 48.00 MHz)
Info: Max delay <async> -> posedge clk_sys: 9.74 ns
Info: Max delay posedge clk_48m -> <async> : 4.45 ns
Info: Max delay posedge clk_48m -> posedge clk_sys: 6.77 ns
Info: Max delay posedge clk_sys -> <async> : 13.92 ns
Info: Max delay posedge clk_sys -> posedge clk_48m: 13.11 ns
Info: Slack histogram:
Info: legend: * represents 55 endpoint(s)
Info: + represents [1,55) endpoint(s)
Info: [ 802, 4772) |+
Info: [ 4772, 8742) |***+
Info: [ 8742, 12712) |**********+
Info: [ 12712, 16682) |***************************+
Info: [ 16682, 20652) |****************+
Info: [ 20652, 24622) |*******************************************+
Info: [ 24622, 28592) |************************************************************
Info: [ 28592, 32562) |*+
Info: [ 32562, 36532) |
Info: [ 36532, 40502) |
Info: [ 40502, 44472) |
Info: [ 44472, 48442) |
Info: [ 48442, 52412) |
Info: [ 52412, 56382) |
Info: [ 56382, 60352) |
Info: [ 60352, 64322) |
Info: [ 64322, 68292) |
Info: [ 68292, 72262) |+
Info: [ 72262, 76232) |+
Info: [ 76232, 80202) |+
4 warnings, 0 errors
icepack -s /build/gateware/icE1usb/build-tmp/icE1usb.asc /build/gateware/icE1usb/build-tmp/icE1usb.bin
make: Leaving directory '/build/gateware/icE1usb'
$ ssh-agent -k
unset SSH_AUTH_SOCK;
unset SSH_AGENT_PID;
echo Agent pid 4188407 killed;
[ssh-agent] Stopped.
Archiving artifacts
‘**/core’ doesn’t match anything: ‘**’ exists but not ‘**/core’
No artifacts found that match the file pattern "**/core, **/testsuite.log, **/workspace.tar.xz". Configuration error?
Finished: SUCCESS
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