When running ttcn3-bts-test, parameters such as SETTA, FAKE_RSSI, FAKE_TOA, and others may persist across testcases if not explicitly reset, leading to unintended cross-test interference.
Reset all transceiver settings on CMD POWEROFF to ensure proper test isolation and predictable behavior between testcases.
Change-Id: I5c58bc684acc7a58d7aa940bb2ae7597d4a282f2 (cherry picked from commit 754d5ebb1e120e661fd3b1e025abfc5b5216ac80)
When running ttcn3-bts-test, parameters such as SETTA, FAKE_RSSI, FAKE_TOA, and others may persist across testcases if not explicitly reset, leading to unintended cross-test interference.
Reset all transceiver settings on CMD POWEROFF to ensure proper test isolation and predictable behavior between testcases.
trxcon/l1sched: pre-populate MR cache during lchan allocation
Instead of checking if the MR cache is populated in prim_compose_mr() and populating it there, let's do this during lchan allocation. Take a chance to move lchan allocation logic into its own function.
trxcon/fsm: handle_dch_est_req(): do not reset the scheduler
Calling l1sched_reset() results in resetting the UL SACCH cache, that may have been populated prior to sending L1CTL_DM_EST_REQ. Instead, do what the comment says - call l1sched_del_all_ts().
trxcon/fsm: handle_dch_est_req(): do not reset the scheduler
Calling l1sched_reset() results in resetting the UL SACCH cache, that may have been populated prior to sending L1CTL_DM_EST_REQ. Instead, do what the comment says - call l1sched_del_all_ts().
trxcon/l1sched: pre-populate MR cache during lchan allocation
Instead of checking if the MR cache is populated in prim_compose_mr() and populating it there, let's do this during lchan allocation. Take a chance to move lchan allocation logic into its own function.
