Skip to content
Sign in
Success

Changes

Summary

  1. trxcon/l1ctl: print an error for uhnandled DATA.req / TRAFFIC.req (details)
  2. trxcon/l1sched: add API for reading/updating UL SACCH cache (details)
  3. trxcon/l1sched: pre-populate MR cache during lchan allocation (details)
  4. trxcon/l1sched: l1sched_reset(): remove unused param (details)
  5. trxcon/l1sched: l1sched_reset(): also reset bsic (details)
  6. trxcon/l1sched: add and use l1sched_del_all_ts() (details)
  7. trxcon/fsm: handle_dch_est_req(): do not reset the scheduler (details)
Commit a2ffdf46b29208cae639d90f994867126c54224b by Vadim Yanitskiy
trxcon/l1ctl: print an error for uhnandled DATA.req / TRAFFIC.req

Change-Id: I1d965c2882eb72dc845bea85a4ffaa26d37cee05
The file was modifiedsrc/host/trxcon/src/l1ctl.c
Commit 335ae654d8f197e2023de0ea32e810e94613df15 by Vadim Yanitskiy
trxcon/l1sched: add API for reading/updating UL SACCH cache

Change-Id: Ica42dbc28cfdd7af2e1becdcc5d45337b70da8a7
Related: 15877ba05 ("trxcon: allow populating global SACCH cache via L1CTL")
The file was modifiedsrc/host/trxcon/src/sched_prim.c
The file was modifiedsrc/host/trxcon/src/sched_trx.c
The file was modifiedsrc/host/trxcon/src/trxcon_fsm.c
The file was modifiedsrc/host/trxcon/include/osmocom/bb/l1sched/l1sched.h
Commit 7a18c273659e891737c362476778010448875a06 by Vadim Yanitskiy
trxcon/l1sched: pre-populate MR cache during lchan allocation

Instead of checking if the MR cache is populated in prim_compose_mr()
and populating it there, let's do this during lchan allocation.  Take
a chance to move lchan allocation logic into its own function.

Change-Id: I079074a402f9c27fff7e25b49bfd1dd409c0f8c3
The file was modifiedsrc/host/trxcon/src/sched_trx.c
The file was modifiedsrc/host/trxcon/src/sched_prim.c
Commit d3c4d88ae9f9016a02dabaf54201c7f40400a0f7 by Vadim Yanitskiy
trxcon/l1sched: l1sched_reset(): remove unused param

The l1sched no longer has its own clock source, so there's nothing
to reset.  This parameter is no-op and can be safely removed.

Change-Id: I88dfa8770c9cd205006f569315b07f4d91cc08de
The file was modifiedsrc/host/trxcon/include/osmocom/bb/l1sched/l1sched.h
The file was modifiedsrc/host/trxcon/src/sched_trx.c
The file was modifiedsrc/host/trxcon/src/trxcon_fsm.c
Commit 25e2dbc4d46e5803bbd140a2b72b1320cca96f85 by Vadim Yanitskiy
trxcon/l1sched: l1sched_reset(): also reset bsic

Change-Id: I4dfe5663fac12548d33393fe3b1426e5d80f50e7
Related: 8428b1ea0 ("trxcon: abstract out the scheduler API from L1CTL/TRXD/TRXC")
The file was modifiedsrc/host/trxcon/src/sched_trx.c
Commit 4618071659e536da18db979ad52bfa3d3f2e0423 by Vadim Yanitskiy
trxcon/l1sched: add and use l1sched_del_all_ts()

Change-Id: I35ce97459dcd0e2cac4ab8927f02fe0232aa6142
The file was modifiedsrc/host/trxcon/include/osmocom/bb/l1sched/l1sched.h
The file was modifiedsrc/host/trxcon/src/sched_trx.c
Commit dd5c263ae05795966435b9d1a1e563957db793b8 by Vadim Yanitskiy
trxcon/fsm: handle_dch_est_req(): do not reset the scheduler

Calling l1sched_reset() results in resetting the UL SACCH cache,
that may have been populated prior to sending L1CTL_DM_EST_REQ.
Instead, do what the comment says - call l1sched_del_all_ts().

Change-Id: Iff03fa5b90ac1ec30b7937cea6bd09c6ececb5f6
Fixes: c6fe9c3f ("trxcon: trxcon_fsm: permit loop [P]DCH transitions")
Related: 15877ba05 ("trxcon: allow populating global SACCH cache via L1CTL")
Related: OS#6919
The file was modifiedsrc/host/trxcon/src/trxcon_fsm.c